CN110428859A - Nonvolatile memory and its manufacturing method - Google Patents
Nonvolatile memory and its manufacturing method Download PDFInfo
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- CN110428859A CN110428859A CN201910728547.6A CN201910728547A CN110428859A CN 110428859 A CN110428859 A CN 110428859A CN 201910728547 A CN201910728547 A CN 201910728547A CN 110428859 A CN110428859 A CN 110428859A
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Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
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- Microelectronics & Electronic Packaging (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
The present invention relates to a kind of nonvolatile memory and its manufacturing methods.The nonvolatile memory includes memory cell array and the intermediate selecting pipe of going here and there not with storage unit.Memory cell array includes multiple storage strings, and each storage string includes concatenated first substring and the second substring, and first substring and the second substring respectively include multiple storage units.Centre string selecting pipe, is connected between first substring and second substring.The present invention connects the intermediate selecting pipe of going here and there without storage unit between storage string, during programming, by applying higher voltage to centre string selecting pipe, the groove potential of non-selected storage unit can be improved, reduce interference of the programming operation to non-selected storage unit.
Description
Technical field
The present invention relates to the technical field of semiconductor devices more particularly to a kind of nonvolatile memory and its manufacturers
Method.
Background technique
With the development of technology, smaller and smaller to the size requirement of electronic product, while volume is proposed to memory device
The requirement of small high capacity.Nonvolatile memory can keep stored data in power breakdown.It is non-volatile in order to improve
The integrated level of property memory, proposes the 3D nonvolatile semiconductor memory member by storage unit from silicon substrate stacked vertical.
For the 3D NAND type nonvolatile memory of vertical channel structure, there is dielectric layer and grid layer to replace
Stack the stack architecture formed and the channel hole through the stack architecture.With the increase of stacking number, deep hole is etched increasingly
It is difficult.Common practice is vertically to connect two or more stack architectures, forms the stack architecture of more layers.In
It is connected between different stack architectures with oxide layer, primary pad product then is carried out to the functional layer inside channel hole again.Functional layer
Common pad product sequence is followed successively by barrier layer, accumulation layer and tunnel layer from channel hole side wall to channel hole center, then pads product conduction
Layer.Since multiple stack architectures connect, the channel hole to be formed is very deep, the thickness meeting of the functional layer by once padding product formation
It is inconsistent up and down, and the consistency of each layer component can be poor, thus causes the electric property of memory poor.Another party
Face, due to increasing for the number of plies, programming interference problem of the nonvolatile memory with multiple stack architectures in programming phases
It can be more serious.
Summary of the invention
Technical problem to be solved by the invention is to provide a kind of preferable nonvolatile memories of functional layer consistency, can
To reduce programming interference.
The present invention to solve above-mentioned technical problem and the technical solution adopted is that propose a kind of nonvolatile memory, including
Memory cell array and intermediate selecting pipe of going here and there not with storage unit.Memory cell array includes multiple storage strings, Mei Gecun
Storage string includes concatenated first substring and the second substring, and first substring and the second substring respectively include multiple storage units.
Centre string selecting pipe, is connected between first substring and second substring.
In one embodiment of this invention, above-mentioned nonvolatile memory further includes controller, is configured that in the programming phase
Between, it chooses storage unit to apply program voltage each storage string, the first conducting voltage is applied to non-selected storage unit, and
Second conducting voltage is applied to the intermediate string selecting pipe, wherein at least part period during the programming, described the
Two conducting voltages are greater than first conducting voltage.
In one embodiment of this invention, the waveform of second conducting voltage is identical as the waveform of the program voltage,
And second conducting voltage and the ratio of the program voltage are between 0.9~1.1.
In one embodiment of this invention, the waveform phase of the waveform of second conducting voltage and first conducting voltage
Together, and second conducting voltage and the ratio of the program voltage are less than or equal to 1.1.
In one embodiment of this invention, above-mentioned nonvolatile memory further include: the first string selecting pipe is connected to institute
State one end that the first substring is not connect with the intermediate string selecting pipe；Second string selecting pipe, be connected to second substring not with
One end of the intermediate string selecting pipe connection；Wherein during the programming, shutdown voltage is applied to the first string selecting pipe,
Cut-in voltage is applied to the second string selecting pipe.
In one embodiment of this invention, above-mentioned nonvolatile memory further includes connecting with the first string selecting pipe
Common source end；And the drain terminal being connect with the second string selecting pipe；Wherein during the programming, the common source end is applied
Ground voltage applies shutdown voltage to the drain terminal.
The present invention also proposes a kind of operating method of nonvolatile memory, and the nonvolatile memory includes that storage is single
Element array and selecting pipe is gone here and there not with the intermediate of storage unit, the memory cell array includes multiple storage strings, each storage
String includes concatenated first substring and the second substring, and first substring and the second substring respectively include multiple storage units, institute
Intermediate string selecting pipe is stated, is connected between first substring and second substring, the method comprise the steps that in the programming phase
Between, it chooses storage unit to apply program voltage each storage string, the first conducting voltage is applied to non-selected storage unit, and
Second conducting voltage is applied to the intermediate string selecting pipe, wherein at least part period during the programming, described the
Two conducting voltages are greater than first conducting voltage.
The present invention also proposes a kind of nonvolatile memory, including stack layer and memory cell array.Stack layer includes heap
Folded the first storehouse and the second storehouse and the articulamentum between first storehouse and the second storehouse, first storehouse
The grid layer being alternately stacked and dielectric layer are respectively included with the second storehouse.Memory cell array includes multiple storage strings, Mei Gecun
Storage string includes the first substring and the second substring, and first substring extends vertically through first storehouse, and second substring is vertical
Through second storehouse, first substring includes the first channel layer, and second substring includes the second channel layer, and described the
One channel layer is electrically connected second channel layer；Wherein the articulamentum is on the extending direction of the stack layer with described
The channel interconnecting piece of one channel layer and second channel layer is opposite, and is Jie between the articulamentum and the channel interconnecting piece
Matter layer.
In one embodiment of this invention, first substring includes the first charge storage layer, and second substring includes
Second charge storage layer, wherein first charge storage layer and second charge storage layer do not extend into the articulamentum with
Region between the channel interconnecting piece.
In one embodiment of this invention, the channel interconnecting piece of first channel layer and second channel layer is hollow
Column or solid cylindrical.
In one embodiment of this invention, the articulamentum and the channel interconnecting piece are constituted not in storage unit
Between go here and there selecting pipe, be electrically connected between first substring and second substring.
In one embodiment of this invention, above-mentioned nonvolatile memory further includes controller, is configured that in the programming phase
Between, it chooses storage unit to apply program voltage each storage string, the first conducting voltage is applied to non-selected storage unit, and
Second conducting voltage is applied to the intermediate string selecting pipe, wherein at least part period during the programming, described the
Two conducting voltages are greater than first conducting voltage.
In one embodiment of this invention, the waveform of second conducting voltage is identical as the waveform of the program voltage,
And second conducting voltage and the ratio of the program voltage are between 0.9~1.1.
In one embodiment of this invention, the waveform phase of the waveform of second conducting voltage and first conducting voltage
Together, and second conducting voltage and the program voltage are less than or equal to 1.1.
The present invention also proposes a kind of manufacturing method of nonvolatile memory, comprising the following steps: forms the first storehouse, institute
Stating the first storehouse includes the first material layer and second material layer being alternately stacked；Formation extends vertically through the first of first storehouse
Substring, first substring include the first channel layer；Articulamentum is formed on first storehouse；It is formed on the articulamentum
Second storehouse, second storehouse include the first material layer and second material layer being alternately stacked；And it is formed and extends vertically through institute
State the second substring of the second storehouse, second substring includes the second channel layer, and first channel layer is electrically connected described the
Two channel layers, wherein extending direction of the channel interconnecting piece of first channel layer and second channel layer in the stack layer
It is upper opposite with the articulamentum, and be dielectric layer between the channel interconnecting piece and the articulamentum；Wherein first material
Layer is grid layer or dummy gate layer, and the second material layer is dielectric layer.
In one embodiment of this invention, first substring further includes the first charge storage layer, and second substring is also
Including the second charge storage layer, wherein first charge storage layer and second charge storage layer do not extend into the connection
Region between layer and the channel interconnecting piece.
It in one embodiment of this invention, further include being formed described in contact after forming articulamentum on first storehouse
The channel interconnecting piece of first channel layer；And when forming second substring, second channel layer contacts the channel interconnecting piece.
In one embodiment of this invention, the channel interconnecting piece is open column shape or solid cylindrical.
In one embodiment of this invention, the articulamentum and the channel interconnecting piece are constituted not in storage unit
Between go here and there selecting pipe, be electrically connected between first substring and second substring.
Technical solution of the present invention connects the intermediate string selecting pipe without storage unit between storage string, in the programming phase
Between, by applying higher voltage to centre string selecting pipe, the groove potential of non-selected storage unit can be improved, reduce and compile
Journey operates the interference to non-selected storage unit；The manufacturing method of nonvolatile memory according to the present invention is respectively formed every
Functional layer and conductivity channel layer in a storehouse improve the uniformity up and down and consistency of functional layer and conductivity channel layer.
Detailed description of the invention
For the above objects, features and advantages of the present invention can be clearer and more comprehensible, below in conjunction with attached drawing to tool of the invention
Body embodiment elaborates, in which:
Figure 1A is the structural schematic diagram for forming the 3D nand memory of functional layer by once padding product；
Figure 1B is the circuit diagram of memory shown in Figure 1A；
Fig. 1 C is the program timing sequence schematic diagram of memory shown in Figure 1A；
Fig. 2A is the structural schematic block diagram of the nonvolatile memory of one embodiment of the invention；
Fig. 2 B is the circuit diagram of the storage string in the nonvolatile memory of one embodiment of the invention；
Fig. 3 A and 3B are the program timing sequence schematic diagrames of the nonvolatile memory of one embodiment of the invention；
Fig. 4 A is the structural schematic diagram of the nonvolatile memory of one embodiment of the invention；
Fig. 4 B is the structural schematic diagram of the nonvolatile memory of another embodiment of the present invention；
Fig. 5 is the exemplary process diagram of the manufacturing method of the nonvolatile memory of one embodiment of the invention；
Fig. 6 A be the nonvolatile memory of one embodiment of the invention manufacturing method in form the process of the first storehouse and show
It is intended to；
Fig. 6 B and Fig. 6 C be the nonvolatile memory of one embodiment of the invention manufacturing method in form the first substring
Process schematic；
Fig. 6 D and 6E are the processes that articulamentum is formed in the manufacturing method of the nonvolatile memory of one embodiment of the invention
Schematic diagram；
Fig. 6 F be the nonvolatile memory of one embodiment of the invention manufacturing method in form the process of the second storehouse and show
It is intended to；
Fig. 7 A-7C be the nonvolatile memory of one embodiment of the invention manufacturing method in form the process of the second substring
Schematic diagram；
Fig. 8 A-8C be the nonvolatile memory of another embodiment of the present invention manufacturing method in form the mistake of the second substring
Journey schematic diagram.
Specific embodiment
For the above objects, features and advantages of the present invention can be clearer and more comprehensible, below in conjunction with attached drawing to tool of the invention
Body embodiment elaborates.
In the following description, numerous specific details are set forth in order to facilitate a full understanding of the present invention, but the present invention can be with
It is different from other way described herein using other and implements, therefore the present invention is by the limit of following public specific embodiment
System.
As shown in the application and claims, unless context clearly prompts exceptional situation, " one ", "one", " one
The words such as kind " and/or "the" not refer in particular to odd number, may also comprise plural number.It is, in general, that term " includes " only prompts to wrap with "comprising"
Include clearly identify the step of and element, and these steps and element do not constitute one it is exclusive enumerate, method or apparatus
The step of may also including other or element.
When describing the embodiments of the present invention, for purposes of illustration only, indicating that the sectional view of device architecture can disobey general proportion work
Partial enlargement, and the schematic diagram is example, should not limit the scope of protection of the invention herein.In addition, in practical system
It should include the three-dimensional space of length, width and depth in work.
For the convenience of description, herein may use such as " under ", " lower section ", " being lower than ", " following ", " top ", "upper"
Etc. spatial relationship word the relationships of an elements or features shown in the drawings and other elements or feature described.It will reason
Solve, these spatial relationship words be intended to encompass in use or device in operation, other than the direction described in attached drawing
Other directions.For example, being described as be in other elements or feature " below " or " under " if overturning the device in attached drawing
Or the direction of the element of " following " will be changed to " top " in the other elements or feature.Thus, illustrative word " under
Side " and " following " can include upper and lower both direction.Device may also have other directions (to be rotated by 90 ° or in its other party
To), therefore spatial relation description word used herein should be interpreted accordingly.In addition, it will also be understood that being referred to as when one layer at two layers
" between " when, it can be only layer between described two layers, or there may also be one or more intervenient layers.
In the context of this application, structure of the described fisrt feature in the "upper" of second feature may include first
Be formed as the embodiment directly contacted with second feature, also may include that other feature is formed between the first and second features
Embodiment, such first and second feature may not be direct contact.
It is referred to as " on the other part " it should be appreciated that working as a component, " being connected to another component ", " is coupled in
When another component " or " contacting another component ", it can directly on another component, be connected or coupled to,
Or another component is contacted, or may exist insertion part.In contrast, when a component is referred to as " directly another
On a component ", " being directly connected in ", " being coupled directly to " or when " directly contact " another component, insertion part is not present.Together
Sample, when first component referred to as " is in electrical contact " or " being electrically coupled to " second component, in the first component and this second
There is the power path for allowing electric current flowing between part.The power path may include capacitor, the inductor of coupling and/or permission electricity
Other components of flowing, or even do not contacted directly between conductive component.
Flow chart has been used to be used to illustrate operation performed by manufacturing method according to an embodiment of the present invention in this application.
It should be understood that the operation of front not necessarily accurately carries out in sequence.On the contrary, can be handled according to inverted order or simultaneously
Various steps.Meanwhile or during other operations are added to these, or from these processes remove a certain step or number step operation.
Figure 1A is the structural schematic diagram for forming the 3D nand memory of functional layer by once padding product.With reference to shown in Figure 1A,
The memory is made of two stack architectures, is push-down stack 110 and upper storehouse 120 respectively.Each stack architecture includes
By first material layer 141 and the alternately stacked lamination of second material layer 142.
First material layer 141 and second material layer 142 can be selected from following material and include at least a kind of insulation Jie
Matter, such as silicon nitride, silica, amorphous carbon, diamond-like amorphous carbon, germanium oxide, aluminium oxide etc. and combinations thereof.First material
Layer 141 and second material layer 142 have different Etch selectivities.Such as it can be the combination of silicon nitride and silica, oxidation
Silicon and undoped polysilicon or combination, silicon oxide or silicon nitride and the combination of amorphous carbon of amorphous silicon etc..The of stack architecture
The deposition method of one material layer 141 and second material layer 142 may include chemical vapor deposition (CVD, PECVD, LPCVD,
HDPCVD), atomic layer deposition (ALD) or physical gas-phase deposite method such as molecular beam epitaxy (MBE), thermal oxide, evaporation, sputtering
Deng its various method.One layer in first material layer 141 and second material layer 142 can be used as grid sacrificial layer, such as nitrogenize
Silicon layer.Lamination as grid sacrificial layer can also be other conductive layers, such as tungsten, cobalt, nickel etc..Not as grid sacrifice
Another material layer of layer can be the dielectric material of such as silica, such as aluminium oxide, hafnium oxide, tantalum oxide etc..In the present invention
Embodiment in, stack architecture can by as grid sacrificial layer material and oxide skin(coating) be alternatively formed, can also be by metal
Layer and oxide skin(coating) are alternatively formed.
The channel hole 150 for being used to form storage unit is also formed in each stack architecture.It can be in stack architecture
Cooperate corresponding etching technics using photomask to form channel hole 150.Figure 1A is not limited to the shape in channel hole, position
And quantity.In fact, multiple channel holes through its laminated construction can be formed in stack architecture.
Upper storehouse 120 is located at the top of push-down stack 110, therebetween with the connection of oxide layer 130.The channel of upper storehouse 120
Hole and the channel hole of push-down stack 110 are mutually aligned, and form new channel hole 150.Due to the limitation of technique and the height in channel hole
Depth-to-width ratio, being formed by channel hole 150 in practice is not diameter consistent cylindrical hole up and down, but above aperture it is big,
Aperture is small below.In the channel hole 150 pad product functional layer, the functional layer include from channel hole side wall to channel hole center successively
Pad barrier layer 154, electric charge capture layer 153, tunnel layer 152 and the conductive layer 151 of product.With reference to shown in Figure 1A, the function that is formed in this way
Distribution is inconsistent up and down in channel hole 150 for ergosphere, will affect the electric property of the memory.
Figure 1B is the circuit diagram of memory shown in Figure 1A.It include two in the memory circuit with reference to shown in Figure 1B
Memory cell group is the first memory cell group 160 and the second memory cell group 170 respectively.First memory cell group 160 corresponds to
Push-down stack 110 in Figure 1A, the second memory cell group 170 correspond to the upper storehouse 120 in Figure 1A.In each memory cell group
It all include multiple storage units (Memory Cell, MC) and multiple dummy memory cells (Dummy Memory Cell, DMC).Its
In, it further include lower selecting pipe (the Bottom Select for being connected to source (Source) in the first memory cell group 160
Transistor, BST), it further include the upper selecting pipe for being connected to drain terminal (Drain) in the second memory cell group 170
(TopSelect Transistor,TST).Dummy memory cells have the structure similar with storage unit, but single not as storage
Member uses.
With reference to shown in Figure 1B, the first memory cell group 160 is by being located at the drain terminals and the of the dummy memory cells of its edge
The source that two memory cell groups 170 are located at the dummy memory cells of its edge is connected with each other.
Fig. 1 C is the program timing sequence schematic diagram of memory shown in Figure 1A.With reference to shown in Fig. 1 C, in programming operation, by multiple
As the memory of stack architecture composition with the memory of single stack architecture is.In the time diagram, from dotted line mark
The programming phases of memory are initially entered at note.In the programming phases, storage unit (Selected Memory is being chosen
Cell, SMC) grid on apply program voltage Vpgm, non-selected storage unit (UnSelected Memory Cell,
USMC apply conducting voltage Vpass on grid), apply dummy memory cells conducting voltage on the grid of dummy memory cells
Vdummy applies selecting pipe conducting voltage Von in upper selecting pipe.Meanwhile drain terminal, source, lower selecting pipe and the substrate of memory
All keep low potential.
In an embodiment of the present invention, low potential is 0V.In other examples, low potential may be other electricity
Pressure value.
According to nonvolatile memory shown in Figure 1A -1C, following problems can be brought since channel is too long:
(1) poor by once padding the functional layer consistency that product is formed；
(2) in programming process, it is usually to pass through shutdown that the storage string where non-selected storage unit, which needs to program, which to be inhibited,
The selecting pipe up and down of non-selected string, string channel non-selected in this way are at floating state, and channel can be due to couplings such as Vpass and Vpgm
Certain potential is closed out, to weaken non-selected Series Code journey electric field, realizes that programming inhibits.In actual programming process, by Vpgm
The groove potential of coupling is higher than the groove potential of Vpass coupling, and the channel coupling potential that such Vpass is generated can drag down Vpgm production
Raw channel couples potential, and channel is longer, and such effect that drags down is stronger, so that it is poorer to program inhibitory effect, programs band
The interference come is bigger.
Fig. 2A is the structural schematic block diagram of the nonvolatile memory of one embodiment of the invention.With reference to shown in Fig. 2A, this is non-
Volatile memory includes memory cell array 21 and controller 22.It wherein, include multiple storages in the memory cell array 21
String.Each storage string includes concatenated first substring and the second substring, and the first substring and the second substring respectively include multiple storages
Unit.Multiple storage units in memory cell array 21 can pass through wordline (WL), string selection line (String Select
Line, SSL), selection line (Ground Select Line, GSL), common source polar curve (Common Source Line, CSL)
Etc. being connected to driving circuit 23, and read/write circuit 24 can be connected to by bit line (BL).Controller 22 can in response to from
The control signal of outside transmission and control the operation of driving circuit 23 and read/write circuit 24.For example, executing to storage unit
When read operation, controller 22 can control driving circuit 23 so that voltage needed for read operation is provided to related storage list
The wordline of member；Controller 22 can also control read/write circuit 24 to allow the reading of read/write circuit 24 to be stored in particular memory location
In data.
Fig. 2 B is the circuit diagram of the storage string in the nonvolatile memory of one embodiment of the invention.With reference to Fig. 2 B institute
Show, which includes concatenated first substring 210 and the second substring 220, and the first substring 210 and the second substring 220 are distinguished
Including multiple storage units (MC).
With reference to shown in Fig. 2 B, intermediate string selecting pipe is connected between the first substring 210 and the second substring 220
Selecting pipe is gone here and there not with storage unit in (Intermediate String Select Transistor, ISST), the centre.
In some embodiments, the controller 22 of nonvolatile memory of the invention is additionally configured to: right during programming
Each storage string chooses storage unit SMC to apply program voltage, applies the first conducting voltage to non-selected storage unit USMC,
And the second conducting voltage is applied to centre string selecting pipe ISST, wherein at least part period during the programming, second is led
The pressure that is powered is greater than the first conducting voltage.
According to these embodiments, the groove potential of non-selected storage unit can be improved, reduce programming operation to non-selected
The interference of storage unit.
In these embodiments, it with reference to shown in Fig. 2 B, can also be wrapped in the storage string of nonvolatile memory of the invention
Include the string of the first string selecting pipe SST1 and second selecting pipe SST2.Wherein, the first string selecting pipe SST1 is connected to the first substring 210 not
The one end (being lower end in figure) being connect with intermediate string selecting pipe ISST；Second string selecting pipe SST2 is connected to the second substring 220 not
The one end (being upper end in figure) being connect with intermediate string selecting pipe ISST.Controller is configured to during programming, is selected the first string
Pipe SST1 applies shutdown voltage, applies cut-in voltage to the second string selecting pipe SST2.
In some embodiments, with reference to shown in Fig. 2 B, nonvolatile memory of the invention can also include and the first string
The common source end CS of selecting pipe SST1 connection, and the drain terminal being connect with the second string selecting pipe.Controller is configured to during programming,
Ground voltage is applied to common source end, shutdown voltage is applied to drain terminal.
In memory cell array, the first string selecting pipe in each storage string is all connected to common source end, for NAND type
For memory, common source polar curve CSL is formed；The second string selecting pipe in each storage string is all connected to drain terminal, then passes through leakage
End is connected to the bit line of memory；The grid of each storage unit is connected to the wordline of memory；Multiple storage strings can be shared
The same substrate (Substrate).
For nand type memory, the grid of the second string selecting pipe in different storage strings is interconnected, and forms string
Selection transistor SST；The grid of the first string selecting pipe in different storage strings interconnects, and forms ground selection transistor GST.Respectively
The grid of first string selecting pipe of a storage string and the second string selecting pipe is separately connected corresponding string selection wordline.
With reference to shown in Fig. 2 B, in some embodiments, except including more in the storage string of nonvolatile memory of the invention
It further include multiple dummy memory cells DMC except a storage unit.In physical storage manufacturing process, it is formed in memory
The storage unit reliability of edge is lower, therefore is not used in use using this partial memory cell as dummy memory cells
Actual read-write operation.It is appreciated that in some embodiments, nonvolatile memory can not have dummy memory cells.
Fig. 2 B is not used in the number for the substring being together in series in storage string in the limitation embodiment of the present invention.In some embodiments
In, can be together in series the storage string formed by more than two multiple substrings.In these embodiments, multiple substrings two-by-two
Between connection without storage unit intermediate selecting pipe of going here and there.Correspondingly, controller is configured that during programming, is deposited to each
Storage string chooses storage unit to apply program voltage, applies the first conducting voltage to non-selected storage unit, and to all centres
Selecting pipe of going here and there applies the second conducting voltage, wherein at least part period during the programming, the second conducting voltage is greater than the
One conducting voltage.
Nonvolatile memory described above can be two dimensional memory, be also possible to three-dimensional storage, such as 3D
Nand memory.
Fig. 3 A and 3B are the program timing sequence schematic diagrames of the nonvolatile memory of one embodiment of the invention.With reference to Fig. 3 A and 3B
It is shown, the programming phases of memory are initially entered from dotted line mark.In general, being the pre- of memory before at the dotted line mark
Conducting phase.In pre- conducting phase, apply pre- conducting voltage in the string of the drain terminal Drain of memory and second selecting pipe SST2.In
Programming phases are chosen storage unit SMC to apply program voltage Vpgm each storage string, are applied to non-selected storage unit USMC
Add the first conducting voltage Vpass, and the second conducting voltage Vpgm' is applied to centre string selecting pipe ISSG, wherein during programming
At least part period, the second conducting voltage Vpgm' be greater than the first conducting voltage Vpass.The voltage that storage unit is applied
Apply on its gate, the voltage applied to string selecting pipe also applies on its gate.
In the embodiment as shown in fig. 3 a, be applied to the waveform of the second conducting voltage Vpgm' in intermediate string selecting pipe with
It is applied to and chooses the waveform of the Vpgm of the program voltage in storage unit identical.In pre- conducting phase, the electricity in storage unit is chosen
Pressure is in low potential；Into after programming phases, applies and the program voltage Vpgm in storage unit is chosen to rise shape in ladder.Such as
Shown in Fig. 3 A, program voltage Vpgm first rises to the first program voltage value 311 and continues for some time, then rises to the second programming
Voltage value 312 simultaneously continues for some time, and then program voltage Vpgm directly drops to low potential water identical with pre- conducting phase
Flat, expression terminates the programming phases for choosing storage unit.It is understood that it is merely illustrative shown in Fig. 3 A, it is not used in limitation
The specific waveform and specific voltage value of program voltage Vpgm.In other examples, the waveform of program voltage Vpgm can be
Waveform with multiple step horizontals, including multiple and different program voltage values.
In the embodiment as shown in fig. 3 a, the second conducting voltage Vpgm' has waveform identical with program voltage Vpgm.In
Pre- conducting phase, the voltage being applied in intermediate string selecting pipe are in low potential；Into after programming phases, the second conducting voltage
Vpgm' first rises to the first turn-on voltage 321 and continues for some time, then rises to the second turn-on voltage 322 and continue
For a period of time；Then it is horizontal directly to drop to low potential identical with pre- conducting phase by the second conducting voltage Vpgm'.
Specifically, the voltage value of the second conducting voltage Vpgm' and the voltage value of program voltage Vpgm can it is identical can also be with
It is different.In some embodiments, the ratio of the voltage value of the voltage value and program voltage Vpgm of the second conducting voltage Vpgm' exists
Between 0.9~1.1.
In embodiment not shown, the second conducting voltage Vpgm' have it is similar to program voltage Vpgm or it is significant not
Same waveform.In these embodiments, the ratio of the voltage value of the voltage value and program voltage Vpgm of the second conducting voltage Vpgm'
It may be less than or equal to 1.1.
In the embodiment as shown in fig. 3 a, at least part period during programming is applied in intermediate string selecting pipe
The second conducting voltage Vpgm' be greater than the first conducting voltage Vpass for being applied in non-selected storage unit.As shown in Figure 3A,
First turn-on voltage 321 can be greater than the first conducting less than the first conducting voltage Vpass, the second turn-on voltage 322
Voltage Vpass.In this way, second conducting voltage Vpgm' is greater than at least in this partial period of the second turn-on voltage 322
First conducting voltage Vpass.In an embodiment of the present invention, at least part period can be at least 1/4 during programming
Period.
In other examples, the first turn-on voltage 321 and the second turn-on voltage 322 may be larger than first and lead
The pressure that is powered Vpass, so that the second conducting voltage Vpgm' is both greater than the first conducting voltage Vpass during entire programming.
In the embodiment shown in figure 3b, it is applied to the wave of the second conducting voltage Vpgm' on intermediate string selecting pipe ISST
Shape chooses the waveform of the Vpgm of the program voltage on storage unit SMC different from being applied to.With reference to shown in Fig. 3 B, not with Fig. 3 A
It is with place, into after programming phases, the second conducting voltage Vpgm' directly rises to a fixed turn-on voltage 330, and
It continues for some time, at the end of programming phases, the second conducting voltage Vpgm' directly drops to identical with pre- conducting phase
Low potential is horizontal.
In the embodiment shown in figure 3b, fixed turn-on voltage 330 is greater than the first conducting voltage Vpass.
Fig. 4 A is the structural schematic diagram of the nonvolatile memory of one embodiment of the invention.With reference to shown in Fig. 4 A, the implementation
The nonvolatile memory of example includes stack layer and memory cell array.Wherein, stack layer includes 410 He of the first storehouse stacked
Second storehouse 420, and the articulamentum 430 between the first storehouse 410 and the second storehouse 420.First storehouse 410 and
Two storehouses 420 all include the grid layer 441 and dielectric layer 442 being alternately stacked respectively.
Memory cell array includes multiple storage strings, and each storage string includes the first substring 450 and the second substring 460.Ginseng
It examines shown in Fig. 4 A, the first substring 450 runs through the first storehouse 410, and the second substring 460 runs through the second storehouse 420.In the first storehouse
410 and second are respectively formed with through the first channel hole 411 and the second channel hole 421 of its stack architecture in storehouse 420.This
One channel hole 411 and the second channel hole 421 are all poroid in cylinder.Fig. 4 A be the nonvolatile memory of the embodiment of the present invention just
Depending on cross-sectional view, the elevational sectional view of storage string is shown.It is appreciated that the first substring 450 is formed in first from the visual angle of Fig. 4 A
It is in cylindrical annular configuration, and do not fill up the space in the first channel hole 411 on the side wall in channel hole 411.Second substring
460 are formed on the side wall in the second channel hole 421, are in cylindrical annular configuration, and do not fill up the sky in the second channel hole 421
Between.
With reference to shown in Fig. 4 A, the first substring 450 includes the first channel layer 451, and the second substring 460 includes the second channel layer
461, it is electrically connected between the first channel layer 451 and the second channel layer 461 by channel interconnecting piece 431.First channel layer 451 exists
The innermost ring of first substring 450 is adjacent with the gap inside the first channel hole 411；Second channel layer 461 is in the second substring 460
Innermost ring, it is adjacent with the gap inside the second channel hole 421.
With reference to shown in Fig. 4 A, the stack layer in the nonvolatile memory of the present embodiment can be by grid layer 441 and medium
Layer 442 is alternately stacked, and the extending direction of stack layer is defined as extending direction D1, the stacking direction of stack layer is defined as
Stacking direction D2, D1 and D2 are mutually perpendicular to.Articulamentum 430 is distributed along extending direction D1, with the first substring 450 and the second son
Grid layer in string 460 is parallel with dielectric layer.Articulamentum 430 on stacking direction D2, positioned at the first substring 410 dielectric layer and
Between the dielectric layer of second substring 420, i.e., articulamentum 430 does not connect with the grid layer in the first substring 410 and the second substring 420
Touching.
Articulamentum 430 connects on the extending direction D1 of stack layer with the channel of the first channel layer 451 and the second channel layer 461
Socket part 431 is opposite, and is dielectric layer between articulamentum 430 and channel interconnecting piece 431.
In the present embodiment, articulamentum 430 and channel interconnecting piece 431 constitute the intermediate string selection not with storage unit
Pipe, go here and there the intermediate selecting pipe ISST that goes here and there shown in selecting pipe, that is, Fig. 2 B and Fig. 3 A, 3B for the centre.Due to the of the first substring 410
One channel layer 451 is by the second channel layer 461 electric connection of channel interconnecting piece 431 and the second substring 420, therefore, among this
String selecting pipe is electrically connected between the first substring 410 and the second substring 420.
It in some embodiments, further include the first charge storage layer 452 in the first substring 450 with reference to shown in Fig. 4 A, second
It further include the second charge storage layer 462 in substring 460, first charge storage layer 452 and the second charge storage layer 462 do not extend
To the region 432 between articulamentum 430 and channel interconnecting piece 431.The region 432 is dielectric layer.
The channel interconnecting piece 431 between the first channel layer 451 and the second channel layer 461 in the present embodiment is solid post
Shape.
In some embodiments, the first charge storage layer 452 in the first substring 450 includes the first tunnel layer 4521, the
One electric charge capture layer 4522 and the first barrier layer 4523, the second charge storage layer 462 in the second substring 460 include the second tunnelling
The 4621, second electric charge capture layer 4622 of layer and the second barrier layer 4623.In these embodiments, the first substring 450 is from the first ditch
The side wall in road hole 411 is followed successively by the first barrier layer 4523, the first electric charge capture layer 4522, the first tunnel layer 4521 and to center
One channel layer 451；Second substring 460 is followed successively by second the 4623, second electricity of barrier layer from the side wall in the second channel hole 421 to center
Lotus trapping layer 4622, the second tunnel layer 4621 and the second channel layer 461.
In an embodiment of the present invention, the exemplary materials of barrier layer and tunnel layer are silica, silicon oxynitride or both
Mixture, the exemplary materials of electric charge capture layer are the multilayered structure of silicon nitride or silicon nitride and silicon oxynitride.Barrier layer,
Electric charge capture layer, tunnel layer can form the multilayer knot for example with silicon oxynitride-silicon-nitride and silicon oxide (SiON/SiN/SiO)
Structure；The exemplary materials of channel layer are polysilicon.It is to be understood that these layers can choose other materials.For example, barrier layer
Material may include high K (dielectric constant) oxide layer；The material of channel layer may include monocrystalline silicon, monocrystalline germanium, SiGe, Si:C,
The semiconductor materials such as SiGe:C, SiGe:H.
Gap with reference to shown in Fig. 4 A, inside the first channel hole 411 of the nonvolatile memory of the embodiment of the present invention
It is also filled with insulating materials in the gap inside the second channel hole 421, plays the role of insulation and support.The insulating materials can
To be the material identical or different with second material layer 442.The insulating materials can be oxide.
In some embodiments, nonvolatile memory shown in Fig. 4 A further includes controller, is configured in the programming phase
Between, it chooses storage unit to apply program voltage each storage string, conducting voltage, and centering is applied to non-selected storage unit
Between string selecting pipe apply the second conducting voltage, wherein at least part period during programming, the second conducting voltage, which is greater than, to be led
Be powered pressure.The voltage value of the voltage value and program voltage Vpgm of second conducting voltage Vpgm' can be the same or different.
In some embodiments, the ratio of the voltage value of the voltage value and program voltage Vpgm of the second conducting voltage Vpgm'
Between 0.9~1.1.
In further embodiments, the ratio of the voltage value of the voltage value and program voltage Vpgm of the second conducting voltage Vpgm'
Example is less than or equal to 1.1.
Operation description about the controller and its during programming is referred to correspond to Fig. 2A, 2B, 3A and 3B above
Description.
It should be noted that stack layer, storage string, the first substring, the second substring etc. included in the embodiment of the present invention
All be it is symmetrical centered on the central axis in channel hole, therefore, a part of structure may have only been indicated in figure, for
The description of the part-structure does not indicate part-structure suitable for symmetrical with it.
Fig. 4 A is not used in the number of storehouse and substring in the limitation embodiment of the present invention.It in some embodiments, can be by two
A above multiple storehouses are stacked up to form nonvolatile memory of the invention.In these embodiments, in each storehouse
One substring of middle formation, and articulamentum and channel interconnecting piece are formed between multiple adjacent substrings.Correspondingly, controller is configured that In
It during programming, chooses storage unit to apply program voltage each storage string, the first conducting is applied to non-selected storage unit
Voltage, and the second conducting voltage is applied to all intermediate string selecting pipes, wherein at least part period during the programming, the
Two conducting voltages are greater than the first conducting voltage.
Fig. 4 B is the structural schematic diagram of the nonvolatile memory of another embodiment of the present invention.With reference to shown in Fig. 4 B, the reality
Apply example and Fig. 4 A the difference is that, the channel between the first channel layer 451 and the second channel layer 461 in the embodiment connects
Socket part 431 is open column shape.
With reference to shown in Fig. 4 A and Fig. 4 B, no matter channel interconnecting piece 431 is solid cylindrical or open column shape, the channel interconnecting piece
431 and articulamentum 430 all constitute the intermediate selecting pipe of going here and there not with storage unit.In this way, being carried out to nonvolatile memory
When programming operation, applies a higher second conducting voltage Vpgm' in the string selecting pipe of centre, non-selected storage can be improved
The groove potential of unit reduces the potential difference between the groove potential and conducting voltage Vpass, to reduce programming operation to non-
Choose the interference of storage unit.
Fig. 5 is the exemplary process diagram of the manufacturing method of the nonvolatile memory of one embodiment of the invention.In conjunction with Fig. 5 and
Shown in Fig. 6 A-8C, the manufacturing method of the present embodiment the following steps are included:
Step 510, the first storehouse is formed.
Fig. 6 A be the nonvolatile memory of one embodiment of the invention manufacturing method in form the process of the first storehouse and show
It is intended to.With reference to shown in Fig. 6 A, being formed by the first storehouse 610 in step 510 includes 641 He of first material layer being alternately stacked
Second material layer 642.
In some embodiments, first material layer 641 and second material layer 642 can be selected from following material and at least
Including a kind of dielectric, such as silicon nitride, silica, amorphous carbon, diamond-like amorphous carbon, germanium oxide, aluminium oxide etc. and
A combination thereof.First material layer 641 and second material layer 642 have different Etch selectivities.Such as it can be silicon nitride and oxygen
The combination of the combination of SiClx, silica and undoped polysilicon or amorphous silicon, the combination of silicon oxide or silicon nitride and amorphous carbon
Deng.The first material layer 641 of first storehouse 610 and the deposition method of second material layer 642 may include chemical vapor deposition
(CVD, PECVD, LPCVD, HDPCVD), atomic layer deposition (ALD) or physical gas-phase deposite method such as molecular beam epitaxy (MBE),
Its various method such as thermal oxide, evaporation, sputtering.One layer in first material layer 641 and second material layer 642 can be used as grid
Sacrificial layer, such as silicon nitride layer.Lamination as grid sacrificial layer can also be other conductive layers, such as tungsten, cobalt, nickel
Deng.It can be the dielectric material of such as silica, such as aluminium oxide not as another material layer of grid sacrificial layer, hafnium oxide,
Tantalum oxide etc..
In an embodiment of the present invention, first material layer 641 is dummy gate layer, and second material layer 642 is dielectric layer.
Step 520, the first substring for extending vertically through the first storehouse is formed.
Fig. 6 B and Fig. 6 C be the nonvolatile memory of one embodiment of the invention manufacturing method in form the first substring
Process schematic.With reference to shown in Fig. 6 B, etching forms the first channel hole 611 first in the first storehouse 610.With reference to Fig. 6 C institute
Show, the first substring 650 of product is padded in the first channel hole 611.In the present embodiment, which includes the first channel
Layer 651.First channel layer 651 can be conductive material, such as polysilicon.
It is understood that Fig. 6 C is the elevational cross-sectional view of the nonvolatile memory of the embodiment of the present invention, is shown
The elevational sectional view of one substring.It is appreciated that the first substring 650 answers structure annular in shape from the visual angle of Fig. 6 C, and does not fill up
Space in first channel hole 611.First channel layer 651 the first substring 650 innermost ring, inside the first channel hole 611
Gap it is adjacent.
In some embodiments, the first substring 650 further includes the first charge storage layer 652.
In some embodiments, the first charge storage layer 652 in the first substring 650 includes the first tunnel layer 6521, the
One electric charge capture layer 6522 and the first barrier layer 6523.In these embodiments, the first channel hole 611 side wall to center according to
The first barrier layer 6523 of secondary pad product, the first electric charge capture layer 6522, the first tunnel layer 6521 and the first channel layer 651, to be formed
First substring 650.
It is the second material layer 642 as dielectric layer in the top of first storehouse 610 with reference to shown in Fig. 6 C.
Step 530, articulamentum is formed on the first storehouse.
Fig. 6 D and 6E are the processes that articulamentum is formed in the manufacturing method of the nonvolatile memory of one embodiment of the invention
Schematic diagram.With reference to shown in Fig. 6 D, fill oxide, the oxide material be can be in the gap in the first channel hole 611 first
The identical or different material with second material layer 642.Then one layer of articulamentum 630 is formed on the first storehouse 610.Due to first
It is second material layer 642 at the top of storehouse 610, therefore, which is formed in the second material layer 642 at the top of this.The company
The material identical or different with first material layer 641 can be used by connecing layer 630.The technique for forming the articulamentum 630 can use
It is formed with deposition first material layer 641 and the similar technique of second material layer 642.
It, in some embodiments, can also be on the articulamentum 630 after forming articulamentum 630 with reference to shown in Fig. 6 D
Form one layer of second material layer 642.
In the manufacturing method of the embodiment of the present invention, after filling the first channel hole 611 or forming articulamentum 630, with
And it is some other during, can also include the steps that certain surfaces carry out planarization process.
With reference to shown in Fig. 6 E, the channel interconnecting piece 631 of the first channel layer 651 of contact is formed.The channel interconnecting piece 631 is located at
The top in the first channel hole 611, size can cover the maximum diameter of hole in the first channel hole 611.It can be tied shown in Fig. 6 D
On the basis of structure, by mask to articulamentum and it is disposed thereon under two layers of second material layer 642 perform etching and pad product, with
Form the channel interconnecting piece 631.
The material of channel interconnecting piece 631 can be the conductive material identical or different with the first channel layer 651.
With reference to shown in Fig. 6 E, it can also be contacted with articulamentum 630 in the channel interconnecting piece 631 that this step is formed.
Step 540, the second storehouse is formed on articulamentum.
Fig. 6 F be the nonvolatile memory of one embodiment of the invention manufacturing method in form the process of the second storehouse and show
It is intended to.With reference to shown in Fig. 6 F, in the structure shown in Fig. 6 E, the second storehouse 620 is formed.Similarly with the first storehouse 610, second
Storehouse 620 includes the first material layer 641 and second material layer 642 being alternately stacked.About first material layer 641 and the second material
The explanation of layer 642 can be with reference to the explanation about the first storehouse 610.
The method for forming the second storehouse 620 can be in the layer-by-layer alternating deposit first material layer in the top of the first storehouse 610
641 and second material layer 642.
With reference to shown in Fig. 6 F, the second storehouse 620 is located at the ditch in the first material layer 641 and the first storehouse 610 of bottommost
Road interconnecting piece 631 contacts, and is in contact with the second material layer 642 of 630 top of articulamentum.
Step 550, the second substring for extending vertically through the second storehouse is formed.
The manufacturing method of nonvolatile memory according to the present invention nonvolatile memory obtained such as Fig. 4 A and 4B
It is shown.Corresponding to the embodiment of two kinds of nonvolatile memories shown in Fig. 4 A and 4B, slightly have in the manufacturing method of this step
Difference is divided to two embodiments to illustrate step 550 respectively below.
Embodiment corresponding to nonvolatile memory shown in Fig. 4 A:
Fig. 7 A-7C be the nonvolatile memory of one embodiment of the invention manufacturing method in form the process of the second substring
Schematic diagram.With reference to shown in Fig. 7 A, the second substring 660 for running through second storehouse 620 is formed in the second storehouse 620.With first
The forming method of substring 650 is similarly, it is necessary first to which etching forms the second channel hole 621 in the second storehouse 620；It then can be with
The second substring 660 of product is padded in the second channel hole 621.In the present embodiment, which includes the second channel layer
661.Second channel layer 661 can be conductive material.Second substring 660 answers structure annular in shape, and does not fill up the second ditch
Space in road hole 621.Second channel layer 661 the second substring 660 innermost ring, with the gap inside the second channel hole 621
It is adjacent.
In some embodiments, as shown in Figure 7 A, the second channel layer 661 is in contact with channel interconnecting piece 631.Due to first
Channel layer 651 is also in contact with channel interconnecting piece 631, and the first channel layer 651, the second channel layer 661 and channel interconnecting piece
631 can be conductive material, and three can be electrically connected.
In some embodiments, the second substring 660 further includes the second charge storage layer 662.First charge storage layer, 652 He
It is separated between second charge storage layer 662 by channel interconnecting piece 631.
In some embodiments, the second charge storage layer 662 in the second substring 660 includes the second tunnel layer 6621, the
Two electric charge capture layers 6622 and the second barrier layer 6623.In these embodiments, the second channel hole 621 side wall to center according to
The second barrier layer 6623 of secondary pad product, the second electric charge capture layer 6622, the second tunnel layer 6621 and the second channel layer 661, to be formed
Second substring 660.
With reference to shown in Fig. 7 B, the fill insulant in the second channel hole 621.The insulating materials can be and the second material
642 identical or different material of layer.During shown in Fig. 7 B, the first material layer 641 as dummy gate layer is also etched away.
It should be noted that articulamentum 630 is also possible to the first material layer 641 as dummy gate layer in front the step of.Cause
This, in the process, while by the first material layer 641 in the laminated construction of the first storehouse 610 and the second storehouse 620, and
First material layer 641 in articulamentum 630 etches away together.
It further include the channel interconnecting piece 631 of oxidized portion during shown in Fig. 7 B.It is right in conjunction with shown in Fig. 7 A and 7B
The part that channel interconnecting piece 631 is in contact with articulamentum 630 is aoxidized, and the first charge storage layer 652 and the second charge are deposited
Reservoir 662 does not extend into the region 632 between articulamentum 630 and channel interconnecting piece 631.That is, in the first substring 650
The second charge storage layer 662 in first charge storage layer 652 and the second substring 660 will not be electrically connected.
Further, in some embodiments, the first electric charge capture layer 6522 and the first tunnel layer in the first substring 650
6521 and second the second electric charge capture layer 6622 in substring 660 and the second tunnel layer 6621 all do not extend into articulamentum yet
Region 632 between 630 and channel interconnecting piece 631.
With reference to shown in Fig. 7 C, product is padded at the position of the first material layer 641 and articulamentum 630 that etch away during Fig. 7 B
Conductive material.The first material layer 641 indicated in fig. 7 c forms nonvolatile memory by padding product conductive material later
Grid layer.
The manufacturing method of as nonvolatile memory according to an embodiment of the present invention shown in Fig. 7 C is obtained non-volatile
Property memory.The nonvolatile memory is identical as nonvolatile memory shown in Fig. 4 A.Its channel interconnecting piece 631 is solid
Column.
For the embodiment of nonvolatile memory shown in Fig. 4 B, can be manufactured by the way of following.
Fig. 8 A-8C be the nonvolatile memory of another embodiment of the present invention manufacturing method in form the mistake of the second substring
Journey schematic diagram.Process shown in Fig. 8 A and process shown in Fig. 7 A are more similar, the difference is that, in the second storehouse 620
When etching forms the second channel hole 621, also channel interconnecting piece 631 is etched, channel interconnecting piece 631 is made to become open tubular column
The structure of shape.As shown in Figure 8 A, the etching of channel interconnecting piece 631 is made to fill out in the first channel hole 611 of the first storehouse 610
The oxide filled is exposed.
The process that the second substring 660 of product is padded in the second channel hole 621 is also identical as Fig. 7 A, can refer to relevant theory
Bright content.
With reference to shown in Fig. 8 B, the fill oxide in the second channel hole 621, while also in the hollow of channel interconnecting piece 631
Portion's fill oxide.Make the hollow part of the oxide and channel interconnecting piece 631 in the first channel hole 611, the second channel hole 621
Oxide is integrally formed.During shown in Fig. 8 B, to the first material layer 641 and articulamentum 630 as dummy gate layer
It is identical shown in the process and Fig. 7 B of the channel interconnecting piece 631 of etching and oxidized portion, it can be with reference in relevant explanation
Hold.
With reference to shown in Fig. 8 C, the manufacturing method of nonvolatile memory according to an embodiment of the present invention is obtained non-volatile
Property memory is identical as nonvolatile memory shown in Fig. 4 B.Channel interconnecting piece 631 in Fig. 8 C is open column shape.
In other examples, above-mentioned manufacturing method can be adapted for having more than two multiple storehouses stack and
At nonvolatile memory manufacture.
The manufacturing method of the nonvolatile memory of embodiment according to the present invention is respectively formed in the first storehouse 610
The second substring 660 in first substring 650 and the second storehouse 620, rather than disposable pad product forms the first son after stacking
String 650 and the second substring 660, improve the uniformity and consistency of functional layer and conductivity channel layer.
Although the present invention is described with reference to current specific embodiment, those of ordinary skill in the art
It should be appreciated that above embodiment is intended merely to illustrate the present invention, can also make in the case where no disengaging spirit of that invention
Various equivalent change or replacement out, therefore, as long as to the variation of above-described embodiment, change in spirit of the invention
Type will all be fallen in the range of following claims.
Claims (19)
1. a kind of nonvolatile memory, comprising:
Memory cell array, including multiple storage strings, each storage string include concatenated first substring and the second substring, and described
One substring and the second substring respectively include multiple storage units；And
Not with the intermediate string selecting pipe of storage unit, it is connected between first substring and second substring.
2. nonvolatile memory as described in claim 1, which is characterized in that further include:
Controller is configured that during programming, chooses storage unit to apply program voltage each storage string, to non-selected
Storage unit applies the first conducting voltage, and applies the second conducting voltage to the intermediate string selecting pipe, wherein in the programming
At least part period of period, second conducting voltage are greater than first conducting voltage.
3. nonvolatile memory as claimed in claim 2, which is characterized in that the waveform of second conducting voltage with it is described
The waveform of program voltage is identical, and second conducting voltage and the ratio of the program voltage are between 0.9~1.1.
4. nonvolatile memory as claimed in claim 2, which is characterized in that the waveform of second conducting voltage with it is described
The waveform of first conducting voltage is identical, and second conducting voltage and the ratio of the program voltage are less than or equal to 1.1.
5. nonvolatile memory as claimed in claim 2, which is characterized in that further include:
First string selecting pipe is connected to one end that first substring is not connect with the intermediate string selecting pipe；
Second string selecting pipe is connected to one end that second substring is not connect with the intermediate string selecting pipe；
Wherein during the programming, shutdown voltage is applied to the first string selecting pipe, the second string selecting pipe is applied
Cut-in voltage.
6. nonvolatile memory as claimed in claim 5, which is characterized in that further include:
The common source end being connect with the first string selecting pipe；And
The drain terminal being connect with the second string selecting pipe；
Wherein during the programming, ground voltage is applied to the common source end, shutdown voltage is applied to the drain terminal.
7. a kind of operating method of nonvolatile memory, the nonvolatile memory include memory cell array and not with
The intermediate of storage unit goes here and there selecting pipe, and the memory cell array includes multiple storage strings, and each storage string includes concatenated the
One substring and the second substring, first substring and the second substring respectively include multiple storage units, it is described it is intermediate go here and there selecting pipe,
It is connected between first substring and second substring, the method comprise the steps that
During programming, chooses storage unit to apply program voltage each storage string, the is applied to non-selected storage unit
One conducting voltage, and the second conducting voltage is applied to the intermediate string selecting pipe, wherein at least one during the programming
At times, second conducting voltage is greater than first conducting voltage.
8. a kind of nonvolatile memory, comprising:
Stack layer, the first storehouse and the second storehouse including stacking and the company between first storehouse and the second storehouse
Layer is connect, first storehouse and the second storehouse respectively include the grid layer being alternately stacked and dielectric layer；And
Memory cell array, including multiple storage strings, each storage string include the first substring and the second substring, first substring
First storehouse is extended vertically through, second substring extends vertically through second storehouse, and first substring includes the first ditch
Channel layer, second substring include the second channel layer, and first channel layer is electrically connected second channel layer；
Wherein the articulamentum on the extending direction of the stack layer with first channel layer and second channel layer
Channel interconnecting piece is opposite, and is dielectric layer between the articulamentum and the channel interconnecting piece.
9. nonvolatile memory as claimed in claim 8, which is characterized in that first substring includes the first charge storage
Layer, second substring includes the second charge storage layer, wherein first charge storage layer and second charge storage layer
The region between the articulamentum and the channel interconnecting piece is not extend intoed.
10. nonvolatile memory as claimed in claim 8, which is characterized in that first channel layer and second ditch
The channel interconnecting piece of channel layer is open column shape or solid cylindrical.
11. nonvolatile memory as claimed in claim 8, which is characterized in that the articulamentum and the channel interconnecting piece
The intermediate string selecting pipe not with storage unit is constituted, is electrically connected between first substring and second substring.
12. nonvolatile memory as claimed in claim 11, which is characterized in that further include controller, be configured that and programming
Period chooses storage unit to apply program voltage each storage string, applies the first conducting voltage to non-selected storage unit,
And the second conducting voltage is applied to the intermediate string selecting pipe, wherein at least part period during the programming, described
Second conducting voltage is greater than first conducting voltage.
13. nonvolatile memory as claimed in claim 12, which is characterized in that the waveform of second conducting voltage and institute
The waveform for stating program voltage is identical, and second conducting voltage and the ratio of the program voltage are between 0.9~1.1.
14. nonvolatile memory as claimed in claim 12, which is characterized in that the waveform of second conducting voltage and institute
The waveform for stating the first conducting voltage is identical, and second conducting voltage and the program voltage are less than or equal to 1.1.
15. a kind of manufacturing method of nonvolatile memory, comprising the following steps:
The first storehouse is formed, first storehouse includes the first material layer and second material layer being alternately stacked；
The first substring for extending vertically through first storehouse is formed, first substring includes the first channel layer；
Articulamentum is formed on first storehouse；
The second storehouse is formed on the articulamentum, second storehouse includes the first material layer being alternately stacked and the second material
Layer；And
The second substring for extending vertically through second storehouse is formed, second substring includes the second channel layer, first ditch
Channel layer is electrically connected second channel layer, wherein the channel interconnecting piece of first channel layer and second channel layer is in institute
State it is opposite with the articulamentum on the extending direction of stack layer, and between the channel interconnecting piece and the articulamentum be medium
Layer；
Wherein the first material layer is grid layer or dummy gate layer, and the second material layer is dielectric layer.
16. method as claimed in claim 15, which is characterized in that first substring further includes the first charge storage layer, institute
Stating the second substring further includes the second charge storage layer, wherein first charge storage layer and second charge storage layer do not prolong
Reach the region between the articulamentum and the channel interconnecting piece.
17. method as claimed in claim 15, which is characterized in that further include after forming articulamentum on first storehouse,
Form the channel interconnecting piece for contacting first channel layer；And when forming second substring, second channel layer contacts institute
State channel interconnecting piece.
18. method as claimed in claim 17, which is characterized in that the channel interconnecting piece is open column shape or solid post
Shape.
19. method as claimed in claim 15, which is characterized in that the articulamentum and the channel interconnecting piece constitute not with
The intermediate string selecting pipe of storage unit, is electrically connected between first substring and second substring.
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| CN111402942B (en) | 2021-03-19 |
| CN111402942A (en) | 2020-07-10 |
| CN110428859B (en) | 2020-09-04 |
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