CN110428859B

CN110428859B - Nonvolatile memory and method of manufacturing the same

Info

Publication number: CN110428859B
Application number: CN201910728547.6A
Authority: CN
Inventors: 刘红涛; 黄莹; 魏文喆; 许锋
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2019-08-08
Filing date: 2019-08-08
Publication date: 2020-09-04
Anticipated expiration: 2039-08-08
Also published as: CN111402942A; CN111402942B; CN110428859A

Abstract

The invention relates to a nonvolatile memory and a manufacturing method thereof. The non-volatile memory includes an array of memory cells and an intermediate string select pipe with no memory cells. The storage unit array comprises a plurality of storage strings, each storage string comprises a first sub string and a second sub string which are connected in series, and the first sub string and the second sub string respectively comprise a plurality of storage units. And the middle string selection pipe is connected between the first sub string and the second sub string. In the invention, the middle string selection tube without the storage unit is connected between the storage strings, and during programming, higher voltage is applied to the middle string selection tube, so that the channel potential of the unselected storage unit can be improved, and the interference of programming operation on the unselected storage unit is reduced.

Description

Nonvolatile memory and method of manufacturing the same

Technical Field

The present invention relates to the field of semiconductor devices, and more particularly, to a nonvolatile memory and a method for manufacturing the same.

Background

With the development of technology, the size of electronic products is required to be smaller and smaller, and the memory device is required to be small in size and high in capacity. Non-volatile memory may retain stored data when power is interrupted. In order to improve the integration of the nonvolatile memory, a 3D nonvolatile memory device in which memory cells are vertically stacked from a silicon substrate is proposed.

For a 3D NAND type nonvolatile memory of a vertical channel structure, a stack structure having dielectric layers and gate layers alternately stacked and a channel hole penetrating the stack structure are provided. Deep hole etching is increasingly difficult as the number of stacked layers increases. It is common practice to join two or more stacked structures in a vertical direction to form a more stacked structure. Connecting different stack structures by using an oxide layer, and then carrying out primary padding on the functional layer inside the channel hole. A common padding sequence of the functional layer is a blocking layer, a storage layer and a tunneling layer from the side wall of the channel hole to the center of the channel hole in sequence, and then a conductive layer is padded. Because the trench holes formed by connecting a plurality of stack structures are deep, the thicknesses of the functional layers formed by one-time padding are inconsistent, and the consistency of the components of each layer is poor, so that the electrical performance of the memory is poor. On the other hand, the program disturb problem of the nonvolatile memory with multiple stack structures in the programming stage is also more serious due to the increase of the number of layers.

Disclosure of Invention

The technical problem to be solved by the invention is to provide a nonvolatile memory with a better functional layer consistency, which can reduce programming interference.

The invention provides a nonvolatile memory, which comprises a memory cell array and a middle string selection pipe without memory cells. The storage unit array comprises a plurality of storage strings, each storage string comprises a first sub string and a second sub string which are connected in series, and the first sub string and the second sub string respectively comprise a plurality of storage units. And the middle string selection pipe is connected between the first sub string and the second sub string.

In an embodiment of the invention, the nonvolatile memory further includes a controller configured to: during programming, a programming voltage is applied to selected memory cells of each memory string, a first turn-on voltage is applied to unselected memory cells, and a second turn-on voltage is applied to the intermediate string select transistor, wherein the second turn-on voltage is greater than the first turn-on voltage for at least a portion of the period during the programming.

In an embodiment of the invention, a waveform of the second turn-on voltage is the same as a waveform of the programming voltage, and a ratio of the second turn-on voltage to the programming voltage is between 0.9 and 1.1.

In an embodiment of the invention, a waveform of the second turn-on voltage is the same as a waveform of the first turn-on voltage, and a ratio of the second turn-on voltage to the programming voltage is less than or equal to 1.1.

In an embodiment of the invention, the nonvolatile memory further includes: the first string selection pipe is connected to one end of the first sub string which is not connected with the middle string selection pipe; the second string selection pipe is connected to one end, which is not connected with the middle string selection pipe, of the second sub string; wherein during the programming, an off voltage is applied to the first string select tubes and an on voltage is applied to the second string select tubes.

In an embodiment of the invention, the nonvolatile memory further includes a common source terminal connected to the first string selection pipe; and a drain connected to the second string of selection pipes; and applying a ground voltage to the common source terminal and applying a turn-off voltage to the drain terminal during the programming.

The present invention further provides an operating method of a non-volatile memory, the non-volatile memory including a memory cell array and an intermediate string selection pipe without memory cells, the memory cell array including a plurality of memory strings, each memory string including a first sub string and a second sub string connected in series, the first sub string and the second sub string respectively including a plurality of memory cells, the intermediate string selection pipe being connected between the first sub string and the second sub string, wherein the method includes: during programming, a programming voltage is applied to selected memory cells of each memory string, a first turn-on voltage is applied to unselected memory cells, and a second turn-on voltage is applied to the intermediate string select transistor, wherein the second turn-on voltage is greater than the first turn-on voltage for at least a portion of the period during the programming.

The invention also provides a nonvolatile memory, which comprises a stack layer and a memory cell array. The stacking layer comprises a first stack and a second stack which are stacked and a connecting layer positioned between the first stack and the second stack, wherein the first stack and the second stack respectively comprise gate layers and dielectric layers which are stacked alternately. The memory cell array comprises a plurality of memory strings, each memory string comprises a first substring and a second substring, the first substring vertically penetrates through the first stack, the second substring vertically penetrates through the second stack, the first substring comprises a first channel layer, the second substring comprises a second channel layer, and the first channel layer is electrically connected with the second channel layer; the connection layer is opposite to the channel connection portions of the first channel layer and the second channel layer in the extension direction of the stacked layer, and a dielectric layer is arranged between the connection layer and the channel connection portions.

In an embodiment of the invention, the first sub-string comprises a first charge storage layer and the second sub-string comprises a second charge storage layer, wherein the first charge storage layer and the second charge storage layer do not extend to a region between the connection layer and the channel connection.

In an embodiment of the present invention, the channel connection portion of the first channel layer and the second channel layer is a hollow pillar shape or a solid pillar shape.

In an embodiment of the invention, the connection layer and the channel connection portion constitute an intermediate string selection tube without a memory cell, and are electrically connected between the first sub string and the second sub string.

In an embodiment of the invention, a waveform of the second turn-on voltage is the same as a waveform of the first turn-on voltage, and the second turn-on voltage and the programming voltage are less than or equal to 1.1.

The invention also provides a manufacturing method of the nonvolatile memory, which comprises the following steps: forming a first stack comprising first and second material layers stacked alternately; forming a first sub-string vertically penetrating the first stack, the first sub-string including a first channel layer; forming a connection layer on the first stack; forming a second stack on the connection layer, the second stack comprising first material layers and second material layers stacked alternately; and forming a second substring vertically penetrating through the second stack, the second substring including a second channel layer, the first channel layer being electrically connected to the second channel layer, wherein a channel connection portion of the first channel layer and the second channel layer is opposite to the connection layer in an extending direction of the stacked layer, and a dielectric layer is between the channel connection portion and the connection layer; the first material layer is a gate layer or a dummy gate layer, and the second material layer is a dielectric layer.

In an embodiment of the invention, the first sub-string further comprises a first charge storage layer, the second sub-string further comprises a second charge storage layer, wherein the first charge storage layer and the second charge storage layer do not extend to a region between the connection layer and the channel connection portion.

In an embodiment of the invention, forming a connection layer on the first stack further comprises forming a channel connection portion contacting the first channel layer; and when the second substring is formed, the second channel layer contacts the channel connecting part.

In an embodiment of the invention, the channel connection portion is a hollow column or a solid column.

According to the technical scheme, the middle string selection tube without the storage unit is connected between the storage strings, and during programming, higher voltage is applied to the middle string selection tube, so that the channel potential of the unselected storage unit can be improved, and the interference of programming operation on the unselected storage unit is reduced; according to the manufacturing method of the nonvolatile memory, the functional layer and the conductive channel layer in each stack are respectively formed, and the up-and-down uniformity and the consistency of the functional layer and the conductive channel layer are improved.

Drawings

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below, wherein:

FIG. 1A is a schematic diagram of a 3D NAND memory with functional layers formed by one pad deposition;

FIG. 1B is a circuit schematic of the memory of FIG. 1A;

FIG. 1C is a schematic diagram of a programming timing diagram of the memory of FIG. 1A;

FIG. 2A is a block diagram illustrating the structure of a non-volatile memory according to an embodiment of the present invention;

FIG. 2B is a circuit diagram of a memory string in a non-volatile memory according to an embodiment of the present invention;

FIGS. 3A and 3B are schematic diagrams of the programming timing of a non-volatile memory according to an embodiment of the present invention;

FIG. 4A is a schematic structural diagram of a nonvolatile memory according to an embodiment of the present invention;

FIG. 4B is a schematic structural diagram of a nonvolatile memory according to another embodiment of the present invention;

FIG. 5 is an exemplary flow chart of a method of manufacturing a non-volatile memory according to one embodiment of the present invention;

FIG. 6A is a schematic diagram of a process of forming a first stack in a method of fabricating a non-volatile memory according to an embodiment of the invention;

FIGS. 6B and 6C are schematic diagrams illustrating a process of forming a first sub-string in a method of manufacturing a non-volatile memory according to an embodiment of the invention;

FIGS. 6D and 6E are schematic views illustrating a process of forming a connection layer in a method of manufacturing a nonvolatile memory according to an embodiment of the present invention;

FIG. 6F is a process diagram of forming a second stack in the method of fabricating a non-volatile memory according to an embodiment of the invention;

FIGS. 7A-7C are schematic diagrams illustrating a process of forming a second sub-string in a method of manufacturing a non-volatile memory according to an embodiment of the invention;

FIGS. 8A-8C are schematic views illustrating a process of forming a second sub-string in a method of manufacturing a non-volatile memory according to another embodiment of the invention.

Detailed Description

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways than those specifically described herein, and thus the present invention is not limited to the specific embodiments disclosed below.

As used in this application and the appended claims, the terms "a," "an," "the," and/or "the" are not intended to be inclusive in the singular, but rather are intended to be inclusive in the plural unless the context clearly dictates otherwise. In general, the terms "comprises" and "comprising" merely indicate that steps and elements are included which are explicitly identified, that the steps and elements do not form an exclusive list, and that a method or apparatus may include other steps or elements.

In describing the embodiments of the present invention in detail, the cross-sectional views illustrating the structure of the device are not enlarged partially in a general scale for convenience of illustration, and the schematic drawings are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.

For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary words "below" and "beneath" can encompass both an orientation of up and down. The device may have other orientations (rotated 90 degrees or at other orientations) and the spatial relationship descriptors used herein should be interpreted accordingly. Further, it will also be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

In the context of this application, a structure described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.

It will be understood that when an element is referred to as being "on," "connected to," "coupled to" or "contacting" another element, it can be directly on, connected or coupled to, or contacting the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly on," "directly connected to," "directly coupled to" or "directly contacting" another element, there are no intervening elements present. Similarly, when a first component is said to be "in electrical contact with" or "electrically coupled to" a second component, there is an electrical path between the first component and the second component that allows current to flow. The electrical path may include capacitors, coupled inductors, and/or other components that allow current to flow even without direct contact between the conductive components.

Flow charts are used in this application to illustrate the operations performed by a manufacturing method according to an embodiment of the present invention. It should be understood that the preceding operations are not necessarily performed in the exact order in which they are performed. Rather, various steps may be processed in reverse order or simultaneously. Meanwhile, other operations are added to or removed from these processes.

Fig. 1A is a schematic structural diagram of a 3D NAND memory in which a functional layer is formed by one-time pad deposition. Referring to fig. 1A, the memory is composed of two stack structures, a lower stack 110 and an upper stack 120. Each stack structure includes a stack of first material layers 141 and second material layers 142 alternately stacked.

The first material layer 141 and the second material layer 142 may be materials selected from and include at least one insulating dielectric such as silicon nitride, silicon oxide, amorphous carbon, diamond-like amorphous carbon, germanium oxide, aluminum oxide, and the like, and combinations thereof. The first material layer 141 and the second material layer 142 have different etch selectivity. For example, a combination of silicon nitride and silicon oxide, a combination of silicon oxide and undoped polysilicon or amorphous silicon, a combination of silicon oxide or silicon nitride and amorphous carbon, or the like may be used. The deposition method of the first material layer 141 and the second material layer 142 of the stack structure may include chemical vapor deposition (CVD, PECVD, LPCVD, HDPCVD), Atomic Layer Deposition (ALD), or a physical vapor deposition method such as Molecular Beam Epitaxy (MBE), thermal oxidation, evaporation, sputtering, and the like, among various methods thereof. One of the first material layer 141 and the second material layer 142 may serve as a gate sacrificial layer, such as a silicon nitride layer. The stack serving as the gate sacrificial layer may also be another conductive layer, such as metal tungsten, cobalt, nickel, etc. Another material layer not serving as a gate sacrificial layer may be a dielectric material such as silicon oxide, for example, aluminum oxide, hafnium oxide, tantalum oxide, etc. In the embodiment of the present invention, the stack structure may be formed by alternately forming a material as a gate sacrificial layer and an oxide layer, or may be formed by alternately forming a metal layer and an oxide layer.

Each stack structure also has formed therein a channel hole 150 for forming a memory cell. A photomask may be used in conjunction with a corresponding etch process in a stacked structure to form the channel hole 150. Fig. 1A is not intended to limit the shape, location, and number of channel holes. In practice, a plurality of channel holes may be formed in the stack structure through the stack structure thereof.

The upper stack 120 is located above the lower stack 110, and is connected to the lower stack by an oxide layer 130. The channel holes of the upper stack 120 and the channel holes of the lower stack 110 are aligned with each other to form new channel holes 150. Due to the process limitation and the high aspect ratio of the channel hole, the channel hole 150 is not formed as a cylindrical hole having a uniform diameter at the top and bottom, but as a large diameter at the top and a small diameter at the bottom. A functional layer including a blocking layer 154, a charge trap layer 153, a tunneling layer 152, and a conductive layer 151 is sequentially stacked from a sidewall of the channel hole toward a center of the channel hole 150. Referring to fig. 1A, the functional layer thus formed may not be uniformly distributed in the trench hole 150, which may affect the electrical performance of the memory.

FIG. 1B is a circuit schematic of the memory of FIG. 1A. Referring to fig. 1B, the memory circuit includes two memory cell groups, a first memory cell group 160 and a second memory cell group 170. The first memory cell group 160 corresponds to the lower stack 110 in fig. 1A, and the second memory cell group 170 corresponds to the upper stack 120 in fig. 1A. Each Memory Cell group includes a plurality of Memory Cells (MC) and a plurality of Dummy Memory Cells (DMC). The first memory cell group 160 further includes a Bottom Select Transistor (BST) connected to a Source (Source), and the second memory cell group 170 further includes a Top Select Transistor (TST) connected to a Drain (Drain). The dummy memory cell has a similar structure to the memory cell, but is not used as the memory cell.

Referring to fig. 1B, the first memory cell group 160 is connected to each other through drain terminals of dummy memory cells located at an edge thereof and source terminals of dummy memory cells located at an edge thereof of the second memory cell group 170.

FIG. 1C is a schematic diagram of a programming timing diagram of the memory of FIG. 1A. Referring to fig. 1C, in the program operation, the memory composed of a plurality of stack structures is the same as the memory of a single stack structure. In this timing diagram, the programming phase of the memory is entered starting at the dashed line label. In this programming phase, a program voltage Vpgm is applied to the gate of a Selected Memory Cell (SMC), a pass voltage Vpass is applied to the gate of an UnSelected Memory Cell (USMC), a dummy Memory Cell pass voltage Vdummy is applied to the gate of a dummy Memory Cell, and a select gate pass voltage Von is applied to an upper select gate. Meanwhile, the drain terminal, the source terminal, the lower selection tube and the substrate of the memory are all kept at low potential.

In the embodiment of the invention, the low potentials are all 0V. In other embodiments, the low voltage level may be other voltage values.

According to the nonvolatile memory shown in fig. 1A to 1C, the following problems are caused due to the excessively long channel:

(1) the functional layer formed by the primary deposition has poor consistency;

(2) in the programming process, the memory string where the unselected memory cell is located needs to be inhibited by programming, and usually, an upper selection tube and a lower selection tube of the unselected string are turned off, so that a channel of the unselected string is in a floating state, and the channel is coupled with a certain potential due to Vpass, Vpgm and the like, so that the programming electric field of the unselected string is weakened, and the programming inhibition is realized. In an actual programming process, the channel potential coupled by Vpgm is higher than the channel potential coupled by Vpass, so that the channel coupling potential generated by Vpass pulls down the channel coupling potential generated by Vpgm, and the longer the channel, the stronger such pulling down effect, and thus the worse the program inhibit effect, the larger the disturbance caused by programming.

Fig. 2A is a schematic block diagram of a structure of a nonvolatile memory according to an embodiment of the present invention. Referring to fig. 2A, the nonvolatile memory includes a memory cell array 21 and a controller 22. The memory cell array 21 includes a plurality of memory strings. Each storage string comprises a first sub string and a second sub string which are connected in series, and the first sub string and the second sub string respectively comprise a plurality of storage units. A plurality of memory cells in the memory cell array 21 may be connected to the driver circuit 23 through Word Lines (WL), String Select Lines (SSL), Ground Select Lines (GSL), Common Source Lines (CSL), and the like, and may be connected to the read/write circuit 24 through Bit Lines (BL). The controller 22 may control the operations of the driving circuit 23 and the read/write circuit 24 in response to control signals transmitted from the outside. For example, in performing a read operation on a memory cell, the controller 22 may control the driving circuit 23 so that a voltage required for the read operation is supplied to a word line of the concerned memory cell; controller 22 may also control read/write circuits 24 to allow read/write circuits 24 to read data stored in a particular memory cell.

FIG. 2B is a circuit diagram of a memory string in a non-volatile memory according to an embodiment of the invention. Referring to fig. 2B, the memory string 200 includes a first sub string 210 and a second sub string 220 connected in series, and the first sub string 210 and the second sub string 220 respectively include a plurality of Memory Cells (MCs).

Referring to fig. 2B, an Intermediate String selection pipe (ISST) is connected between the first sub String 210 and the second sub String 220, and the Intermediate String selection pipe does not have a storage unit.

In some embodiments, the controller 22 of the non-volatile memory of the present invention is further configured to: during programming, a programming voltage is applied to the selected memory cell SMC of each memory string, a first turn-on voltage is applied to the unselected memory cells USMC, and a second turn-on voltage is applied to the middle string select pipe ISST, wherein the second turn-on voltage is greater than the first turn-on voltage for at least a portion of the period during the programming.

According to the embodiments, the channel potential of the unselected memory cells can be increased, and the interference of the programming operation on the unselected memory cells can be reduced.

In these embodiments, as shown with reference to fig. 2B, the memory string of the nonvolatile memory of the present invention may further include a first string select pipe SST1 and a second string select pipe SST 2. Wherein, the first string selection pipe SST1 is connected to the end (lower end in the figure) of the first sub-string 210 not connected to the intermediate string selection pipe ISST; the second string selection pipe SST2 is connected to the end (upper end in the drawing) of the second sub string 220 not connected to the intermediate string selection pipe ISST. The controller is configured to apply an off voltage to the first string select tube SST1 and an on voltage to the second string select tube SST2 during programming.

In some embodiments, as shown in fig. 2B, the nonvolatile memory of the present invention may further include a common source terminal CS connected to the first string select pipe SST1, and a drain terminal connected to the second string select pipe. The controller is configured to apply a ground voltage to the common source terminal and a turn-off voltage to the drain terminal during programming.

In the memory cell array, the first string select transistors in each memory string are connected to a common source terminal, and for the NAND type memory, a common source line CSL is formed; the second string selection tube in each memory string is connected to the drain end and then connected to the bit line of the memory through the drain end; the gate of each memory cell is connected to a word line of the memory; multiple memory strings may share the same Substrate (Substrate).

For a NAND type memory, the gates of the second string select transistors in different memory strings are connected to each other, forming a string select transistor SST; the gates of the first string select transistors in the different memory strings are connected to each other to form a ground select transistor GST. The gates of the first string selection tube and the second string selection tube of each memory string are respectively connected with the corresponding string selection word line.

Referring to fig. 2B, in some embodiments, the memory string of the nonvolatile memory of the present invention includes a plurality of dummy memory cells DMC in addition to the plurality of memory cells. In an actual memory manufacturing process, the reliability of the memory cells formed at the edges of the memory is low, so that the memory cells are used as dummy memory cells and are not used for actual read and write operations. It is understood that in some embodiments, the non-volatile memory may not have dummy memory cells.

Fig. 2B is not intended to limit the number of substrings concatenated in a memory string in the embodiment of the present invention. In some embodiments, a memory string may be formed from more than two multiple sub-strings connected in series. In these embodiments, an intermediate string selection pipe without a storage unit is connected between the plurality of sub-strings two by two. Accordingly, the controller is configured to: during programming, a programming voltage is applied to selected memory cells of each memory string, a first turn-on voltage is applied to unselected memory cells, and a second turn-on voltage is applied to all intermediate string select transistors, wherein the second turn-on voltage is greater than the first turn-on voltage for at least a portion of the time period during the programming.

The non-volatile memory described above may be a two-dimensional memory or a three-dimensional memory, such as a 3d nand memory.

FIGS. 3A and 3B are schematic diagrams of a programming timing sequence of a non-volatile memory according to an embodiment of the invention. Referring to fig. 3A and 3B, the programming phase of the memory is entered starting at the dashed line label. Typically, before the dotted line label, there is a pre-turn on phase of the memory. In the pre-turn-on phase, a pre-turn-on voltage is applied to the Drain terminal Drain of the memory and the second string select pipe SST 2. In the program phase, a program voltage Vpgm is applied to selected memory cells SMC of each memory string, a first pass voltage Vpass is applied to unselected memory cells USMC, and a second pass voltage Vpgm 'is applied to the middle string select pipe ISSG, wherein the second pass voltage Vpgm' is greater than the first pass voltage Vpass for at least a portion of the period during programming. The voltage applied to the memory cell is applied to its gate, and the voltage applied to the string select transistor is also applied to its gate.

In the embodiment shown in fig. 3A, the waveform of the second pass voltage Vpgm' applied to the intermediate string selection pipe is the same as the waveform of the program voltage Vpgm applied to the selected memory cell. In the pre-conduction stage, the voltage on the selected storage unit is at a low potential; after entering the programming phase, the program voltage Vpgm applied to the selected memory cell steps up. As shown in FIG. 3A, the program voltage Vpgm is raised to the first program voltage 311 for a period of time, then raised to the second program voltage 312 for a period of time, and then lowered directly to the same low level as the pre-conduction phase, indicating the end of the program phase for the selected memory cell. It is to be understood that the illustration of fig. 3A is merely an example and is not intended to limit the specific waveform and specific voltage values of the program voltage Vpgm. In other embodiments, the waveform of the program voltage Vpgm may be a waveform having a plurality of step levels including a plurality of different program voltage values.

In the embodiment shown in fig. 3A, the second pass voltage Vpgm' has the same waveform as the program voltage Vpgm. In the pre-conduction stage, the voltage applied to the middle string selection tube is at a low potential; after entering the programming phase, the second pass voltage Vpgm' rises to the first pass voltage value 321 for a period of time, and then rises to the second pass voltage value 322 for a period of time; the second pass voltage Vpgm' then drops directly to the same low level as the pre-pass phase.

Specifically, the voltage value of the second pass voltage Vpgm' may be the same as or different from the voltage value of the program voltage Vpgm. In some embodiments, the ratio of the voltage value of the second pass voltage Vpgm' to the voltage value of the program voltage Vpgm is between 0.9 and 1.1.

In an embodiment not shown, the second pass voltage Vpgm' has a waveform similar to or significantly different from the program voltage Vpgm. In these embodiments, the ratio of the voltage value of the second pass voltage Vpgm' to the voltage value of the program voltage Vpgm may be less than or equal to 1.1.

In the embodiment shown in FIG. 3A, the second pass voltage Vpgm' applied to the middle string select pipe is greater than the first pass voltage Vpass applied to the unselected memory cells for at least a portion of the period during programming. As shown in fig. 3A, the first pass voltage value 321 may be less than the first pass voltage Vpass, and the second pass voltage value 322 may be greater than the first pass voltage Vpass. Thus, the second pass voltage Vpgm' is greater than the first pass voltage Vpass at least during the portion of the second pass voltage value 322. In an embodiment of the invention, the at least a portion of the time period may be at least 1/4 of the time period during programming.

In other embodiments, both the first and second

pass voltage values

321 and 322 may be greater than the first pass voltage Vpass, such that the second pass voltage Vpgm' is greater than the first pass voltage Vpass throughout the programming period.

In the embodiment shown in fig. 3B, the waveform of the second pass voltage Vpgm' applied to the intermediate string selection pipe ISST is different from the waveform of the program voltage Vpgm applied to the selected memory cell SMC. Referring to FIG. 3B, the difference between the first pass voltage Vpgm 'and the pre-pass voltage Vpgm' is that after the program phase is entered, the second pass voltage Vpgm 'is raised to a fixed pass voltage value 330 and continues for a period of time until the program phase is completed, and the second pass voltage Vpgm' is lowered to the same low level as the pre-pass phase.

In the embodiment shown in FIG. 3B, the fixed pass voltage value 330 is greater than the first pass voltage Vpass.

Fig. 4A is a schematic structural diagram of a nonvolatile memory according to an embodiment of the present invention. Referring to fig. 4A, the nonvolatile memory of this embodiment includes a stack layer and a memory cell array. The stack layer includes a first stack 410 and a second stack 420 stacked, and a connection layer 430 located between the first stack 410 and the second stack 420. The first stack 410 and the second stack 420 each include gate layers 441 and dielectric layers 442, which are alternately stacked.

The memory cell array includes a plurality of memory strings, each including a first sub-string 450 and a second sub-string 460. Referring to FIG. 4A, a first substring 450 extends through first stack 410 and a second substring 460 extends through second stack 420. A first channel hole 411 and a second channel hole 421 penetrating the stack structures thereof are formed in the first stack 410 and the second stack 420, respectively. The first channel hole 411 and the second channel hole 421 are both cylindrical hole-shaped. Fig. 4A is a front cross-sectional view of a nonvolatile memory of an embodiment of the present invention, showing a front cross-sectional view of a memory string. As can be understood from the perspective of fig. 4A, the first substrings 450 are formed on the sidewalls of the first channel holes 411, have a cylindrical ring structure, and do not fill the space in the first channel holes 411. The second sub-strings 460 are formed on the sidewall of the second channel hole 421, and have a cylindrical ring structure, and do not fill the space in the second channel hole 421.

Referring to fig. 4A, the first sub string 450 includes a first channel layer 451, the second sub string 460 includes a second channel layer 461, and the first channel layer 451 and the second channel layer 461 are electrically connected through a channel connection portion 431. The first channel layer 451 is at the innermost ring of the first substring 450, adjacent to the void inside the first channel hole 411; the second channel layer 461 is at the innermost ring of the second sub-string 460, adjacent to the void inside the second channel hole 421.

Referring to fig. 4A, the stacked layers in the nonvolatile memory of this embodiment may be formed by alternately stacking the gate layers 441 and the dielectric layers 442, the extending direction of the stacked layers is defined as the extending direction D1, the stacking direction of the stacked layers is defined as the stacking direction D2, and D1 and D2 are perpendicular to each other. The connection layers 430 are distributed along the extension direction D1, parallel to the gate layers and the dielectric layers in the first and

second substrings

450, 460. The connection layer 430 is located between the dielectric layers of the first sub-string 410 and the dielectric layers of the second sub-string 420 in the stacking direction D2, i.e., the connection layer 430 is not in contact with the gate layers in the first sub-string 410 and the second sub-string 420.

The connection layer 430 is opposite to the channel connection 431 of the first and second channel layers 451 and 461 in the extending direction D1 of the stacked layers, and a dielectric layer is between the connection layer 430 and the channel connection 431.

In the present embodiment, the connection layer 430 and the channel connection portion 431 constitute an intermediate string selection pipe without memory cells, that is, an intermediate string selection pipe ISST shown in fig. 2B and fig. 3A and 3B. Since the first channel layer 451 of the first sub string 410 is electrically connected to the second channel layer 461 of the second sub string 420 through the channel connection portion 431, the middle string selection pipe is electrically connected between the first sub string 410 and the second sub string 420.

In some embodiments, referring to fig. 4A, first sub-string 450 further includes a first charge storage layer 452 therein, and second sub-string 460 further includes a second charge storage layer 462 therein, the first charge storage layer 452 and the second charge storage layer 462 not extending to the region 432 between the connection layer 430 and the channel connection 431. The region 432 is a dielectric layer.

The channel connection portion 431 between the first channel layer 451 and the second channel layer 461 in the present embodiment has a solid columnar shape.

In some embodiments, first charge storage layer 452 in first substring 450 includes a first tunneling layer 4521, a first charge-trapping layer 4522, and a first blocking layer 4523, and second charge storage layer 462 in second substring 460 includes a second tunneling layer 4621, a second charge-trapping layer 4622, and a second blocking layer 4623. In these embodiments, the first substring 450 is, in order from the sidewall of the first channel hole 411 toward the center, a first blocking layer 4523, a first charge trapping layer 4522, a first tunneling layer 4521, and a first channel layer 451; the second substrings 460 are, in order from the sidewall of the second channel hole 421 toward the center, a second blocking layer 4623, a second charge trapping layer 4622, a second tunneling layer 4621 and a second channel layer 461.

In an embodiment of the present invention, an exemplary material of the blocking layer and the tunneling layer is silicon oxide, silicon oxynitride or a mixture thereof, and an exemplary material of the charge trapping layer is silicon nitride or a multilayer structure of silicon nitride and silicon oxynitride. The blocking layer, the charge trapping layer, and the tunneling layer may be formed, for example, in a multilayer structure having silicon oxynitride-silicon nitride-silicon oxide (SiON/SiN/SiO); an exemplary material of the channel layer is polysilicon. It will be appreciated that other materials may be selected for these layers. For example, the material of the barrier layer may include a high-K (dielectric constant) oxide layer; the material of the channel layer may include monocrystalline silicon, monocrystalline germanium, SiGe, Si: C, SiGe: C, SiGe: H, and other semiconductor materials.

Referring to fig. 4A, the non-volatile memory according to the embodiment of the present invention is further filled with an insulating material in the space inside the first channel hole 411 and the space inside the second channel hole 421, so as to perform the functions of insulation and support. The insulating material may be the same or different material as the second material layer 442. The insulating material may be an oxide.

In some embodiments, the non-volatile memory shown in fig. 4A further includes a controller configured to, during programming, apply a programming voltage to selected memory cells of each memory string, apply a turn-on voltage to unselected memory cells, and apply a second turn-on voltage to the intermediate string select transistor, wherein the second turn-on voltage is greater than the turn-on voltage for at least a portion of the period during programming. The voltage value of the second pass voltage Vpgm' may be the same as or different from the voltage value of the program voltage Vpgm.

In some embodiments, the ratio of the voltage value of the second pass voltage Vpgm' to the voltage value of the program voltage Vpgm is between 0.9 and 1.1.

In other embodiments, the ratio of the voltage value of the second pass voltage Vpgm' to the voltage value of the program voltage Vpgm is less than or equal to 1.1.

Reference may be made to the description above corresponding to fig. 2A, 2B, 3A and 3B with respect to the controller and its operation during programming.

It should be noted that, in the embodiments of the present invention, all of the stacked layers, the storage strings, the first substrings, the second substrings, and the like are symmetrically distributed around the central axis of the channel hole, so that only a part of the structures may be labeled in the drawings, and the description of the part of the structures applies to the part of the structures that are not labeled and symmetrically distributed with the part of the structures.

FIG. 4A is not intended to limit the number of stacks and substrings in embodiments of the present invention. In some embodiments, the non-volatile memory of the present invention may be formed from more than two multiple stacks stacked together. In these embodiments, a substring is formed in each stack, and a connection layer and channel connections are formed between a plurality of adjacent substrings. Accordingly, the controller is configured to: during programming, a programming voltage is applied to selected memory cells of each memory string, a first turn-on voltage is applied to unselected memory cells, and a second turn-on voltage is applied to all intermediate string select transistors, wherein the second turn-on voltage is greater than the first turn-on voltage for at least a portion of the time period during the programming.

FIG. 4B is a schematic structural diagram of a nonvolatile memory according to another embodiment of the present invention. Referring to fig. 4B, the embodiment is different from fig. 4A in that a channel connection portion 431 between a first channel layer 451 and a second channel layer 461 in the embodiment has a hollow cylindrical shape.

Referring to fig. 4A and 4B, the channel connection 431 and the connection layer 430 constitute a middle string selection pipe without memory cells regardless of whether the channel connection 431 has a solid column shape or a hollow column shape. Thus, when the non-volatile memory is programmed, a higher second pass voltage Vpgm' is applied to the middle string selection pipe, so that the channel potential of the non-selected memory cell can be increased, and the potential difference between the channel potential and the pass voltage Vpass can be reduced, thereby reducing the interference of the programming operation on the non-selected memory cell.

Fig. 5 is an exemplary flowchart of a method of manufacturing a nonvolatile memory according to an embodiment of the present invention. As shown in fig. 5 and fig. 6A to 8C, the manufacturing method of the present embodiment includes the steps of:

at step 510, a first stack is formed.

Fig. 6A is a schematic process diagram of forming a first stack in the method for manufacturing a non-volatile memory according to an embodiment of the invention. Referring to fig. 6A, the first stack 610 formed in step 510 includes first material layers 641 and second material layers 642 that are alternately stacked.

In some embodiments, the first material layer 641 and the second material layer 642 can be a material selected from and including at least one insulating dielectric, such as silicon nitride, silicon oxide, amorphous carbon, diamond-like amorphous carbon, germanium oxide, aluminum oxide, and the like, and combinations thereof. The first material layer 641 and the second material layer 642 have different etch selectivity. For example, a combination of silicon nitride and silicon oxide, a combination of silicon oxide and undoped polysilicon or amorphous silicon, a combination of silicon oxide or silicon nitride and amorphous carbon, or the like may be used. The deposition methods of the first material layer 641 and the second material layer 642 of the first stack 610 may include chemical vapor deposition (CVD, PECVD, LPCVD, HDPCVD), Atomic Layer Deposition (ALD), or physical vapor deposition methods such as Molecular Beam Epitaxy (MBE), thermal oxidation, evaporation, sputtering, and the like, among other methods. One of the first material layer 641 and the second material layer 642 may serve as a gate sacrificial layer, such as a silicon nitride layer. The stack serving as the gate sacrificial layer may also be another conductive layer, such as metal tungsten, cobalt, nickel, etc. Another material layer not serving as a gate sacrificial layer may be a dielectric material such as silicon oxide, for example, aluminum oxide, hafnium oxide, tantalum oxide, etc.

In an embodiment of the invention, the first material layer 641 is a dummy gate layer, and the second material layer 642 is a dielectric layer.

Step 520, a first substring is formed that vertically traverses the first stack.

Fig. 6B and 6C are schematic diagrams of a process of forming the first sub-string in the method of manufacturing the nonvolatile memory according to the embodiment of the present invention. Referring to fig. 6B, a first channel hole 611 is first etched in the first stack 610. Referring to fig. 6C, a first sub-string 650 is padded in the first channel hole 611. In the present embodiment, the first sub string 650 includes a first channel layer 651. The first channel layer 651 may be a conductive material, such as polysilicon.

It is to be understood that fig. 6C is a front cross-sectional view of the non-volatile memory of an embodiment of the present invention, showing a front cross-sectional view of the first sub-string. As can be understood from the perspective of fig. 6C, the first substring 650 should have a ring-shaped structure and not fill the space in the first channel hole 611. The first channel layer 651 is at an innermost ring of the first substring 650, adjacent to the void inside the first channel hole 611.

In some embodiments, first sub-string 650 further includes a first charge storage layer 652.

In some embodiments, first charge storage layer 652 in first sub-string 650 includes a first tunneling layer 6521, a first charge trapping layer 6522, and a first blocking layer 6523. In these embodiments, the first blocking layer 6523, the first charge trapping layer 6522, the first tunneling layer 6521 and the first channel layer 651 are sequentially stacked on the sidewalls of the first channel holes 611 toward the center to form the first substrings 650.

Referring to fig. 6C, a second material layer 642 is disposed on top of the first stack 610 as a dielectric layer.

At step 530, a connection layer is formed on the first stack.

Fig. 6D and 6E are schematic diagrams illustrating a process of forming a connection layer in a method of manufacturing a nonvolatile memory according to an embodiment of the present invention. Referring to fig. 6D, an oxide, which may be the same as or different from the second material layer 642, is first filled in the gap of the first channel hole 611. A connection layer 630 is then formed on the first stack 610. Since the top of the first stack 610 is the second material layer 642, the connecting layer 630 is formed on the top second material layer 642. The connection layer 630 may use the same material or different material as the first material layer 641. The process of forming the connection layer 630 may be formed using a process similar to the deposition of the first material layer 641 and the second material layer 642.

Referring to fig. 6D, in some embodiments, after the connection layer 630 is formed, a second material layer 642 may also be formed on the connection layer 630.

In the manufacturing method according to the embodiment of the invention, after the first channel hole 611 is filled or the connection layer 630 is formed, and in some other processes, a step of performing planarization treatment on some surfaces may be further included.

Referring to fig. 6E, a channel connection portion 631 contacting the first channel layer 651 is formed. The channel connecting portion 631 is positioned above the first channel hole 611 and sized to cover a maximum aperture of the first channel hole 611. The channel connection portion 631 may be formed by etching and depositing the connection layer and the two second material layers 642 located thereabove and therebelow through a mask on the basis of the structure shown in fig. 6D.

The material of the channel connection portion 631 may be the same or different conductive material as the first channel layer 651.

As shown in fig. 6E, the channel connection portion 631 formed at this step may also be in contact with the connection layer 630.

At step 540, a second stack is formed on the connection layer.

Fig. 6F is a schematic process diagram of forming a second stack in the method for manufacturing a non-volatile memory according to an embodiment of the invention. Referring to fig. 6F, a second stack 620 is formed over the structure shown in fig. 6E. Similar to the first stack 610, the second stack 620 includes first material layers 641 and second material layers 642 that are alternately stacked. The description about the first material layer 641 and the second material layer 642 may refer to the description about the first stack 610.

The second stack 620 may be formed by alternately depositing a first material layer 641 and a second material layer 642 layer by layer over the first stack 610.

Referring to fig. 6F, the first material layer 641 of the second stack 620 positioned at the bottommost portion is in contact with the channel connection portion 631 in the first stack 610, and is in contact with the second material layer 642 above the connection layer 630.

At step 550, a second sub-string is formed that vertically traverses the second stack.

A nonvolatile memory obtained by the method of manufacturing a nonvolatile memory according to the present invention is shown in fig. 4A and 4B. Corresponding to the two embodiments of the non-volatile memory shown in fig. 4A and 4B, the manufacturing method in this step is slightly different, and step 550 is described in two embodiments below.

Corresponding to the embodiment of the non-volatile memory shown in FIG. 4A:

fig. 7A to 7C are schematic diagrams illustrating a process of forming the second sub-string in the method of manufacturing the nonvolatile memory according to an embodiment of the present invention. Referring to fig. 7A, a second sub-string 660 is formed in the second stack 620 through the second stack 620. Similar to the formation method of the first sub-string 650, first, a second channel hole 621 needs to be formed in the second stack 620 by etching; a second sub-string 660 may then be deposited in the second channel hole 621. In the present embodiment, the second sub-string 660 includes a second channel layer 661. The second channel layer 661 may be a conductive material. The second sub-string 660 should have a ring structure and not fill the space in the second channel hole 621. The second channel layer 661 is at an innermost ring of the second sub-string 660 adjacent to the void inside the second channel hole 621.

In some embodiments, as shown in fig. 7A, the second channel layer 661 is in contact with the channel connection portion 631. Since the first channel layer 651 is also in contact with the channel connection portion 631 and the first channel layer 651, the second channel layer 661, and the channel connection portion 631 may all be conductive materials, the three may be electrically connected.

In some embodiments, second sub-string 660 further includes a second charge storage layer 662. The first charge storage layer 652 and the second charge storage layer 662 are separated by a channel connection 631.

In some embodiments, the second charge storage layer 662 in the second sub-string 660 includes a second tunneling layer 6621, a second charge-trapping layer 6622, and a second blocking layer 6623. In these embodiments, the second blocking layer 6623, the second charge trapping layer 6622, the second tunneling layer 6621, and the second channel layer 661 are sequentially stacked on the sidewalls of the second channel holes 621 toward the center to form the second sub-strings 660.

Referring to fig. 7B, an insulating material is filled in the second channel hole 621. The insulating material may be the same or different material as the second material layer 642. In the process shown in fig. 7B, the first material layer 641 which is a dummy gate layer is also etched away. In the previous step, the connection layer 630 may also be the first material layer 641 serving as a dummy gate layer. Therefore, in this process, the first material layer 641 in the stacked structure of the first stack 610 and the second stack 620 and the first material layer 641 in the connection layer 630 are etched away at the same time.

In the process shown in fig. 7B, a channel connection portion 631 of an oxidation portion is further included. As shown in connection with fig. 7A and 7B, a portion where the channel connection portion 631 contacts the connection layer 630 is oxidized so that the first charge storage layer 652 and the second charge storage layer 662 do not extend to the region 632 between the connection layer 630 and the channel connection portion 631. That is, first charge storage layers 652 in first sub-string 650 and second charge storage layers 662 in second sub-string 660 are not electrically connected.

Further, in some embodiments, neither the first charge-trapping layer 6522 nor the first tunneling layer 6521 in the first sub-string 650, nor the second charge-trapping layer 6622 nor the second tunneling layer 6621 in the second sub-string 660, extend to the region 632 between the connection layer 630 and the channel connection 631.

Referring to fig. 7C, a conductive material is deposited at the portions of the first material layer 641 and the connection layer 630 etched away in the process of fig. 7B. The first material layer 641 marked in fig. 7C is formed into a gate layer of the non-volatile memory after being filled with a conductive material.

Fig. 7C shows a nonvolatile memory obtained by the method for manufacturing a nonvolatile memory according to the embodiment of the present invention. The nonvolatile memory is the same as the nonvolatile memory shown in fig. 4A. The channel connecting portion 631 has a solid columnar shape.

For the embodiment of the non-volatile memory shown in FIG. 4B, it can be fabricated in the following manner.

FIGS. 8A-8C are schematic views illustrating a process of forming a second sub-string in a method of manufacturing a non-volatile memory according to another embodiment of the invention. The process shown in fig. 8A is similar to the process shown in fig. 7A, except that when the second channel hole 621 is etched in the second stack 620, the channel connection portion 631 is also etched, so that the channel connection portion 631 has a hollow cylindrical structure. As shown in fig. 8A, the etching of the channel connection part 631 exposes the oxide filled in the first channel hole 611 of the first stack 610.

The process of depositing the second sub-string 660 in the second channel hole 621 is the same as that in fig. 7A, and reference may be made to the related description.

Referring to fig. 8B, the second channel hole 621 is filled with oxide, and a hollow portion of the channel connection portion 631 is also filled with oxide. The oxide in the first channel hole 611 is integrated with the oxide in the second channel hole 621 and the hollow portion of the channel connecting portion 631. In the process shown in fig. 8B, the etching of the first material layer 641 and the connection layer 630 as a dummy gate layer and the process of oxidizing the channel connection portion 631 of the portion are the same as those shown in fig. 7B, and the related description may be referred to.

Referring to fig. 8C, the nonvolatile memory obtained by the method of manufacturing the nonvolatile memory according to the embodiment of the present invention is the same as the nonvolatile memory shown in fig. 4B. The channel connecting portion 631 in fig. 8C has a hollow columnar shape.

In other embodiments, the above-described manufacturing method can be applied to the manufacture of a nonvolatile memory having more than two stacked stacks.

According to the method for manufacturing the non-volatile memory according to the embodiment of the present invention, the first substrings 650 in the first stack 610 and the second substrings 660 in the second stack 620 are formed, respectively, instead of forming the first substrings 650 and the second substrings 660 by pad-deposition once after stacking, uniformity and consistency of the functional layer and the conductive channel layer are improved.

Although the present invention has been described with reference to the present specific embodiments, it will be appreciated by those skilled in the art that the above embodiments are merely illustrative of the present invention, and various equivalent changes and substitutions may be made without departing from the spirit of the invention, and therefore, it is intended that all changes and modifications to the above embodiments within the spirit and scope of the present invention be covered by the appended claims.

Claims

1. A non-volatile memory, comprising:

the storage unit array comprises a plurality of storage strings, each storage string comprises a first sub string and a second sub string which are connected in series, and the first sub string and the second sub string respectively comprise a plurality of storage units; and

the middle string selection tube without the storage unit is connected between the first sub string and the second sub string;

further comprising:

a controller configured to: during programming, a programming voltage is applied to selected memory cells of each memory string, a first turn-on voltage is applied to unselected memory cells, and a second turn-on voltage is applied to the intermediate string select transistor, wherein the second turn-on voltage is greater than the first turn-on voltage for at least a portion of the period during the programming.

2. The nonvolatile memory of claim 1, wherein the waveform of the second turn-on voltage is the same as the waveform of the programming voltage, and a ratio of the second turn-on voltage to the programming voltage is between 0.9 and 1.1.

3. The non-volatile memory of claim 1, wherein a waveform of the second turn-on voltage is the same as a waveform of the first turn-on voltage, and a ratio of the second turn-on voltage to the programming voltage is less than or equal to 1.1.

4. The non-volatile memory of claim 1, further comprising:

the first string selection pipe is connected to one end of the first sub string which is not connected with the middle string selection pipe;

the second string selection pipe is connected to one end, which is not connected with the middle string selection pipe, of the second sub string;

wherein during the programming, an off voltage is applied to the first string select tubes and an on voltage is applied to the second string select tubes.

5. The non-volatile memory of claim 4, further comprising:

the common source end is connected with the first string selection pipe; and

the drain end is connected with the second string of selection pipes;

and applying a ground voltage to the common source terminal and applying a turn-off voltage to the drain terminal during the programming.

6. A method of operating a non-volatile memory, the non-volatile memory including a memory cell array and an intermediate string select pipe without memory cells, the memory cell array including a plurality of memory strings, each memory string including a first sub-string and a second sub-string connected in series, the first sub-string and the second sub-string respectively including a plurality of memory cells, the intermediate string select pipe connected between the first sub-string and the second sub-string, wherein the method includes:

during programming, a programming voltage is applied to selected memory cells of each memory string, a first turn-on voltage is applied to unselected memory cells, and a second turn-on voltage is applied to the intermediate string select transistor, wherein the second turn-on voltage is greater than the first turn-on voltage for at least a portion of the period during the programming.

7. A non-volatile memory, comprising:

the stacked layer comprises a first stacked layer and a second stacked layer which are stacked and a connecting layer positioned between the first stacked layer and the second stacked layer, and the first stacked layer and the second stacked layer respectively comprise gate layers and dielectric layers which are stacked alternately; and

the storage unit array comprises a plurality of storage strings, each storage string comprises a first substring and a second substring, the first substring vertically penetrates through the first stack, the second substring vertically penetrates through the second stack, the first substring comprises a first channel layer, the second substring comprises a second channel layer, and the first channel layer is electrically connected with the second channel layer;

the connecting layer is opposite to the channel connecting parts of the first channel layer and the second channel layer in the extending direction of the stacked layer, a medium layer is arranged between the connecting layer and the channel connecting parts, and the connecting layer and the channel connecting parts form a middle string selection tube without a storage unit and are electrically connected between the first sub string and the second sub string;

further comprising a controller configured to: during programming, a programming voltage is applied to selected memory cells of each memory string, a first turn-on voltage is applied to unselected memory cells, and a second turn-on voltage is applied to the intermediate string select transistor, wherein the second turn-on voltage is greater than the first turn-on voltage for at least a portion of the period during the programming.

8. The non-volatile memory of claim 7, wherein the first sub-string includes a first charge storage layer and the second sub-string includes a second charge storage layer, wherein the first charge storage layer and the second charge storage layer do not extend to a region between the connection layer and the channel connection.

9. The nonvolatile memory according to claim 7, wherein a channel connection portion of the first channel layer and the second channel layer is a hollow pillar shape or a solid pillar shape.

10. The nonvolatile memory of claim 7, wherein the waveform of the second turn-on voltage is the same as the waveform of the programming voltage, and a ratio of the second turn-on voltage to the programming voltage is between 0.9 and 1.1.

11. The non-volatile memory of claim 7, wherein the second turn-on voltage has a waveform that is the same as the first turn-on voltage, and wherein the second turn-on voltage and the programming voltage are less than or equal to 1.1.