CN112447257A - Test structure and test method - Google Patents

Test structure and test method Download PDF

Info

Publication number
CN112447257A
CN112447257A CN201910819101.4A CN201910819101A CN112447257A CN 112447257 A CN112447257 A CN 112447257A CN 201910819101 A CN201910819101 A CN 201910819101A CN 112447257 A CN112447257 A CN 112447257A
Authority
CN
China
Prior art keywords
test
conductive layer
layer
excitation signal
excitation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201910819101.4A
Other languages
Chinese (zh)
Other versions
CN112447257B (en
Inventor
何世坤
杨晓蕾
王明
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CETHIK Group Ltd
Hikstor Technology Co Ltd
Original Assignee
CETHIK Group Ltd
Hikstor Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by CETHIK Group Ltd, Hikstor Technology Co Ltd filed Critical CETHIK Group Ltd
Priority to CN201910819101.4A priority Critical patent/CN112447257B/en
Publication of CN112447257A publication Critical patent/CN112447257A/en
Application granted granted Critical
Publication of CN112447257B publication Critical patent/CN112447257B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C2029/5004—Voltage
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C2029/5006—Current
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C29/50008—Marginal testing, e.g. race, voltage or current testing of impedance

Abstract

The application provides a test structure and a test method, which are used for testing a memory array comprising a plurality of resistive devices. The test structure includes: the memory array comprises a plurality of resistive switching devices, wherein each resistive switching device comprises at least one magnetic layer; the first conducting layer is arranged in contact with at least part of the resistance change device, the length extending direction of the first conducting layer is a first direction, and the first direction is vertical to the thickness direction of the resistance change device; and the second conducting layer is electrically connected with the first conducting layer, the extending direction of the second conducting layer is a second direction, the second direction is vertical to the first direction, and the second direction is vertical to the thickness direction of the resistance change device. The test structure tests the memory array comprising the plurality of resistive devices, avoids testing the plurality of resistive devices one by one, greatly shortens the test time, and solves the problem that the time required for obtaining the distribution curve of the switching magnetic field, the switching current or the switching voltage is long in the prior art.

Description

Test structure and test method
Technical Field
The present application relates to the field of memories, and in particular, to a test structure and a test method.
Background
In recent years, a rapidly developed Magnetic Random Access Memory (MRAM) has excellent characteristics, for example, the defects of large SRAM area and large electric leakage after the size is reduced are overcome; the defects that the DRAM needs to be refreshed all the time and the power consumption is large are overcome; compared with Flash memory, the read-write time and the read-write times are superior to those of Flash memory by several orders of magnitude.
Although having a number of significant advantages, it is common for core memory cells of current MRAM memories to employ a magnetic tunnel junction with perpendicular magnetization characteristics having at least 3 magnetic layers, a magnetic memory layer, a magnetic reference layer, and a magnetic pinning layer.
The magnetic layers have different functions, and key parameters of each functional layer, such as coercive force field (Hc), coupling field (Hex) and the like, need to meet certain conditions in order to meet various performance indexes of the MRAM. As a magnetic memory device, magnetic switching fields of all layers of the MTJ represent various performances such as interlayer coupling strength, stability and the like, and play an important role in failure analysis of the device, so that the test of a switching magnetic field is particularly important.
In the research and development stage, in order to obtain the magnetic switching field distribution of the MTJ device and analyze the performance and failure mechanism of the MTJ, a large number of MTJ samples are tested, the samples are generally tested one by one, and then the test data is processed and analyzed.
Specifically, the resistance versus magnetic field (R _ H) curve of a large number of MTJ devices is measured in the prior art:
step S1, applying external magnetic field to each MTJ from HstartScan to HendFrom HendScan to HstartObtaining an R _ H curve and obtaining a magnetic field value H corresponding to the change of the MTJ statei(subscript i represents the ith test);
step S2, repeating step S1, and testing the resistance variation (R _ H) curves of the N MTJs along with the magnetic field, as shown in FIG. 1;
in step S3, the data is processed to obtain a plurality of MTJ Hc probability distribution curves, as shown in fig. 2.
The testing method needs to test the MTJs one by one, needs to perform R-H curve scanning for a plurality of times to calculate the distribution curve of the magnetic flip field, and takes a very long time for testing. In addition, the test must ensure that the upper and lower electrodes of the MTJ are manufactured, and the required process steps are multiple, the feedback time is long, and the rapid iteration of material and device research and development is not facilitated.
The above information disclosed in this background section is only for enhancement of understanding of the background of the technology described herein and, therefore, certain information may be included in the background that does not form the prior art that is already known in this country to a person of ordinary skill in the art.
Disclosure of Invention
The application mainly aims to provide a test structure and a test method, so as to solve the problem that in the prior art, the time required for obtaining a distribution curve of a switching magnetic field, a switching current or a switching voltage is long.
To achieve the above object, according to one aspect of the present application, there is provided a test structure for testing a memory array including a plurality of resistive devices, including: the memory array comprises a plurality of resistive switching devices, wherein each resistive switching device comprises at least one magnetic layer; the first conducting layer is arranged in contact with at least part of the resistance change device, the length extending direction of the first conducting layer is a first direction, and the first direction is perpendicular to the thickness direction of the resistance change device; the second conducting layer is electrically connected with the first conducting layer, the extending direction of the second conducting layer is a second direction, the second direction is perpendicular to the first direction, and the second direction is perpendicular to the thickness direction of the resistive switching device.
Further, the test structure further comprises: a first electrode pair comprising two first electrodes, each of the first electrodes being electrically connected to the first conductive layer, respectively; and the second electrode pair comprises two second electrodes, and each second electrode is electrically connected with the second conductive layer respectively.
Furthermore, the test structure further comprises a plurality of interconnection structures, each of which comprises a plurality of first interconnection structures and a plurality of second interconnection structures, wherein one of the first interconnection structures is located between the first conductive layer and one of the first electrodes, the first conductive layer is electrically connected with one of the first electrodes through the first interconnection structure, one of the second interconnection structures is located between the second conductive layer and one of the second electrodes, and the second conductive layer is electrically connected with one of the second electrodes through the second interconnection structure.
Furthermore, at least part of the interconnection structure comprises a conductive through hole and an interconnection metal layer which are arranged along the direction far away from the storage array and connected with each other, and the interconnection metal layer is connected with the first electrode or the second electrode.
Further, the test structure further comprises: and the storage array, the first conducting layer, the second conducting layer and the interconnection structure are all positioned in the insulating medium layer.
Further, each resistive switching device includes a bottom electrode, a memory portion, and a top electrode stacked in sequence, the first conductive layer and the second conductive layer are both located on a first surface, or the first conductive layer and the second conductive layer are both located on a second surface, the first surface is a surface of the bottom electrode away from the memory portion, and the second surface is a surface of the top electrode away from the memory portion.
Further, at least a part of the resistive device is arranged in the first conductive layer, and at least a part of the resistive device is arranged in the second conductive layer.
Further, there are two first conductive layers and two second conductive layers, one of the first conductive layers and one of the second conductive layers are located on the first surface, and the other of the first conductive layers and the other of the second conductive layers are located on the second surface.
Further, the materials of the first conductive layer and the second conductive layer are respectively selected from at least one of Pt, Ta, W, Ir, Hf, Ru, Tl, Bi, Au and Os.
Further, the material of the first conductive layer and the second conductive layer is respectively selected from at least one of Ta, TaN, TiN, Pt, Ta, W, Ir, Hf, Ru, Tl, Bi, Au and Os.
According to another aspect of the present application, there is provided the test method including: step S1, applying an excitation signal to the test structure, wherein the excitation signal is an excitation electrical signal or an excitation magnetic signal, the excitation electrical signal is applied to two ends of the first conductive layer, and the excitation magnetic signal is applied to a space where the test structure is located; step S2, applying detection current at two ends of the first conducting layer, detecting test voltage between two ends of the second conducting layer, and obtaining test resistance according to the detection current and the test voltage; step S3, repeating the step S1 and the step S2 in sequence for a plurality of times until at least one magnetic layer of the resistive switching device is turned over, so as to obtain a first relational expression, where the first relational expression is a relational expression between the test resistance and the excitation signal, and at least a part of the obtained test resistances are different, and in each repetition, the excitation signal at the next time is greater than or less than the excitation signal at the previous time, and the excitation signal changes monotonically; step S5, obtaining performance parameters of the resistive switching device at least according to the first relational expression, where the performance parameters include a mean value and a standard deviation of an inversion electrical signal of the memory array when the excitation signal is an excitation electrical signal, the inversion electrical signal includes an inversion voltage and an inversion current, and the performance parameters include a mean value and a standard deviation of an inversion magnetic field of the memory array when the excitation signal is an excitation magnetic signal.
Further, before the step S1, the testing method further includes: and initializing each resistance change device to enable each resistance change device to be in the same resistance state.
Further, initializing each resistive switching device includes at least one of: applying an initialization voltage to two ends of the memory array, applying an initialization current to two ends of the memory array, and applying an initialization magnetic field in a space where the memory array is located.
Further, in step S3, the excitation signal applied last time is an end-point excitation signal, and the testing method further includes: step S4, repeating the step S1 and the step S2 several times in sequence until at least one of the magnetic layers of the resistive switching device is flipped to obtain a second relation, where the second relation is a relation between the test resistance and the excitation signal, and at least a portion of the obtained test resistances are different, in the process of repeating the steps several times, a difference between the excitation signal at the next time and the excitation signal at the previous time is a first difference, a difference between the excitation signal at the next time and the excitation signal at the previous time in the step S3 is a second difference, one of the first difference and the second difference is greater than 0, and the other is less than 0.
Further, in step S3, the difference between the excitation signal of the next time and the excitation signal of the previous time is a first predetermined difference, and in step S4, the difference between the excitation signal of the next time and the excitation signal of the previous time is a second predetermined difference, where the first predetermined difference is equal to the second predetermined difference.
Further, the step S5 includes: fitting the first relational expression to obtain at least one fitting formula; and acquiring the performance parameters according to the fitting formula.
Further, fitting the first relation to obtain at least one fitting formula, including: taking a differential of the variable corresponding to the excitation signal on the first relational expression to obtain a third relational expression, wherein the variable corresponding to the excitation signal is current or voltage under the condition that the excitation signal is an excitation electric signal, and the variable corresponding to the excitation signal is a magnetic field under the condition that the excitation signal is an excitation magnetic signal; and performing normal distribution fitting on the third relational expression to obtain the fitting formula.
Further, fitting the first relation to obtain at least one fitting formula, including: and fitting the cumulative probability distribution of the first relational expression to obtain the fitting formula.
Further, the step S5 includes: fitting the first relational expression and the second relational expression according to a fitting function to obtain a fitting formula; and acquiring the performance parameters according to the fitting formula.
By applying the technical scheme of the application, in the test structure, the first conducting layer is in contact with at least part of the resistance change device, the second conducting layer is electrically connected with the first conducting layer, in the test process, applying an excitation signal to the test structure, applying a detection current across the first conductive layer, detecting a test voltage across the second conductive layer based on the abnormal hall effect, then obtaining a test resistance according to the test voltage and the test current, applying an excitation signal to the test structure for multiple times, and obtaining the test resistance through the test, wherein the excitation signal of the next time is greater than or less than the excitation signal of the previous time until at least one magnetic layer of the memory array is turned over, so as to obtain a relational expression between the test resistance and the excitation signal, thereby obtaining the mean value and standard deviation of the switching magnetic field, the switching current or the switching voltage of the memory array. The test structure tests the memory array comprising the plurality of resistive devices, avoids testing the plurality of resistive devices one by one, greatly shortens the test time, and solves the problem that the time required for obtaining the distribution curve of the switching magnetic field, the switching current or the switching voltage is long in the prior art.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this application, illustrate embodiments of the application and, together with the description, serve to explain the application and are not intended to limit the application. In the drawings:
FIG. 1 shows a graphical representation of the resistance of an MTJ versus a test magnetic field of a prior art test method;
FIG. 2 shows a schematic diagram of the switching field profile of a MTJ of a prior art test method;
FIG. 3 shows a Hall effect schematic;
FIG. 4 is a graph showing Hall resistivity versus applied magnetic field for anomalous Hall effects;
FIG. 5 shows a schematic diagram of a test structure according to an exemplary embodiment of the present application;
FIG. 6 shows a schematic cross-sectional view of the test structure of FIG. 5 in a first orientation;
FIG. 7 shows a schematic cross-sectional view of a first orientation of a test structure according to an embodiment of the present application;
FIG. 8 shows a schematic cross-sectional view of a first orientation of a test structure according to an embodiment of the present application;
FIG. 9 shows a schematic cross-sectional view of a first orientation of a test structure according to an embodiment of the present application;
FIG. 10 shows a schematic flow diagram of a testing method according to an embodiment of the present application;
FIG. 11 illustrates a graph of test resistance versus test magnetic field according to an embodiment of the present application;
FIG. 12 shows a graph of test resistance versus test magnetic field according to example 1 of the present application;
FIG. 13 shows a plot of test resistance versus test magnetic field according to example 2 of the present application;
FIG. 14 shows a schematic diagram of a test structure according to examples 7 and 8 of the present application;
FIG. 15 shows a diagram of pulsed excitation voltage versus time according to example 8 of the present application;
FIG. 16 shows a schematic of the detected current versus time according to example 8 of the present application; and
fig. 17(a) and 17(b) show graphs of the hall effect versus the test voltage, respectively, according to embodiment 8 of the present application.
Wherein the figures include the following reference numerals:
10. a storage array; 20. a first conductive layer; 30. a second conductive layer; 40. a first electrode; 50. a second electrode; 60. a first interconnect structure; 70. and an insulating dielectric layer.
Detailed Description
It should be noted that the following detailed description is exemplary and is intended to provide further explanation of the disclosure. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.
It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments according to the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, and it should be understood that when the terms "comprises" and/or "comprising" are used in this specification, they specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof, unless the context clearly indicates otherwise.
It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. Also, in the specification and claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element or "connected" to the other element through a third element.
Interpretation of terms:
hall effect: as shown in fig. 3, a non-magnetic metal or semiconductor wafer is placed in the xy-plane with an applied electric field E in the x-direction and an applied magnetic field B perpendicular to the plane of the wafer in the z-direction, where the carriers in the material are not only subjected to the force from the applied electric field to move in the x-direction, but also to the lorentz force of the magnetic field to produce additional lateral motion in the y-direction, which will cause charge accumulation on both sides of the wafer, thereby producing a lateral hall voltage in the y-direction.
Abnormal hall effect: in a ferromagnetic metal material sample, the magnitude of the transverse resistivity includes a normal term, and a normal term related to the magnitude of the magnetization M of the sample is additionally added, and when the sample reaches the saturation magnetization Ms, the normal term becomes constant. Fig. 4 shows the dependence of the lateral hall resistivity on the magnitude of the magnetic field B, where the lateral resistivity ρ xy increases rapidly with increasing applied magnetic field B, and then increases linearly and slowly after an inflection point until saturation, which apparently cannot be explained simply by the lorentz force of the magnetic field, and thus this phenomenon is called anomalous hall effect.
As described in the background, the time required to obtain the distribution curve of the switching field, switching current or switching voltage is long in the prior art. To solve this technical problem, according to an embodiment of the present application, there is provided a test structure for testing a memory array including a plurality of resistive switching devices.
Fig. 5 to 9 show schematic diagrams of test structures of exemplary embodiments of the present application. Should include test structure:
the memory array 10 includes a plurality of resistive devices, each of which includes at least one magnetic layer;
a first conductive layer 20 provided in contact with at least a part of the resistance variable device, the first conductive layer having a first direction of longitudinal extension, the first direction being perpendicular to a thickness direction of the resistance variable device;
and a second conductive layer 30 electrically connected to the first conductive layer, wherein the second conductive layer extends in a second direction perpendicular to the first direction, and the second direction is perpendicular to the thickness direction of the resistive device.
In the test structure, a first conductive layer is arranged in contact with at least part of the resistive random access devices, a second conductive layer is electrically connected with the first conductive layer, in the test process, after an excitation signal is applied to the test structure, a detection current is applied to two ends of the first conductive layer, a test voltage between two ends of the second conductive layer is detected according to the abnormal hall effect, then a test resistance can be obtained according to the test voltage and the detection current, the excitation signal is applied to the test structure for multiple times, the test resistance is obtained through testing, the excitation signal of the next time is greater than or less than the excitation signal of the previous time until at least one magnetic layer of the memory array is turned over, and a relational expression between the test resistance and the excitation signal is obtained, so that the mean value and the standard deviation of the turning magnetic field, the turning current or the turning voltage of the. The test structure tests the memory array comprising the plurality of resistive devices, avoids testing the plurality of resistive devices one by one, greatly shortens the test time, and solves the problem that the time required for obtaining the distribution curve of the switching magnetic field, the switching current or the switching voltage is long in the prior art.
In order to facilitate inputting of excitation electrical signals to the first conductive layer and the second conductive layer, in a specific embodiment of the present application, as shown in fig. 5, the test structure further includes a first electrode pair and a second electrode pair, wherein the first electrode pair includes two first electrodes 40, and each of the first electrodes 40 is connected to the first conductive layer 20; the second electrode pair includes two second electrodes 50, and each of the second electrodes 50 is electrically connected to the second conductive layer 30. Specifically, as shown in fig. 3, two first electrodes 40 are electrically connected to both ends of the first conductive layer 20, respectively, and two second electrodes 50 are electrically connected to both ends of the second conductive layer 30, respectively.
In a specific embodiment of the present application, as shown in fig. 6, the test structure further includes a plurality of interconnection structures, and the plurality of interconnection structures includes a plurality of first interconnection structures 60 and a plurality of second interconnection structures, wherein one of the first interconnection structures 60 is located between the first conductive layer 20 and one of the first electrodes 40, the first conductive layer 20 is electrically connected to one of the first electrodes 40 through the first interconnection structure 60, one of the second interconnection structures (not shown in the figure due to an angle problem) is located between the second conductive layer 30 and one of the second electrodes 50, and the second conductive layer 30 is electrically connected to one of the second electrodes 50 through the second interconnection structure.
It should be noted that fig. 6 is a schematic cross-sectional view of the test structure of fig. 5 in the first direction, and therefore, the interconnect structure and the electrode in fig. 6 are the first interconnect structure 60 and the first electrode 40, respectively, and the second interconnect structure and the second electrode 50 are not shown in fig. 6.
In order to further improve the accuracy of the test structure, in a specific embodiment of the present application, at least a portion of the interconnection structure includes a conductive via and an interconnection metal layer disposed and connected in a direction away from the memory array, and the interconnection metal layer is connected to the first electrode or the second electrode.
In order to prevent the test structure from generating leakage current and further improve the accuracy and safety of the test, in a specific embodiment of the present application, as shown in fig. 6, the test structure further includes an insulating dielectric layer 70, and the memory array 10, the first conductive layer 20, the second conductive layer 30 and the interconnect structure are all located in the insulating dielectric layer.
In an actual testing process, the more resistive devices in the tested memory array are, the higher the device density in the test structure is, and the higher the probability of generating leakage current by the test structure is, so that the devices of the test structure need to be arranged in the insulating medium layer to avoid generating leakage current by the test structure.
In an embodiment of the present application, each of the resistive switching devices includes a bottom electrode, a memory portion, and a top electrode stacked in this order, the first conductive layer is located on a first surface or a second surface of the memory array, the second conductive line layer is located on the first surface or the second surface, the first surface is a surface of the bottom electrode away from the memory portion, and the second surface is a surface of the top electrode away from the memory portion.
Specifically, the memory portion of the resistive random access device comprises a pinning layer, a reference layer, an insulating barrier layer and a free layer, wherein the reference layer, the insulating barrier layer and the free layer are sequentially stacked on the bottom electrode, and the reference layer, the pinning layer and the free layer are all magnetic layers and can generate an abnormal hall effect to turn over in a test process.
In another specific embodiment of the present application, as shown in fig. 6, the first conductive layer 20 and the second conductive layer are both located on the first surface, and in another embodiment, as shown in fig. 7, the first conductive layer 20 and the second conductive layer are both located on the second surface.
Specifically, when the first conductive layer and the second conductive layer are both located on the first surface, that is, the first conductive layer and the second conductive layer are both connected with the bottom electrode of the resistive switching device in the memory array, in the test structure, the abnormal hall effect generated by the reference layer and the pinning layer of the resistive switching device is stronger, so that the hall resistance of the resistive switching device is changed more in the test process, and the test accuracy of the test structure can be improved; when the first conducting layer and the second conducting layer are both located on the second surface, namely the first conducting layer and the second conducting layer are both connected with the top electrode of the resistance change device in the memory array, in the test structure, the abnormal Hall effect generated by the free layer of the resistance change device is stronger, so that the Hall resistance of the resistance change device is changed more in the test process, and the test accuracy of the test structure can be improved.
In still another specific embodiment of the present application, as shown in fig. 8, at least a part of the resistive device is provided in the first conductive layer 20, and at least a part of the resistive device is provided in the second conductive layer.
Of course, the first conductive layer and the second conductive layer in the test structure are not limited to be arranged in the above structure, the first conductive layer and the second conductive layer of the test structure may also be arranged in other structures, and those skilled in the art may select a suitable structure of the first conductive layer and the second conductive layer according to practical situations. For example, the first conductive layer may be on the first surface and the second conductive layer may be on the second surface, or the first conductive layer may be on the second surface and the second conductive layer may be on the first surface.
In order to further improve the testing accuracy of the test structure, in another specific embodiment of the present application, as shown in fig. 9, there are two first conductive layers 20 and two second conductive layers 30, one first conductive layer 20 and one second conductive layer 30 are located on the first surface, and the other first conductive layer 20 and the other second conductive layer 30 are located on the second surface. When the test structure with the structure is used for testing, the magnetic layer, close to the first surface, of the resistance change device is tested through the first conducting layer 20 and the second conducting layer 30 which are located on the first surface, the magnetic layer, close to the second surface, of the resistance change device can be tested through the first conducting layer 20 and the second conducting layer 30 which are located on the first surface, two tests can be conducted simultaneously, the test efficiency is improved, the two magnetic layers are stronger in abnormal Hall effect, the Hall resistance of the resistance change device in the test process is larger in change, and the test accuracy of the test structure can be improved.
In an embodiment of the present application, the resistive switching device in the memory array is an MTJ, and the MTJ is a perpendicular magnetization MTJ.
In one embodiment of the present application, a material of the first conductive layer and the second conductive layer is at least one selected from Ta, TaN, TiN, Ru, W, Cu, Pt, Mo, and Al.
In another embodiment of the present application, a material of the first conductive layer and the second conductive layer is at least one selected from Pt, Ta, W, Ir, Hf, Ru, Tl, Bi, Au, and Os. Specifically, when the first conductive layer and the second conductive layer are formed using the above materials, the first conductive layer and the second conductive layer can be used as spin orbit torque supply lines.
In order to improve the accuracy of the test, in a specific embodiment of the present application, the thickness of the first conductive layer and the second conductive layer ranges from 5 nm to 10 nm. The thicknesses of the first conductive layer and the second conductive layer are set within the above ranges, which not only ensures that the abnormal hall effect can be detected by the test structure, but also prevents the first conductive layer and the second conductive layer from being insulated.
In another exemplary embodiment of the application, a testing method is provided, and fig. 10 shows a flow chart of the testing method according to an embodiment of the application, which includes the following steps:
step S1, applying an excitation signal to the test structure, where the excitation signal is an excitation electrical signal or an excitation magnetic signal, the excitation electrical signal is applied to both ends of the first conductive layer, and the excitation magnetic signal is applied to a space where the test structure is located;
step S2 of applying a test current to both ends of the first conductive layer, detecting a test voltage between both ends of the second conductive layer, and obtaining a test resistance from the test voltage and the test current;
step S3, repeating the steps S1 and S2 a plurality of times until at least one magnetic layer of the resistive switching device is inverted, obtaining a first relational expression, wherein the first relational expression is a relational expression between the test resistance and the excitation signal, and at least a part of the obtained test resistances are different, and each time the process is repeated, the excitation signal at the next time is greater than or less than the excitation signal at the previous time, and the excitation signal changes monotonously;
step S5, obtaining performance parameters of the resistive switching device at least according to the first relational expression, where the performance parameters include a mean value and a standard deviation of an inversion electrical signal of the memory array when the excitation signal is an excitation electrical signal, the inversion electrical signal includes an inversion voltage and an inversion current, and the performance parameters include a mean value and a standard deviation of an inversion magnetic field of the memory array when the excitation signal is an excitation magnetic signal.
In the test method, after an excitation signal is applied to a test structure, detection current is applied to two ends of a first conductive layer, test voltage between two ends of a second conductive layer is detected according to an abnormal Hall effect, then a test resistance can be obtained according to the test voltage and the detection current, the excitation signal is applied to the test structure for multiple times, the test resistance is obtained through testing, the excitation signal of the next time is larger than or smaller than the excitation signal of the previous time until at least one magnetic layer of the memory array is turned over, a relational expression of the test resistance and the excitation signal is obtained, and therefore the mean value and the standard deviation of the turning magnetic field, the turning current or the turning voltage of the memory array are obtained. The testing method tests the memory array comprising the plurality of resistive devices, avoids testing the plurality of resistive devices one by one, greatly shortens the testing time, and solves the problem that the time required for obtaining the distribution curve of the upset signal is long in the prior art.
In the present application, the excitation signal may be positive or negative, and is not the magnitude (i.e., absolute value) of the applied excitation signal, and the specific relationship between the magnitudes of the previous excitation signal and the next excitation signal is a positive-negative magnitude relationship, for example, -5000Oe < -3000Oe, -10V/cm < -5V/cm.
And the test method can obtain the test result only by applying the excitation signal to the whole memory array for multiple times without testing the resistive devices one by one, thereby greatly shortening the test time compared with the existing test method, the test result directly reflects the statistical information of the resistive device array, when the magnetic parameter of the device deviates from the design value, the test method can simultaneously process the obtained relational expressions between different types of test resistors and the excitation signal by the same method, and can obtain a distribution curve of a turning magnetic field, a turning current or a turning voltage without removing the failed device, the data processing is simple and convenient, the data processing working time is saved, the test method utilizes few test resources, and does not need to improve the hardware of the existing test machine or increase hardware equipment.
In order to ensure that the magnetic layer of each of the resistive switching devices can be flipped during the testing process to obtain more test data, so as to obtain more accurate mean and standard deviation of the flipping magnetic field, the flipping current, or the flipping voltage, in an embodiment of the present application, before the step S1, the testing method further includes: and initializing each resistance change device to enable each resistance change device to be in the same resistance state. Specifically, the resistance change device generally has two resistance states, namely a high resistance state and a low resistance state, and when the resistance change device is initialized, the resistance change device can be in the low resistance state, and the resistance change device can be in the high resistance state. One of the high resistance state and the low resistance state is a first resistance state and the other is a second resistance state.
In an actual testing process, there are various ways to initialize each resistance change device, and a person skilled in the art can select any way to make each resistance change device in the same resistance state. In an embodiment of the application, initializing each of the resistive switching devices includes at least one of: an initialization voltage is applied to both ends of the memory array, an initialization current is applied to both ends of the memory array, and an initialization magnetic field is applied in a space where the memory array is located. The resistance variable devices may be any one of the three types described above, or may be a mixture of a plurality of types, as long as the magnetization directions of the magnetic layers of the resistance variable devices are all the same, and the resistance variable devices are in the same resistance state.
In a specific embodiment of the present application, as shown in fig. 11, the resistive switching devices include a free layer, a reference layer and a pinned layer, and before the step S1, the magnetization directions of the magnetic layers of the resistive switching devices are all the first magnetization direction, that is, the resistive switching devices are in the same resistance state, when the abnormal hall resistances R and C of the second conductive layer are present1Msf+C2Msr+C3Msp is proportional, and the step S3 includes: repeating the above steps S1 and S2 for several times until all the reference layers in the memory array are flipped to form antiferromagnetic coupling with the pinned layer, wherein the abnormal Hall resistances R and C of the second conductive layer1Msf-C2Msr+C3Msp is proportional; repeating the above steps S1 and S2 for several times until all the free layers of the memory array are turned over, wherein the abnormal Hall resistances R and-C of the second conductive layer1Msf-C2Msr+C3Msp is proportional; repeating the above steps S1 and S2 for several times until all the pinned layers of the memory array are flipped, and the flipped pinned layers drive the reference layer to be flipped, during which the abnormal Hall resistances R and-C of the second conductive layer1Msf+C2Msr-C3Msp is proportional; repeating the above steps S1 and S2 for several times until all the reference layers of the memory array are inverted, wherein the abnormal Hall resistances R and-C of the second conductive layer1Msf-C2Msr-C3Msp is proportional. Wherein Msf is the magnetization of the free layer of the resistive switching device, Msr is the magnetization of the reference layer of the resistive switching device, Msp is the magnetization of the pinned layer of the resistive switching device, C1、C2And C3Is a constant.
In another specific embodiment of the present application, as shown in fig. 11, the resistive switching devices include a free layer, a reference layer, and a pinned layer, and before the step S4, the magnetization directions of the magnetic layers of each of the resistive switching devices are all the second magnetization direction,the resistance change devices are in the same resistance state, the second magnetization direction is opposite to the first magnetization direction, and the abnormal Hall resistors R and-C of the second conductive layer1Msf-C2Msr-C3Msp is proportional, and the step S4 includes: repeating the above steps S1 and S2 for several times until all the reference layers in the memory array are inverted, wherein the abnormal Hall resistances R and-C of the second conductive layer1Msf+C2Msr-C3Msp is proportional; repeating the steps S1 and S2 for several times until all the free layers of the memory array are turned over, wherein the abnormal Hall resistances R and C of the second conductive layer1Msf+C2Msr-C3Msp is proportional; repeating the above steps S1 and S2 for several times until all the pinned layers of the memory array are flipped, and the flipped pinned layers drive the reference layer to be flipped, during which the abnormal Hall resistances R and C of the second conductive layer1Msf-C2Msr+C3Msp is proportional; repeating the steps S1 and S2 for several times until all the reference layers of the memory array are inverted, wherein the abnormal Hall resistances R and C of the second conductive layer1Msf+C2Msr+C3Msp is proportional. Wherein Msf is the magnetization of the free layer of the resistive switching device, Msr is the magnetization of the reference layer of the resistive switching device, Msp is the magnetization of the pinned layer of the resistive switching device, C1、C2And C3Is a constant.
In an actual test process, the resistance change device comprises a plurality of magnetic layers, the corresponding overturning conditions are different, and the plurality of magnetic layers are tested to obtain a plurality of different first relational expressions, so that different distribution curves of overturning magnetic fields or overturning voltages are obtained.
In a specific embodiment of the present application, the resistive switching devices include a free layer, a reference layer, and a pinned layer, and before the step S1, magnetization directions of the free layers of any two of the resistive switching devices are the same, and magnetization directions of the reference layers of any two of the resistive switching devices are the same, and the step S3 includes: repeating the step S1 and the step S2 a plurality of times until all the free layers in the memory array are flipped, thereby obtaining the first relational expression. The mean value and the standard deviation of the switching magnetic field of the free layer and the switching current or the switching voltage of the resistive device may be obtained according to the first relational expression obtained in step S3, and the distribution curves of the switching magnetic field of the free layer and the switching current or the switching voltage of the resistive device may also be obtained.
In a specific embodiment of the present application, the resistive switching devices include a free layer, a reference layer, and a pinned layer, and before the step S1, the magnetization directions of the free layers of any two of the resistive switching devices are the same, and the magnetization directions of the reference layers of any two of the resistive switching devices are the same; the step S3 includes: repeating the steps S1 and S2 for a plurality of times until all the reference layers in the memory array are flipped; repeating the step S1 and the step S2 a plurality of times until all the free layers in the memory array are flipped, thereby obtaining the first relational expression. The mean value and the standard deviation of the switching magnetic fields of the free layer and the reference layer may be obtained from the first relational expression obtained in step S3, and the distribution curves of the switching magnetic fields of the free layer and the reference layer may also be obtained.
In a specific embodiment of the present application, the resistive switching devices include a free layer, a reference layer, and a pinned layer, and the magnetization direction of the magnetic layer of each of the resistive switching devices is a first magnetization direction before the step S1, and the step S3 includes: repeating the steps S1 and S2 for a plurality of times until all the reference layers in the memory array are flipped; repeating the steps S1 and S2 for a plurality of times until all the free layers of the memory array are flipped; repeating the above steps S1 and S2 for several times until all the pinned layers of the memory array are flipped, and the flipped pinned layers drive the reference layer to be flipped; repeating the step S1 and the step S2 for a plurality of times until all the reference layers of the memory array are inverted, thereby obtaining the first relational expression. The mean and standard deviation of the switching magnetic fields of the free layer, the reference layer, and the pinned layer may be obtained from the first relational expression obtained in the step S3, so that the distribution curves of the switching magnetic fields of the free layer, the reference layer, and the pinned layer may be obtained.
In order to obtain more test data and thus more accurately obtain the mean value and standard deviation of the switching magnetic field, the switching current or the switching voltage, in an embodiment of the present application, the last applied excitation signal in the step S3 is an end-point excitation signal, and the test method further includes: step S4, repeating the above steps S1 and S2 several times until at least one of the magnetic layers of the resistive switching device is inverted, so as to obtain a second relation, where the second relation is a relation between the test resistance and the excitation signal, and at least part of the obtained test resistances are different, and in the process of repeating the above steps, a difference between the excitation signal at the next time and the excitation signal at the previous time is a first difference, a difference between the excitation signal at the next time and the excitation signal at the previous time in the step S3 is a second difference, and one of the first difference and the second difference is greater than 0, and the other is less than 0, i.e. the positive and negative of the two are opposite. In step S4, the first time the step S1 is executed, the excitation signal is applied to the test structure as the end-point excitation signal.
In a specific embodiment of the present application, the resistive switching devices include a free layer, a reference layer, and a pinned layer, and before the step S4, the magnetization directions of the free layers of any two of the resistive switching devices are the same, the magnetization directions of the reference layers of any two of the resistive switching devices are the same, and the second magnetization direction is opposite to the first magnetization direction, and the step S4 includes: repeating the step S1 and the step S2 several times until all the free layers in the memory array are flipped, thereby obtaining the second relational expression. The mean value and the standard deviation of the switching magnetic field of the free layer and the switching current or the switching voltage of the resistive device may be obtained according to the second relational expression obtained in step S4, and the distribution curves of the switching magnetic field of the free layer and the switching current or the switching voltage of the resistive device may also be obtained.
In a specific embodiment of the present application, the resistive switching devices include a free layer, a reference layer, and a pinned layer, and before the step S4, the magnetization directions of the free layers of any two of the resistive switching devices are the same, the magnetization directions of the reference layers of any two of the resistive switching devices are the same, and the second magnetization direction is opposite to the first magnetization direction, and the step S4 includes: repeating the steps S1 and S2 for a plurality of times until all the reference layers in the memory array are flipped; repeating the step S1 and the step S2 several times until all the free layers in the memory array are flipped, thereby obtaining the second relational expression. The mean value and the standard deviation of the switching magnetic fields of the free layer and the reference layer may be obtained from the second relational expression obtained in step S4, and the distribution curves of the switching magnetic fields of the free layer and the reference layer may also be obtained.
In a specific embodiment of the present application, the resistive switching devices include a free layer, a reference layer, and a pinned layer, and before the step S4, the magnetization directions of the magnetic layers of the respective resistive switching devices are all a second magnetization direction, which is opposite to the first magnetization direction, and the step S4 includes: repeating the steps S1 and S2 for a plurality of times until all the reference layers in the memory array are flipped; repeating the steps S1 and S2 for a plurality of times until all the free layers of the memory array are flipped; repeating the above steps S1 and S2 for several times until all the pinned layers of the memory array are flipped, and the flipped pinned layers drive the reference layer to be flipped; repeating the step S1 and the step S2 for a plurality of times until all the reference layers of the memory array are inverted, thereby obtaining the second relational expression. The mean and standard deviation of the switching magnetic fields of the free layer, the reference layer, and the pinned layer may be obtained from the second relational expression obtained in the step S4, so that the distribution curves of the switching magnetic fields of the free layer, the reference layer, and the pinned layer may be obtained.
In one embodiment of the present application, in step S3, a difference between the previous excitation signal and the next excitation signal is a first predetermined difference, and in step S4, a difference between the previous excitation signal and the next excitation signal is a second predetermined difference, where the first predetermined difference is equal to the second predetermined difference. When the first predetermined difference is equal to the second predetermined difference, the variation amplitudes of the excitation signals in step S3 and step S4 are the same, that is, the signal values of each signal increase or decrease are the same, and the mean value and the standard deviation of the switching magnetic field of the magnetic layer and the switching current or the switching voltage of the resistive switching device are obtained according to the first relational expression and the second relational expression, so that the distribution curves of the switching magnetic field of the magnetic layer and the switching current or the switching voltage of the resistive switching device during the scanning of the positive and negative excitation signals are obtained.
In one embodiment of the present application, the step S5 includes: fitting the first relational expression to obtain at least one fitting formula; and obtaining the performance parameters according to the fitting formula. When the excitation signal is an excitation electric signal, the performance parameter includes a mean value and a standard deviation of an inversion electric signal of the memory array, the inversion electric signal includes an inversion voltage and an inversion current, and when the excitation signal is an excitation magnetic signal, the performance parameter includes a mean value and a standard deviation of an inversion magnetic field of the memory array. The person skilled in the art can select a suitable manner to fit the first relation according to actual conditions to obtain a suitable fitting formula.
It should be noted that, in the step S5, the first relational expression is decomposed for fitting, so that one first fitting formula may be obtained, or a plurality of fitting formulas may be obtained, where in the case of obtaining a plurality of fitting formulas, each fitting formula corresponds to the inversion condition of one magnetic layer.
The true coercive force Hc and the magnetic bias field Hoffset of the resistive switching device can be calculated according to the switching magnetic field, where Hc is (Hc1+ Hc2)/2, and Hoffset is (Hc1-Hc2)/2, where Hc1 and Hc2 are absolute values of the average switching field of a certain magnetic layer under positive and negative fields, respectively.
It should be noted that, the average high-low resistance state resistance difference deltaR, the average tunneling magnetoresistance TMR, and the effective average coupling fields Hex1 and Hex2 of the resistive switching device may be calculated according to the switching magnetic field, where deltaR ═ Rmax-Rmin/N, TMR ═ Rmax-Rmin)/Rmin, Hex1 ═ Hcr1+ Hcf1)/2, and Hex2 ═ Hcr2+ Hcf2)/2, where N is the number of series devices, and Hcr1, Hcr2, Hcf1, and Hcf2 are the absolute values of the average switching magnetic fields of the free layer and the reference layer under positive and negative fields, respectively.
In addition, if the memory array contains a failure device, the switching magnetic field or the switching voltage distribution curve cannot be influenced.
In a specific embodiment of the present application, fitting the first relation to obtain at least one fitting formula includes: obtaining a third relational expression by differentiating the first relational expression using the excitation signal as a variable, wherein the variable corresponding to the excitation signal is a current or a voltage when the excitation signal is an excitation electric signal, and the variable corresponding to the excitation signal is a magnetic field when the excitation signal is an excitation magnetic signal; and performing normal distribution fitting on the third relation formula to obtain the fitting formula.
Of course, the manner of fitting the first relation is not limited to the above fitting manner, and in another specific embodiment of the present application, the fitting of the first relation obtains at least one fitting formula, including: and fitting the cumulative probability distribution of the first relational expression to obtain the fitting formula.
Specifically, the fitting formula is a normal distribution cumulative probability distribution function or a sum of a plurality of normal distribution cumulative probability distribution functions. Of course, the fitting formula is not limited to the sum of the normal distribution cumulative probability distribution function and the plurality of normal distribution cumulative probability distribution functions, and those skilled in the art can select a suitable fitting manner according to actual situations, so as to obtain a suitable fitting formula.
In order to improve the accuracy of the average value and the standard deviation of the switching magnetic field of the magnetic layer and the switching current or the switching voltage of the resistive switching device obtained through the test, in an embodiment of the present application, the step S5 includes: fitting the first relational expression and the second relational expression to obtain a fitting formula; and acquiring the performance parameters according to the fitting formula, wherein the performance parameters comprise the mean value and the standard deviation of the switching magnetic field of the magnetic layer and the switching current or the switching voltage of the resistive switching device.
It should be noted that the process for preparing the test structure of the present application may be formed by any suitable semiconductor process, and those skilled in the art may select a suitable process according to actual conditions to form the test result of any of the above-mentioned applications.
In one embodiment of the present application, a method of forming a test structure includes: depositing a first metal layer on an insulating medium layer or an insulating substrate, wherein the first metal layer comprises a first conducting layer and a second conducting layer, then covering a photoresist for exposure, developing and etching to form a corresponding first conducting layer pattern and a second conducting layer pattern, then depositing an insulating medium and polishing by adopting a CMP (chemical mechanical polishing) process; depositing corresponding magnetic layers on the ground first metal layer in sequence, covering a light resistor, exposing, developing, etching the resistance change device to form a corresponding storage array, depositing an insulating layer medium, grinding by adopting a CMP (chemical mechanical polishing) process until the resistance change device is exposed, and isolating the resistance change devices by using the insulating layer medium; depositing a corresponding second metal layer on the ground resistive random access device, wherein the second metal layer comprises a first electrode pair and a second electrode pair, and exposing, developing and etching the second metal layer after covering the photoresist to form a corresponding first electrode pair pattern and a corresponding second electrode pair pattern; depositing an insulating layer medium, polishing by adopting a CMP (chemical mechanical polishing) process, covering a photoresist, exposing, developing and etching to form a conductive through hole, depositing a conductive through hole material, forming a first interconnection structure and a second interconnection structure, and polishing by adopting the CMP process to obtain a test structure. The deposition process may be a PVD process, a CVD process, or an ALD process, and one skilled in the art may select a suitable deposition process according to actual situations.
In another embodiment of the present application, the process for preparing the test structure of the present application comprises: depositing corresponding magnetic layers on the insulating medium layer or the insulating substrate, covering the photoresist, exposing, developing, and etching the resistive device to form a corresponding memory array; depositing a first metal layer, wherein the first metal layer comprises a first conducting layer and a second conducting layer, polishing by adopting a CMP (chemical mechanical polishing) process, then covering a photoresist, then carrying out exposure, developing and etching to form a corresponding first conducting layer pattern and a second conducting layer pattern, and then depositing an insulating layer medium and carrying out CMP polishing; and covering the photoresist, exposing, developing and etching to form a conductive through hole, depositing a conductive through hole material to form a first interconnection structure and a second interconnection structure, and performing CMP (chemical mechanical polishing) to obtain a test structure. The deposition process may be a PVD process, a CVD process, or an ALD process, and one skilled in the art may select a suitable deposition process according to actual situations.
In order to make the technical solutions of the present application more clearly understood by those skilled in the art, the technical solutions of the present application will be described below with reference to specific embodiments.
Example 1
The test structure of the embodiment comprises a memory array, a first conductive layer and a second conductive layer, wherein the memory array comprises a plurality of resistive devices, and each resistive device comprises at least one magnetic layer; the first conducting layer is arranged in contact with at least part of the resistance change device, the length extending direction of the first conducting layer is a first direction, and the first direction is vertical to the thickness direction of the resistance change device; the second conductive layer is electrically connected with the first conductive layer, the extending direction of the second conductive layer is a second direction, the second direction is perpendicular to the first direction, and the second direction is perpendicular to the thickness direction of the resistance change device.
The test method of the embodiment comprises the following steps:
step S0 of applying an initialization magnetic field of-8000 Oe to the space where the memory array is located, and initializing each of the resistive switching devices such that the magnetization directions of the free layers of any two of the resistive switching devices are the same and the magnetization directions of the reference layers of any two of the resistive switching devices are the same;
step S1, applying an excitation magnetic field in the space where the test structure is located;
step S2, applying a detection current to both ends of the first conductive layer; detecting a test voltage between two ends of the second conducting layer, and obtaining a test resistor according to the test voltage and the detection current;
step S3, repeating the above steps S1 and S2 several times until all the free layers in the memory array are turned over, the abnormal hall resistance of the second conductive layer is kept unchanged, then increased, and finally kept unchanged, so as to obtain the first relational expression, wherein the first relational expression is a relational expression between the test resistance and the excitation magnetic field, and at least part of the obtained test resistances are different, when the step S1 is repeated for the first time, the excitation magnetic field is-3000 Oe, and during each repetition, the excitation magnetic field at the next time is increased by 10Oe compared with the excitation magnetic field at the previous time, until the excitation magnetic field becomes 3000 Oe;
step S4, repeating the above steps S1 and S2 several times until all the free layers in the memory array are turned over, the abnormal hall resistance of the second conductive layer is kept unchanged, then decreased, and finally kept unchanged, so as to obtain the second relation, wherein the second relation is a relation between the test resistance and the excitation magnetic field, and at least part of the obtained test resistances are different, and in each repetition, the excitation magnetic field at the next time is decreased by 10Oe compared with the excitation magnetic field at the previous time until the excitation magnetic field becomes-3000 Oe;
step S5 is to obtain the mean value and the standard deviation of the switching magnetic field of the free layer according to the first relational expression and the second relational expression.
And performing data analysis on the test result, and acquiring a relation curve between the test resistance and the excitation magnetic field, namely an R-H curve according to the first relation and the second relation, as shown in fig. 12.
Example 2
The test structure of the embodiment comprises a memory array, a first conductive layer and a second conductive layer, wherein the memory array comprises a plurality of resistive devices, and each resistive device comprises at least one magnetic layer; the first conducting layer is arranged in contact with at least part of the resistance change device, the length extending direction of the first conducting layer is a first direction, and the first direction is vertical to the thickness direction of the resistance change device; the second conductive layer is electrically connected with the first conductive layer, the extending direction of the second conductive layer is a second direction, the second direction is perpendicular to the first direction, and the second direction is perpendicular to the thickness direction of the resistance change device.
The test method of the embodiment comprises the following steps:
step S0 of applying an initialization magnetic field of-8000 Oe to the space in which the memory array is located, and initializing each of the resistive switching devices such that the magnetization direction of each of the magnetic layers of each of the resistive switching devices is a first magnetization direction;
step S1, applying an excitation magnetic field in the space where the memory array is located;
step S2, applying a detection current to both ends of the first conductive layer, detecting a test voltage between both ends of the second conductive layer, and obtaining a test resistance according to the test voltage and the detection current;
step S3, repeating the above steps S1 and S2 several times until all the reference layers in the memory array are turned over, the abnormal hall resistance of the second conductive layer is kept unchanged first and then increased and finally kept unchanged, repeating the above steps S1 and S2 several times until all the free layers of the memory array are turned over, the abnormal hall resistance of the second conductive layer is increased and finally kept unchanged, repeating the above steps S1 and S2 several times until all the pinned layers of the memory array are turned over, the pinned layers are turned over to drive the reference layers to be turned over, the abnormal hall resistance of the second conductive layer is increased and finally kept unchanged, repeating the above steps S1 and S2 several times until all the reference layers of the memory array are turned over, the abnormal hall resistance of the second conductive layer is increased and finally kept unchanged, obtaining the first relational expression, wherein the first relational expression is a relational expression between the test resistance and the test magnetic field, and at least some of the obtained test resistances are different, and when step S1 is repeatedly executed for the first time, the test magnetic field is-8000 Oe, and the test magnetic field at the subsequent time is increased by 100Oe compared with the test magnetic field at the previous time until the test magnetic field becomes 8000Oe in each repetition;
step S4, repeating the above steps S1 and S2 for a plurality of times until all the reference layers in the memory array are inverted, the abnormal hall resistance of the second conductive layer is maintained unchanged and then decreased and finally maintained unchanged, repeating the above steps S1 and S2 for a plurality of times until at least a portion of the free layers in the memory array are inverted, the abnormal hall resistance of the second conductive layer is maintained unchanged and then decreased and finally maintained unchanged, repeating the above steps S1 and S2 for a plurality of times until all the pinned layers in the memory array are inverted, the abnormal hall resistance of the second conductive layer is maintained unchanged and then decreased and finally maintained unchanged, repeating the above steps S1 and S2 for a plurality of times until all the reference layers in the memory array are inverted, the abnormal hall resistance of the second conductive layer is maintained unchanged and then decreased and finally maintained, obtaining the second relational expression, which is a relational expression between the test resistance and the excitation magnetic field, and obtaining at least part of the test resistances different from each other, wherein the excitation magnetic field at the subsequent time is decreased by 100Oe from the excitation magnetic field at the previous time until the excitation magnetic field becomes-8000 Oe for each repetition;
step S5 is to obtain the mean value and the standard deviation of the switching magnetic field of the free layer, the reference layer, and the pinned layer according to the first relational expression and the second relational expression.
And performing data analysis on the test result, and acquiring a relation curve between the test resistance and the excitation magnetic field, namely an R-H curve according to the first relation and the second relation, as shown in fig. 13.
Example 3
As shown in fig. 5 and 6, the test structure of the present embodiment includes a memory array 10, a first conductive layer 20, a second conductive layer 30, a first electrode pair, a second electrode pair, a plurality of first interconnect structures, and a plurality of second interconnect structures, where the memory array 10 includes a plurality of resistive devices, and each resistive device includes at least one magnetic layer; the first conducting layer is arranged in contact with at least part of the resistance change device, the length extending direction of the first conducting layer is a first direction, and the first direction is vertical to the thickness direction of the resistance change device; the second conducting layer is electrically connected with the first conducting layer, the extending direction of the second conducting layer is a second direction, the second direction is perpendicular to the first direction, and the second direction is perpendicular to the thickness direction of the resistance change device; the first electrode pair comprises two first electrodes, and each first electrode is electrically connected with the first conductive layer; the second electrode pair comprises two second electrodes, and each second electrode is electrically connected with the second conducting layer respectively; the first interconnection structure is positioned between the first conductive layer and a first electrode, the first conductive layer is electrically connected with the first electrode through the first interconnection structure, the second interconnection structure is positioned between the second conductive layer and a second electrode, and the second conductive layer is electrically connected with the second electrode through the second interconnection structure.
In addition, the test method of this example is the same as that of example 2.
Example 4
The test structure of this example differs from example 3 in that:
both the first conductive layer and the second conductive layer are located on the second surface, as shown in fig. 7.
In addition, the test method of this example is the same as that of example 2.
Example 5
The test structure of this example differs from example 3 in that:
the resistive device is disposed in the first conductive layer and the resistive device is disposed in the second conductive layer, as shown in fig. 8.
In addition, the test method of this example is the same as that of example 2.
Example 6
The test structure of this example differs from example 3 in that:
there are two first conductive layers and two second conductive layers, one first conductive layer and one second conductive layer being on the first surface, and the other first conductive layer and the other second conductive layer being on the second surface, as shown in fig. 9.
In addition, the test method of this example is the same as that of example 2.
Example 7
The test structure of this example differs from example 3 in that:
as shown in fig. 14, the first conductive layer and the second conductive layer provide lines for spin orbit torque, i.e., the memory array is an SOT-MRAM.
The test method of the embodiment comprises the following steps:
step S0 of applying an initialization magnetic field of-8000 Oe to the space where the memory array is located, and initializing each of the resistive switching devices such that the magnetization direction of each of the magnetic layers of each of the resistive switching devices is a first magnetization direction;
step S1, applying an excitation magnetic field in the space where the test structure is located;
step S2, applying a detection current to both ends of the first conductive layer, detecting a test voltage between both ends of the second conductive layer, and obtaining a test resistance according to the detection current and the test voltage;
step S3, repeating the above steps S1 and S2 several times until all the reference layers in the memory array are turned over, the abnormal hall resistance of the second conductive layer is maintained unchanged, then increased and finally maintained unchanged, repeating the above steps S1 and S2 several times until all the free layers of the memory array are turned over, the abnormal hall resistance of the second conductive layer is maintained unchanged, then increased and finally maintained unchanged, repeating the above steps S1 and S2 several times until all the pinned layers of the memory array are turned over, the pinned layers are turned over to drive the reference layers to be turned over, the abnormal hall resistance of the second conductive layer is maintained unchanged, then increased and finally maintained, repeating the above steps S1 and S2 several times until all the reference layers of the memory array are turned over, the abnormal hall resistance of the second conductive layer is first kept unchanged, then increased, and finally kept unchanged to obtain the first relational expression, the first relational expression is a relational expression between the test resistance and the excitation magnetic field, and at least part of the obtained test resistances are different, when the step S1 is repeatedly executed for the first time, the excitation magnetic field is-8000 Oe, and in each repetition, the excitation magnetic field at the next time is increased by 100Oe compared with the excitation magnetic field at the previous time until the excitation magnetic field becomes 8000 Oe;
step S4, repeating the above steps S1 and S2 several times until all the reference layers in the memory array are turned over, the abnormal hall resistance of the second conductive layer is kept unchanged and then reduced and finally kept unchanged, repeating the above steps S1 and S2 several times until at least part of the free layers in the memory array are turned over, the abnormal hall resistance of the second conductive layer is kept unchanged and then reduced and finally kept unchanged, repeating the above steps S1 and S2 several times until all the pinned layers in the memory array are turned over, the pinned layers are turned over to drive the reference layers to be turned over, the abnormal hall resistance of the second conductive layer is kept unchanged and then reduced and finally kept unchanged, repeating the above steps S1 and S2 several times, until all the reference layers in the memory array are turned over, the abnormal hall resistance of the second conductive layer is firstly kept unchanged, then reduced and finally kept unchanged to obtain a second relational expression, wherein the second relational expression is a relational expression between the test resistance and the excitation magnetic field, and at least part of the obtained excitation resistances are different, and in each repeating process, the excitation magnetic field at the next time is increased and reduced by 100Oe compared with the excitation magnetic field at the previous time until the excitation magnetic field becomes-8000 Oe;
step S5 is to obtain the mean value and the standard deviation of the switching magnetic field of the free layer, the reference layer, and the pinned layer according to the first relational expression and the second relational expression.
Example 8
The test structure of this example differs from example 3 in that:
as shown in fig. 14, the first conductive layer and the second conductive layer provide lines for spin orbit torque, i.e., the memory array is an SOT-MRAM.
The test method of the embodiment comprises the following steps:
step S0 of applying an initialization voltage to both ends of the first conductive layer to initialize each of the resistance change devices so that the magnetization directions of the free layers of any two of the resistance change devices are the same and the magnetization directions of the reference layers of any two of the resistance change devices are the same;
step S1, applying an excitation voltage to both ends of the first conductive layer;
step S2, applying a detection current to both ends of the first conductive layer, detecting a test voltage between both ends of the second conductive layer, and obtaining a test resistance according to the detection current and the test voltage;
step S3, repeating the above steps S1 and S2 several times until all the free layers in the memory array are turned over, the abnormal hall resistance of the second conductive layer is kept unchanged, then increased, and finally kept unchanged, so as to obtain the first relational expression, wherein the first relational expression is a relational expression between the test resistance and the excitation voltage, and at least part of the obtained test resistances are different, when the step S1 is repeated for the first time, the excitation voltage is-1V, and during each repetition, the excitation voltage at the next time is increased by 0.01V compared with the excitation voltage at the previous time until the excitation voltage becomes 1V;
step S4, repeating the above steps S1 and S2 several times until all the free layers in all the memory arrays are turned over, the abnormal hall resistance of the second conductive layer is kept unchanged, then decreased, and finally kept unchanged, so as to obtain the second relational expression, wherein the second relational expression is a relational expression between the test resistance and the excitation voltage, and at least part of the obtained test resistances are different, when the step S1 is repeated for the first time, the excitation voltage is 1V, and during each repetition, the excitation voltage at the next time is decreased by 0.01V compared with the excitation voltage at the previous time, until the excitation voltage becomes-1V;
step S5, obtaining the mean value and the standard deviation of the reversed voltage according to the first relational expression and the second relational expression.
In the testing process, fig. 15 is a schematic diagram of the pulse excitation voltage V applied to the two ends of the first conductive layer in step S1 and the time T, fig. 16 is a schematic diagram of the detection current I and the time T in step S2, fig. 17(a) is a graph of the relationship between the test resistance and the test voltage in step S3, and fig. 17(b) is a graph of the relationship between the test resistance and the test voltage in step S4.
From the above description, it can be seen that the above-described embodiments of the present application achieve the following technical effects:
1) in the test structure, a first conducting layer is in contact with at least part of resistive devices, a second conducting layer is electrically connected with the first conducting layer, after an excitation signal is applied to the test structure in the test process, detection current is applied to two ends of the first conducting layer, test voltage between two ends of the second conducting layer is detected according to an abnormal Hall effect, then a test resistor can be obtained according to the test voltage and the detection current, the excitation signal is applied to the test structure for multiple times, the test resistor is obtained through testing, the excitation signal of the next time is greater than or less than the excitation signal of the previous time until at least one magnetic layer of the memory array is overturned, and a relational expression of the test resistor and the excitation signal is obtained, so that the mean value and the standard deviation of the overturning magnetic field, the overturning current or the overturning voltage of the memory array are obtained. The test structure tests the memory array comprising the plurality of resistive devices, avoids testing the plurality of resistive devices one by one, greatly shortens the test time, and solves the problem that the time required for obtaining the distribution curve of the switching magnetic field, the switching current or the switching voltage is long in the prior art.
2) In the test method, after an excitation signal is applied to a test structure, detection current is applied to two ends of a first conducting layer, test voltage between two ends of a second conducting layer is detected according to an abnormal Hall effect, then a test resistor can be obtained according to the test voltage and the detection current, the excitation signal is applied to the test structure for multiple times, the test resistor is obtained through testing, the excitation signal of the next time is larger than or smaller than the excitation signal of the previous time until at least one magnetic layer of the memory array is turned over, a relational expression of the test resistor and the excitation signal is obtained, and therefore the mean value and the standard deviation of the turning magnetic field, the turning current or the turning voltage of the memory array are obtained. The testing method tests the memory array comprising the plurality of resistive devices, avoids testing the plurality of resistive devices one by one, greatly shortens the testing time, and solves the problem that the time required for obtaining the distribution curve of the switching magnetic field, the switching current or the switching voltage is long in the prior art.
The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims (19)

1. A test structure for testing a memory array including a plurality of resistive switching devices, comprising:
the memory array comprises a plurality of resistive switching devices, wherein each resistive switching device comprises at least one magnetic layer;
the first conducting layer is arranged in contact with at least part of the resistance change device, the length extending direction of the first conducting layer is a first direction, and the first direction is perpendicular to the thickness direction of the resistance change device;
the second conducting layer is electrically connected with the first conducting layer, the extending direction of the second conducting layer is a second direction, the second direction is perpendicular to the first direction, and the second direction is perpendicular to the thickness direction of the resistive switching device.
2. The test structure of claim 1, further comprising:
a first electrode pair comprising two first electrodes, each of the first electrodes being electrically connected to the first conductive layer, respectively;
and the second electrode pair comprises two second electrodes, and each second electrode is electrically connected with the second conductive layer respectively.
3. The test structure of claim 2, further comprising a plurality of interconnect structures, the plurality of interconnect structures comprising a plurality of first interconnect structures and a plurality of second interconnect structures, wherein one of the first interconnect structures is located between the first conductive layer and one of the first electrodes, the first conductive layer is electrically connected to one of the first electrodes through the first interconnect structures, one of the second interconnect structures is located between the second conductive layer and one of the second electrodes, and the second conductive layer is electrically connected to one of the second electrodes through the second interconnect structures.
4. The test structure of claim 3, wherein at least some of the interconnect structures comprise conductive vias and interconnect metal layers disposed and connected in a direction away from the memory array, the interconnect metal layers being connected to the first electrodes or the second electrodes.
5. The test structure of claim 3, further comprising:
and the storage array, the first conducting layer, the second conducting layer and the interconnection structure are all positioned in the insulating medium layer.
6. The test structure according to any one of claims 1 to 5, wherein each of the resistive switching devices includes a bottom electrode, a memory portion, and a top electrode, which are stacked in this order, and the first conductive layer and the second conductive layer are both located on a first surface, or the first conductive layer and the second conductive layer are both located on a second surface, the first surface being a surface of the bottom electrode which is away from the memory portion, and the second surface being a surface of the top electrode which is away from the memory portion.
7. The test structure according to any one of claims 1 to 5, wherein at least part of the resistive switching device is disposed within the first conductive layer and at least part of the resistive switching device is disposed within the second conductive layer.
8. The test structure of any of claims 1 to 5, wherein there are two of the first conductive layers and two of the second conductive layers, one of the first conductive layers and one of the second conductive layers being located on a first surface, and the other of the first conductive layers and the other of the second conductive layers being located on a second surface.
9. The test structure of any one of claims 1 to 5, wherein the material of the first and second conductive layers is selected from at least one of Pt, Ta, W, Ir, Hf, Ru, Tl, Bi, Au and Os, respectively.
10. The test structure of any of claims 1 to 5, wherein the material of the first and second conductive layers is selected from at least one of Ta, TaN, TiN, Pt, Ta, W, Ir, Hf, Ru, Tl, Bi, Au and Os, respectively.
11. A method of testing a test structure according to any of claims 1 to 10, characterized in that the method of testing comprises:
step S1, applying an excitation signal to the test structure, wherein the excitation signal is an excitation electrical signal or an excitation magnetic signal, the excitation electrical signal is applied to two ends of the first conductive layer, and the excitation magnetic signal is applied to a space where the test structure is located;
step S2, applying detection current at two ends of the first conducting layer, detecting test voltage between two ends of the second conducting layer, and obtaining test resistance according to the detection current and the test voltage;
step S3, repeating the step S1 and the step S2 in sequence for a plurality of times until at least one magnetic layer of the resistive switching device is turned over, so as to obtain a first relational expression, where the first relational expression is a relational expression between the test resistance and the excitation signal, and at least a part of the obtained test resistances are different, and in each repetition, the excitation signal at the next time is greater than or less than the excitation signal at the previous time, and the excitation signal changes monotonically;
step S5, obtaining performance parameters of the resistive switching device at least according to the first relational expression, where the performance parameters include a mean value and a standard deviation of an inversion electrical signal of the memory array when the excitation signal is an excitation electrical signal, the inversion electrical signal includes an inversion voltage and an inversion current, and the performance parameters include a mean value and a standard deviation of an inversion magnetic field of the memory array when the excitation signal is an excitation magnetic signal.
12. The testing method of claim 11, wherein prior to the step S1, the testing method further comprises:
and initializing each resistance change device to enable each resistance change device to be in the same resistance state.
13. The testing method according to claim 12, wherein initializing each resistive switching device comprises at least one of: applying an initialization voltage to two ends of the memory array, applying an initialization current to two ends of the memory array, and applying an initialization magnetic field in a space where the memory array is located.
14. The testing method according to claim 11, wherein in the step S3, the excitation signal applied last time is an end-point excitation signal, and the testing method further comprises:
step S4, repeating the step S1 and the step S2 several times in sequence until at least one of the magnetic layers of the resistive switching device is flipped to obtain a second relation, where the second relation is a relation between the test resistance and the excitation signal, and at least a portion of the obtained test resistances are different, in the process of repeating the steps several times, a difference between the excitation signal at the next time and the excitation signal at the previous time is a first difference, a difference between the excitation signal at the next time and the excitation signal at the previous time in the step S3 is a second difference, one of the first difference and the second difference is greater than 0, and the other is less than 0.
15. The test method according to claim 14, wherein in the step S3, the difference between the excitation signal of the next time and the excitation signal of the previous time is a first predetermined difference, and in the step S4, the difference between the excitation signal of the next time and the excitation signal of the previous time is a second predetermined difference, and the first predetermined difference is equal to the second predetermined difference.
16. The test method according to any one of claims 11 to 15, wherein the step S5 includes:
fitting the first relational expression to obtain at least one fitting formula;
and acquiring the performance parameters according to the fitting formula.
17. The test method of claim 16, wherein fitting the first relationship to obtain at least one fitting equation comprises:
taking a differential of the variable corresponding to the excitation signal on the first relational expression to obtain a third relational expression, wherein the variable corresponding to the excitation signal is current or voltage under the condition that the excitation signal is an excitation electric signal, and the variable corresponding to the excitation signal is a magnetic field under the condition that the excitation signal is an excitation magnetic signal;
and performing normal distribution fitting on the third relational expression to obtain the fitting formula.
18. The test method of claim 16, wherein fitting the first relationship to obtain at least one fitting equation comprises:
and fitting the cumulative probability distribution of the first relational expression to obtain the fitting formula.
19. The testing method according to claim 14, wherein the step S5 includes:
fitting the first relational expression and the second relational expression according to a fitting function to obtain a fitting formula;
and acquiring the performance parameters according to the fitting formula.
CN201910819101.4A 2019-08-30 2019-08-30 Test structure and test method Active CN112447257B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201910819101.4A CN112447257B (en) 2019-08-30 2019-08-30 Test structure and test method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201910819101.4A CN112447257B (en) 2019-08-30 2019-08-30 Test structure and test method

Publications (2)

Publication Number Publication Date
CN112447257A true CN112447257A (en) 2021-03-05
CN112447257B CN112447257B (en) 2022-10-14

Family

ID=74735299

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201910819101.4A Active CN112447257B (en) 2019-08-30 2019-08-30 Test structure and test method

Country Status (1)

Country Link
CN (1) CN112447257B (en)

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020167838A1 (en) * 2001-05-14 2002-11-14 Perner Frederick A. Resistive cross point memory with on-chip sense amplifier calibration method and apparatus
US20040165453A1 (en) * 2003-02-26 2004-08-26 Kentaro Nakajima MRAM having SAL layer
KR20110021405A (en) * 2009-08-26 2011-03-04 삼성전자주식회사 Resistive random access memory
US20120326712A1 (en) * 2011-06-21 2012-12-27 Ioan Tudosa Method and apparatus for measuring magnetic parameters of magnetic thin film structures
US20170170081A1 (en) * 2015-12-14 2017-06-15 Samsung Electronics Co., Ltd. Test architecture of semiconductor device, test system, and method of testing semicondurctor devices at wafer level
CN109087995A (en) * 2017-06-14 2018-12-25 中电海康集团有限公司 Perpendicular magnetization MTJ device and STT-MRAM
CN110021335A (en) * 2018-01-09 2019-07-16 中电海康集团有限公司 The acquisition methods and device of the data retention over time of magnetic tunnel junction

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020167838A1 (en) * 2001-05-14 2002-11-14 Perner Frederick A. Resistive cross point memory with on-chip sense amplifier calibration method and apparatus
US20040165453A1 (en) * 2003-02-26 2004-08-26 Kentaro Nakajima MRAM having SAL layer
KR20110021405A (en) * 2009-08-26 2011-03-04 삼성전자주식회사 Resistive random access memory
US20120326712A1 (en) * 2011-06-21 2012-12-27 Ioan Tudosa Method and apparatus for measuring magnetic parameters of magnetic thin film structures
US20170170081A1 (en) * 2015-12-14 2017-06-15 Samsung Electronics Co., Ltd. Test architecture of semiconductor device, test system, and method of testing semicondurctor devices at wafer level
CN109087995A (en) * 2017-06-14 2018-12-25 中电海康集团有限公司 Perpendicular magnetization MTJ device and STT-MRAM
CN110021335A (en) * 2018-01-09 2019-07-16 中电海康集团有限公司 The acquisition methods and device of the data retention over time of magnetic tunnel junction

Also Published As

Publication number Publication date
CN112447257B (en) 2022-10-14

Similar Documents

Publication Publication Date Title
US10276783B2 (en) Gate voltage controlled perpendicular spin orbit torque MRAM memory cell
US6909631B2 (en) MRAM and methods for reading the MRAM
US8750031B2 (en) Test structures, methods of manufacturing thereof, test methods, and MRAM arrays
KR100558480B1 (en) Magnetic tunnel junction structures and methods of fabrication
RU2469441C2 (en) Memory cell and method of forming magnetic tunnel junction (mtj) of memory cell
EP1248273A2 (en) Cladded read conductor for a tunnel junction memory cell
JP2007300078A (en) Magnetic memory element
US9252187B2 (en) Devices and methods for measurement of magnetic characteristics of MRAM wafers using magnetoresistive test strips
US11488647B2 (en) Stacked magnetoresistive structures and methods therefor
US7800941B2 (en) Magnetic memory with magnetic tunnel junction cell sets
JP2003007982A (en) Magnetic storage device and method of designing the same
Wu et al. Pinhole defect characterization and fault modeling for STT-MRAM testing
Hosotani et al. Effect of self-heating on time-dependent dielectric breakdown in ultrathin MgO magnetic tunnel junctions for spin torque transfer switching magnetic random access memory
US10971245B1 (en) Measurement of MTJ in a compact memory array
US7169622B2 (en) Magnetoresistive random access memory devices and methods for fabricating the same
Abraham et al. Rapid-turnaround characterization methods for MRAM development
CN112447257B (en) Test structure and test method
US7619409B2 (en) Methods and apparatus for electrically characterizing magnetic tunnel junctions having three metal layers separated by two dielectric layers
US20200365653A1 (en) SOT MRAM Having Dielectric Interfacial Layer and Method Forming Same
US6552554B1 (en) Testing current perpendicular to plane giant magnetoresistance multilayer devices
US6787372B1 (en) Method for manufacturing MTJ cell of magnetic random access memory
Sitaram et al. A 0.18/spl mu/m logic-based MRAM technology for high performance nonvolatile memory applications
US10607902B2 (en) Method for measuring proximity effect on high density magnetic tunnel junction devices in a magnetic random access memory device
RU2532589C2 (en) Cmos/soi mram memory integrated with vlsi and method for production thereof (versions)
Van Beek et al. Voltage acceleration and pulse dependence of barrier breakdown in MgO based magnetic tunnel junctions

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant