RU2532589C2 - Cmos/soi mram memory integrated with vlsi and method for production thereof (versions) - Google Patents

Abstract

FIELD: physics, computer engineering.

SUBSTANCE: invention relates to computer engineering, particularly MRAM cell array circuits which employ spin-transfer torque magnetoresistive random-access memory technology. A method of making CMOS/SOI MRAM integrated into a basic processing route in order to form an initial planar VLSI heterostructure of CMOS/SOI technology with STI insulation, used as a substrate, and subsequently forming thereon an MRAM array, includes successively forming in Si device layer of a SOI heterostructure regions of n- and p-pockets, STI insulation, n⁺- and p⁺-polysilicon gates for n- and p-channel transistors, respectively, regions of high-ohmic drains and sources of MOS transistors, p⁺-drains which run to the bottom of the device layer, as well as layers of self-aligned titanium silicide and a multilayer metal coating, then on the formed VLSI structure, after the third metal coating layer, forming an MRAM array, which includes a freely re-magnetising ferromagnetic layer (SS), a fixed magnetisation ferromagnetic layer (FS) and a tunnel insulation layer (IS) between the SS and the FS, and then forming a fourth level of metal coating and a protective dielectric layer.

EFFECT: integrating the technology of forming an MRAM array with improved magnetic hysteresis of magnetic elements into a CMOS/SOI VLSI structure.

36 cl, 56 dwg

Description

The present invention relates to the field of computing, in particular to schemes of matrixes of memory cells “MRAM” (“Magnetic Random Access Memory”) using the technology of magnetoresistive random access memory with spin rotation transmission, the so-called spin-valve storage devices, “STT-MRAM” also known as “RAM” (“Random Access Memory”) with spin torque transmission (“Spin Transfer Torque RAM”, “STT-RAM”), “RAM” with magnetization switching and spin torque transmission (“Spin Torque Transfer” Magnetization Switching RAM ”, or“ Spin-RAM ”),“ RAM ”from the front whose spin moment ("SMT-RAM").

To use ferromagnetic particles for storing information, including as the main element of memory, it is necessary that in the particle (single-layer) only one state is possible, uniformly magnetized, and that the particle has an anisotropy axis - the distinguished direction along which the magnetization vector will be directed particles. (This is precisely what makes it possible to ascribe to two possible states (magnetization along or against the anisotropy axis) the logical values “0” and “1”.)

The invention is known / 1 /, in which the registration layer and the fixation layers are formed from, for example, Fe, Co, Ni or their alloys, magnetite with a large spin polarization, oxides of the type CrO ₂ or RXMnO ₃ - у (R: rare earths, X : Ca, Ba or Sr, у is the spin state) or of the Heusler alloy of the NiMnSb or PtMnSb type. These magnetic substances may contain a small amount of a non-magnetic element such as Ag, Cu, Au, Al, Mg, Si, Bi, Ta, B, C, O, N, Pd, Pt, Zr, Ir, W, Mo or Nb, if they Do not lose ferromagnetism. The tunnel barrier layer is formed from one of various dielectrics, for example Al ₂ O ₃ , SiO ₂ , MgO, AlN, Bi ₂ O ₃ , MgF ₂ , CaF ₂ , SrTiO ₂ and AlLaO ₃ . The upper ferromagnetic layer and the lower ferromagnetic layer are formed of, for example, Fe, Co, Ni or their alloys, magnetites having a large spin polarization, oxides of the type CrO ₂ or RXMnO ₃ - у (R: rare-earth, X: Ca, Ba or Sr) or Heusler alloy type NiMnSb or PtMnSb. Non-magnetic layers are formed from one of various dielectrics, for example Al ₂ O ₃ , SiO ₂ , MgO, AlN, Bi ₂ O ₃ , MgF ₂ , CaF ₂ , SrTiO ₂ and AlLaO ₂ . The antiferromagnetic layer is formed from, for example, Fe-Mn, Pt-Mn, Pt-Cr-Mn, Ni-Mn, Ir-Mn, NiO or Fe ₂ O ₃ . The first and second pairs of ferromagnetic layers are formed from, for example, NiFe, CoFe, amorphous CoZrNb, FeN _X, or FeAlSi. EFFECT: invention makes it possible to provide a random access magnetic memory capable of reducing current, and to provide a method for recording data.

The disadvantage of this invention is the need to create an antiferromagnetic layer for fixing one of the magnetic layers, which makes the process more cumbersome and expensive.

The invention is known / 2 /, which includes the formation of a magnetic tunnel junction having a freely magnetizable layer, a layer with a fixed magnetization and a tunnel insulating layer located between a freely magnetizable layer and a layer with a fixed magnetization; the formation of a conductive solid mask lying over the first region of the magnetic transition, while the freely magnetizable layer in the second region is unprotected; a freely remagnetizable layer is electrically and magnetically inactive in the second region; the formation of a conductive line that binds into a solid mask, the specified solid mask is not electrically connected by a magnetic transition "MTJ" to the conductive line. The tunnel barrier layer is formed by depositing a thin dielectric layer on an attached layer. Typically, the tunnel barrier layer is formed from Al ₂ O ₃ type alumina having a thickness of about 1 nm. Materials available for use as a tunnel barrier layer include magnesium oxides, silicon oxides, silicon nitrides, and silicon carbides; oxides, nitrides and carbides of other elements or combinations of elements and other materials by incorporation or formation of semiconductor materials. A freely remagnetizable layer is formed by depositing a NiFe layer having a thickness of about 5 nm onto the tunnel insulating layer. Thereafter, a conductive barrier layer of tantalum nitride (TaN) having a thickness of approximately 5 nm is formed by deposition. This TaN layer serves to protect the NiFe layer during subsequent processing and to provide adhesion to one or more subsequently formed layers.

Alternatively, NiCoFe, amorphous CoFeB, and similar ferromagnets can be used instead of NiFe as the ferromagnetic part of the free layer. In an alternative embodiment, the free layer may be formed from more than one such ferromagnetic layer to improve performance or production capabilities. Multiple layers can be separated by non-magnetic layers like TaN or Ru. These layers are typically in the thickness range of 2 to 10 nm.

The disadvantage of this invention is the multilayer structure, which increases the risk of loss of electron spin during the tunneling process and the transition through the interface between the layers and, therefore, leads to the deterioration of the most important parameter.

The closest technical solution, selected as a prototype, is a method of forming structures of magnetic tunnel junctions for magnetoresistive magnetic random access memory / 3 /. This method includes the formation of a magnetic tunnel junction (“MTJ”) on a substrate having a freely magnetizable layer, a fixed magnetization layer and a tunnel insulating layer located between the freely magnetizable layer and a fixed magnetization layer, in which, to form a magnetic tunnel transition to the substrate, a vacuum layer of iron is precipitated at room temperature, then a silicon layer is deposited on a surface of an iron layer in vacuum at room temperature, then acidification surface deposited silicon in a glow discharge plasma at room temperature, thereafter forming a silicide layer of the ferromagnetic layer of silicon oxide by solid state reaction at a temperature of 400-800 ° C, then a magnetization fixed layer is formed on the tunnel insulating layer.

Despite the fact that this technical solution allows the formation of a ferromagnetic electrode made in the form of a free magnetizable layer in contact with a tunnel barrier with a high smoothness characteristic, it eliminates the presence of a paramagnetic phase while simplifying the method of obtaining magnetic tunnel junctions, and makes it easy to integrate into an existing (silicon) manufacturing technology of memory elements; it does not solve the problem of integrating the “MRAM” matrix into the VLSI structure of the basic manufacturing technology of CMOS / KND.

The technical result of the proposed technical solution is the integration of the technology of forming a matrix of memory "MRAM" with improved magnetic hysteresis of magnetic elements in the structure of the VLSI technology "complementary-metal-oxide-semiconductor / silicon-on-insulator" (CMOS / SOI).

The technical result is achieved by the fact that in the method of manufacturing a built-in CMOS / SOI memory “MRAM” embedded in the basic technological route in order to form the initial planar heterostructure VLSI CMOS / SOI technology with “STI” insulation used as a substrate, and subsequent formation of a memory matrix on it «MRAM», successively formed in the instrument Si layer of the SOI heterostructure field n- and p-pockets insulation «STI», n ⁺ - and p ⁺ -polikremnievye closures for n- and p-channel transistors, respectively, the areas of high impedance source and drain a PMOS transistor, p ⁺ -Stock reaching to the bottom layer of the instrument, as well as self-aligned titanium silicide layers and reliable system of multilevel metallization, then on VLSI after the third metallization layer structure formed on a planar technology and form a matrix memory «MRAM», comprising a freely remagnetizing a ferromagnetic layer ("SS"), a ferromagnetic layer with a fixed magnetization ("FS") and a tunnel insulating layer ("IS") located between "SS" and "FS", then form the fourth level of metallization and aschitny dielectric layer.

In order to form the VLSI structure of CMOS / SOI technology with small-grooved silicon oxide (“STI”) insulation, a silicon-on-insulator (SOI) plate with a p ^- type device layer thickness of about 200 is used as the initial structure for it nm, the buried oxide thickness of about 200-400 nm and the substrate orientation is (100).

To form the active transistor structures of the VLSI MOSFET, buffer oxide is grown on the SOI plate and a layer of Si ₃ N _{4 is} deposited, after which “Active Regions” photolithography is performed and the sides of the islands are acidified.

To form “STI” insulation in the VLSI structure, a SiO ₂ layer is deposited by plasma chemical vapor deposition (“HDP”), compaction (annealing) is performed, then “Inversion of active regions” photolithography is performed to create “STI” insulation, chemical-mechanical polishing is performed (CMP), then etching of Si ₃ N ₄ in hot phosphoric acid and etching of SiO ₂ are carried out, followed by an oxidation process to form a buffer oxide.

To form an n-pocket in the VLSI structure, an “n-pocket” photocopying operation and ion doping with phosphorus are performed, and then the photoresist is removed.

To form a p-pocket, the p-pocket photocopying operation is performed and ion doping with boron is performed, followed by plasmochemical removal of the photoresist.

To form polysilicon gates of transistors in the VLSI structure, their formation is realized by removing buffer oxide, growing a gate oxide and depositing undoped Si, followed by the Shutters photolithography operation.

To form high-resistance n ^- sinks using ion-beam doping (“LDD”) in the VLSI structure, “n ^- stocks” are photocopied and ion doped with phosphorus and arsenic.

For the formation of high-resistance p ^- sinks using "LDD" in the VLSI structure, photocopying of the "p ^- stocks" and ion doping operation using compound BF _{2 are} performed.

To form interconnects (spacers) in the VLSI structure, a layer of "silicon hydride - silicon dioxide"("Silane-SiO ₂ ") is deposited by chemical vapor deposition technology ("LPTEOS") and then reactive-ion etching of the "Silane- SiO ₂ + SiO ₂ ".

To form n ⁺ -stocks in the VLSI structure, oxidation is carried out with the subsequent implementation of photocopying of "n ⁺ -stocks" and ion doping is carried out with As ⁺ ions.

To form p ⁺ -stocks in the VLSI structure, photocopy the “p ⁺ -stocks” and perform ion doping with boron, which leads to doping of the gate of the p-channel transistor (p ⁺ polysilicon gate), then using the technology of chemical vapor deposition form a layer of "LPTEOS-SiO ₂ ", then conduct annealing and perform fast annealing, which stimulates the diffusion of effluents.

To form high-resistance resistances in the VLSI structure, photolithography is performed to protect the region of these resistances and then react-ion etching of the SiO ₂ layer is carried out.

To form a titanium silicide layer in the VLSI structure, Ti deposition and TiN deposition are performed and a two-stage heat treatment is used to obtain TiSi ₂ compound.

To form contacts in the VLSI structure, borophosphor glass (BPTEOS-SiO ₂ ) is deposited, its melted is “SATEOS-SiO ₂ ” followed by a chemical-mechanical polishing procedure, then contacts are formed, for which the “Contacts” photocopying operation is performed, then perform the process of thermal suppression and carry out reactive-ion etching of the SiO ₂ layer, then perform the process of spraying the Ti / TiN barrier layers, carry out the deposition of tungsten (W), and then carry out chemical-mechanical polishing of the W / TiN / Ti structure to SiO ₂ .

To form the first metallization level in the VLSI structure, MET1 photocopying and the TiN / Ti / Al / Ti reactive-ion etching process are performed, then a thick inter-level PECVD-SiO ₂ dielectric is deposited, SATEOS-SiO _{2 is} fused and conduct chemical-mechanical polishing of the layer "PECVD-SiO ₂ ".

To form a “VIA-1” layer with metallization in the VLSI structure, “VIA-1” photocopying is performed, reactive-ion etching of SiO _{2 is} performed over the entire thickness of the layer, then the Ti / TiN deposition process and W deposition and chemical-mechanical polishing are performed layer W / TiN / Ti to SiO ₂ .

To form the second metallization level “MET2” in the VLSI structure, Ti / Al / Ti / TiN is deposited, photocopying “MET2” is performed, and TiN / Ti / Al / Ti is reactively ion etched, then a thick PECVD-SiO thick interlevel dielectric is deposited ₂ ", melt it with" SATEOS-SiO ₂ "and carry out chemical-mechanical polishing with" PECVD-SiO ₂ ".

To form a VIA-2 layer with metallization in the VLSI structure, VIA-2 is photocopied, SiO ₂ is rectively ion etched over the entire thickness of the layer, then Ti / TiN is deposited, W is deposited, and chemical-mechanical polishing is performed W / TiN / Ti to SiO ₂ .

To form the third metallization level in the VLSI structure, processes similar to those for the formation of the second metallization level are performed.

To form a binder with metallization of the VIA-3 layer in the VLSI structure, processes similar to those for forming the VIA-2 binder layer are performed.

In order to reduce the temperature effect on the subsequent MRAM memory formation process, this process is implemented between the third and fourth metallization levels of the LSI structure of CMOS / SOI technology at low temperatures.

According to the first embodiment, between the third and fourth metallization levels, the LSI structures form the STT-MRAM memory matrix with the corresponding structure.

According to the second option, between the third and fourth metallization levels, the LSI structures form a “MRAM” memory matrix with Savchenko architecture with the corresponding structure.

According to the first option, the STT-MRAM memory built into the VLSI CMOS / SOI technology includes a base electrode, a fixed magnetization ferromagnetic layer (“FS”) made of a film ferromagnetic structure, a tunnel insulating layer (“IC”) located on it, made of TaO _x, disposed on top of the "IP" remagnetizing free ferromagnetic layer ( "MOP"), made of a ferromagnetic structure, double-layered ferromagnetic structure is provided on top with a conductive layer Au with access to the surface for contact with control read / write buses, and the whole two-layer structure of ferromagnetic _{Au / Ta / Co / TaO x} / Co / Au is placed in a matrix of dielectric Ta ₂ O _5. The structure of the “STT-MRAM” matrix is formed on the surface of the third metallization layer “MET3” of the SOI with an additional Au / Ta intermediate layer deposited on it, and to achieve the greatest magnetoresistive effect, the ferromagnetic layers “SS” and “FS” are made of Co using a binder (pinning) sublayer from granular Co or using a known disintegrating Co-Cu metal solution, on top of the two-layer ferromagnetic structure, a fourth metallization layer “MET4” is applied and a dielectric passivating coating .

In order to interconnect the CMOS / SOI and STT-MRAM structures, the general STT-MRAM matrix fabrication process is implemented after the formation of the third metallization level of the LSI structure of CMOS / SOI technology by forming the next conductive Au / Ta sublayer on which the STT matrix is formed -MRAM "from a film multilayer ferromagnetic structure Au / Ta / Co / TaO _x / Co / Au by ion etching in an argon atmosphere in a complex combined mask using a negative electron resist that determines the shape of the particles, the dielectric layer is formed naturally by thinning the Ta thin film by letting the atmosphere into the chamber, then, to ensure good contact, the upper magnetic layer of the particles is coated with Au, then the entire structure is covered with a layer of dielectric Ta ₂ O ₃ and then it is removed from the tops of the ferromagnetic particles by explosion of the mask remaining after ion etching, two-layer ferromagnetic the cells are thus placed in a dielectric matrix, and the upper layer of cells is coated with Au to reach the surface.

According to the second variant, the MRAM memory built into the CMOS / SOI basic technological route, made in accordance with Savchenko’s architecture, includes a base electrode, a fixed magnetization ferromagnetic layer (FS), a free magnetization layer (“SS”), and a tunnel a dielectric interlayer or an insulating layer (“IS”) made of Al ₂ O ₃ located between “SS” and “FS”, the two-layer ferromagnetic structure on top is provided with a conductive Au layer with access to the surface to provide contact with the control write / read buses, and the entire two-layer ferromagnetic structure is placed in a matrix of Ta ₂ O ₅ dielectric. According to Savchenko’s method, the MRAM matrix structure is formed on the surface of the third MET3 metallization layer of the planar structure of the BIS CMOS / SOI technology with an additional Au / Ta intermediate layer deposited on top of it, and to achieve the greatest magnetoresistive effect, the ferromagnetic layers SS and FS "Are made on the basis of a multilayer pinning structure" ferromagnet-interlayer Ru-ferromagnet ", on top of a two-layer ferromagnetic structure, a fourth metallization layer" MET4 "and a dielectric passivating coating are applied.

To form the lower base conductive electrode of the structure of the MRAM memory matrix, the multilayer Au / Ta structure is deposited by magnetron sputtering on the VLSI structure of CMOS / SOI technology with STI insulation until the stage of “forming the fourth metallization level + VIA-3”.

To form a ferromagnetic layer with a fixed magnetization (“FS”) in the “MRAM” memory matrix using the Savchenko architecture, the first antiferromagnetic layer (Pinning) is applied to the surface of the multilayer structure using magnetron sputtering, then a layer of a ferromagnet is applied, then a layer of Ru and a layer of ferromagnet .

Then, to form a tunneling layer of dielectric, an Al ₂ O ₃ dielectric _of optimum thickness is deposited onto the surface of the structure, allowing a current to pass through an element with a resistance of the order of 10 ⁵ Ω · μm ² .

In order to form a ferromagnetic layer with free magnetization (“SS”), a layer of a ferromagnet is applied to the surface of the insulating layer (“IS”) by magnetron sputtering, then a layer of Ru and a layer of ferromagnet.

To ensure contact with the write / read control buses, an Au layer is applied to the surface of the ferromagnetic layer with free magnetization (“CC”).

To form multilayer magnetic cells, a photoresist is applied to the surface of the structure, including the surface of the upper layer - Au, photocopying is performed using the “Cells” photo template and the operation is carried out to heat-suppress the photoresist, then the multilayer ferromagnetic structure is etched and the photoresist is removed.

To form the dielectric insulation of the elements of the matrix of storage cells (ZA), a dielectric layer of Ta ₂ O ₅ is applied to the structure surface with a thickness equal to the thickness of the layers of the ferromagnetic cell, a thick layer of photoresist is applied, and a plasma-chemical etching of the layers of photoresist and Ta _{2 is} performed to planarize the surface O ₅ , in which the same etching rate of these materials is selected.

To form the fourth metallization level of the MRAM matrix, a Ti / Al layer is deposited, then MET4 photocopying is performed and Ti / Al is removed to the oxide by reactive ion etching.

To form a protective dielectric layer of the entire surface of the “MRAM” matrix on the LIS CMOS / SOI structure, a “SATEOS-SiO ₂ ” layer is deposited and “PECVD-SW” is deposited, then photocopying “Passivation” and reactive-ion etching of the layers “PECVD- SiN "," SATEOS-SiO ₂ ".

The technical solution is illustrated by the following figures.

Figure 1. Formation of active areas of the VLSI structure of CMOS / SOI technology.

Figure 2. The final formation of isolation “STI” of the VLSI structure of CMOS / SOI technology.

Figure 3. The formation of the n-pocket structure of VLSI technology CMOS / SOI.

Figure 4. The formation of polysilicon gates structure VLSI technology CMOS / SOI.

Figure 5. Formation of n-drains of the VLSI structure of CMOS / SOI technology.

6. The formation of interconnects structure VLSI technology CMOS / SOI.

7. Structure after annealing.

Fig. 8. The formation of titanium silicide structure VLSI technology CMOS / SOI.

Fig.9. Formation of contact windows of the VLSI structure of CMOS / SOI technology.

Figure 10. The deposition of W and HMP W / TiN / Ti to form the structure of the VLSI CMOS / SOI technology.

11. Formation of the first metallization level of the VLSI structure of CMOS / SOI technology.

Fig. 12. CMP layer "PECVD-SiO ₂ " structure VLSI technology CMOS / SOI.

Fig.13. CMP layer W / TiN / Ti structure VLSI technology CMOS / SOI.

Fig.14. Formation of the second level of metallization of the VLSI structure of CMOS / SOI technology.

Fig.15. Formation of the fourth metallization level of the VLSI structure of CMOS / SOI technology.

Fig.16. The final form of the VLSI structure of CMOS / SOI technology with polysilicon gates.

Fig.17. The formation of the "third level of metallization +" VIA-3 "" for "MRAM".

Fig. 18. Multilayer Au / Ta structure for MRAM.

Fig.19. Lower non-magnetic conductive electrode for "MRAM".

Fig.20. Deposition of Co and Ta ferromagnets for MRAM.

Fig.21. Natural oxidation and deposition of a second ferromagnetic Co layer and Au layer for MRAM.

Fig.22. Drawing a combined mask for "MRAM".

Fig.23. Exposure of the structure of the electron beam lithographic system for "MRAM".

Fig.24. Sequential etching of the layers of the metal mask for "MRAM".

Fig.25. Ion etching (IT) of a heat-treated resist for MRAM.

Fig.26. Ion etching of the Co / TaO _x / Co / Au ferromagnetic structure for MRAM.

Fig.27. The deposition of the dielectric layer Ta ₂ O ₅ for "MRAM".

Fig.28. Formed magnetic cells surrounded by a dielectric for "MRAM".

Fig.29. Formation of the fourth level of wiring for "MRAM".

Fig.30. Passivation formation for MRAM.

Fig.31. The final view of the MRAM structure on the VLSI CMOS / SOI technology with n ⁺ - p ⁺ polysilicon gates.

Fig. 32. a) - the multilayer structure of the memory element, b) - options for constructing the architecture of the MRAM chip.

Fig. 33. The formation of the "third level of metallization + VIA-3" for "MRAM" according to the Savchenko method.

Fig. 34. The formation of the lower base conductive electrode for "MRAM" according to the Savchenko method.

Fig. 35. Formation of a “Pinning” layer and a stable layer for “MRAM” according to the Savchenko method.

Fig. 36. Formation of a sequence of layers for a magnetoresistive memory cell for "MRAM" according to the Savchenko method.

Fig.37. The etching of the multilayer structure for "MRAM" according to the method of Savchenko.

Fig. 38. The deposition of the dielectric layer for "MRAM" according to the Savchenko method.

Fig. 39. Application of a thick layer of photoresist for "MRAM" according to the Savchenko method.

Fig.40. The formation of insulation for "MRAM" according to the method of Savchenko.

Fig. 41. Formation of the fourth metallization level for “MRAM” according to the Savchenko method.

Fig. 42. Formation of passivation of the structure "VLSI CMOS / SOI +" SDT-MRAM "for" MRAM "according to the Savchenko method.

Fig. 43. BAX manufactured element Co / TaO _x / Co (sample No. 3). Sweep: along the X axis, the voltage is 100 mV / cell; the current along the Y axis is 10 μA / cell. Full sweep along the axis of 500 mV (in one polarity) and 40 µA. The operating point when measuring R (H) is 100 mV.

Fig.44. Distribution of impurity elements in the structure.

Fig.45. The dependence of the resistance on the external magnetic field for elliptical particles is 300 × 200 nm.

Fig. 46. Dependence of resistance on the external magnetic field for elliptical particles 200 × 100 nm (field along the long axis of the particle).

Fig.47. Field along the length (a) and short axis (b) of the particle.

Fig. 48. IV characteristics of four Co / TaO _x / Co elements: a) BAX in the current range I = 0 ... 10 ^-4 A; b) the current-voltage characteristic in the field of currents I = 10 ^-4 ... 10 ^-7 A (for convenience, the positive and negative branches are presented in the form of a module in one graph).

Fig. 49. The dependence of the resistance of four elements on the voltage: a) dependence in the region R = 0 ... 7 · 10 ³ Ω; b) the dependence in the region R = 3 · 10 ³ ... 7 · 10 ⁴ Ω.

Fig. 50. AFM image of a rectangular wire with ferromagnetic nanoparticles located on it.

Fig. 51. The image on the MSM of the particle array section after magnetization in a magnetic field with an induction value of +300 G.

Fig. 52. The image on the MSM of the particle array section after magnetization in a magnetic field with an induction value of -250-280 G. Magnetization reversal of all particles occurred.

Fig. 53. AFM image of a rectangular wire with ferromagnetic nanoparticles located on it. Arrows - large - shows the direction of the current, small - the direction of the magnetic field.

Fig. 54. The successive stages of the experiment on the magnetization reversal of particles by current. The direction of the magnetic field created by the current coincides with the horizontal axis. The direction of the magnetizing magnetic field also coincides with the horizontal axis: a) stage 1. Coercive field of the selected particle 250 G; b) stage 2. The central particle is magnetized by the current in a magnetizing magnetic field of 50 G. (Thus, the magnetic field created by the current is ≈200 G.).

Fig. 55. The main stages of the manufacture of two-layer magnetic particles: (a) applying a Co / Si / Co film to a substrate; (b) the formation of wells in the film of the electronic resist PMMA (polymethylmethacrylate); (c) coating the structure with film V; (d) the “lift-off” process; e) etching of the Co / Si / Co structure in an Ar atmosphere.

Fig. 56. MSM image of a sample in a zero magnetic field (a) after magnetization in a field of -650 Oe; (b) after magnetization in a field of +220 E.

The technical solution is as follows.

Built-in VLSI technology CMOS / SOI memory "MRAM" and the method of its manufacture have two main options. According to the first of them, the structure of the MRAM memory matrix integrated into the basic CMOS / SOI technological route is formed, which is the basic structure of the CMOS / SOI LSI technology, formed up to the third metallization level, freely magnetizable ferromagnetic layer (“CC”), a ferromagnetic layer with fixed magnetization (“FS”) and a tunnel insulating layer (“IS”) located between “SS” and “FS”. "FS" is located on an additional intermediate conductive layer Au / Ta and is made of a film ferromagnetic structure Co. The “IS” located on it is made of TaO _x . The ferromagnetic “SS” located on top of the “IS” is made of a Co ferromagnetic structure, the Au / Ta / Co / TaO _x / Co / Au two-layer ferromagnetic structure is provided with an Au conducting layer on top to exit to the surface to provide contact with the write / read control buses. The entire two-layer ferromagnetic structure is placed in a matrix of a dielectric Ta ₂ O ₅ .

According to the second option, the structure of the MRAM memory matrix, embedded in the basic CMOS / SOI technological route, is formed, made in accordance with Savchenko architecture, which is the basic structure of CMOS / SOI LSI technology, formed to the third metallization level, the base electrode, and an antiferromagnetic layer with a fixed magnetization (“FS”), a freely magnetizable ferromagnetic stable layer (ferromagnet-interlayer Ru-ferromagnet) (“CC”), a tunneling interlayer-dielectric (Al ₂ O ₃ ), or an insulating layer oh (“IC”) located between “SS” and “FS”, the upper electrode, “FS” is located on an additional intermediate conductive layer Au / Ta and is made of a Pinning multilayer ferromagnetic structure located on it, “IC” is made of Al ₂ O _3, located on top of the "IP" ferromagnetic "SS" is made of a multilayer ferromagnetic structure "ferromagnetic-layer Ru-ferromagnet", double-layered ferromagnetic structure on top provided with a top electrode of conductive Au layer with access to the surface for contact with councils yayuschimi write / read buses, and all-layer ferromagnetic structure is placed in a matrix of dielectric Ta ₂ O _5.

An example of the implementation of a technical solution

The basis of the integrated “VLSI” CMOS / SOI technology “MRAM” memory and the method of its manufacture is the technological route of manufacturing the VLSI technology CMOS / SOI with isolation “STI”. The route includes the formation of n- and p-pockets, isolation of “STI”, n ⁺ and p ⁺ -silicon gates for n- and p-channel transistors, respectively, areas of “LDD”, p ⁺ -stocks reaching the bottom of the instrument layer, as well as the formation of self-aligned titanium silicide and a reliable four-level metallization system.

1. Formation of the VLSI structure of CMOS / SOI technology with polysilicon gates. A SOI plate with a p ^- type instrument layer thickness of 0.2 μm, a buried oxide thickness of 0.2-0.4 μm, and a substrate orientation of (100) was used as the initial structure. Below, the main technological stages of manufacturing the “MRAM” chip with reference to the VLSI technological route, CMOS / SOI technology, are described in detail. This basic technological route in the manufacture of such products consists of the following steps.

0. Formation of global alignment marks.

1. The formation of active areas. On the SOI plate, buffer oxide is grown and a layer of Si ₃ N _{4 is} deposited. Next, conduct active region photolithography (FLG) (Figure 1) and acidify the sides of the islets.

2. The formation of insulation "STI". Precipitated by the method of "HDP" SiO ₂ and conduct compaction (annealing). Next, perform FLG "Inversion of active areas" to create insulation "STI" and chemical-mechanical polishing (CMP). Next, etching of Si ₃ N ₄ in hot phosphoric acid and etching of SiO ₂ are carried out. After this, the oxidation process is carried out, a buffer oxide is formed. At this stage, the formation of insulation "STI" ends (Figure 2).

3. Formation of an n-pocket. A photocopying operation (FC) is carried out for the n-pocket and ion doping (IL) with phosphorus (Figure 3). Remove the photoresist.

4. The formation of a p-pocket. Then perform the FC p-pocket and conduct IL boron. Then perform the plasma-chemical removal of photoresist (PUF).

5. The formation of transistor gates. Polysilicon gates are formed by removing buffer oxide, growing a gate oxide, and depositing undoped Si *. Next, conduct FLG "Gates" (Figure 4).

6. The formation of the "LDD" (n ^- stock). Perform FC "n ^- stock" and IL phosphorus and arsenic (Figure 5).

7. The formation of "LDD" (p ^- stock). Perform FC "p ^- stock" and ion doping of BF ₂ .

8. The formation of spacers. By the method of chemical vapor deposition (CVD), a Silane-SiO ₂ layer is formed and reactive ion etching (RIT) of the Silane-SiO ₂ + SiO ₂ layer is performed to form interconnects (spacers) (Fig. 6).

9. Formation of effluents (n ⁺ stocks). The next operation is oxidation. Then perform the FC "n ⁺ -stock" and conduct IL As ⁺ . During the formation of n ⁺ sources, the gate of the n-channel transistor is doped (n ⁺ polysilicon gate).

10. Formation of effluents (p ⁺ stocks). Perform FC "p ⁺ -stock" and conduct IL boron. When p ⁺ sources are formed, the gate of the p-channel transistor is doped (p ⁺ polysilicon gate). Then, a layer of "LPTEOS-SiO ₂ " is precipitated by the method of CVD. Next, annealing is carried out and fast annealing (diffusion of effluents) is performed (Fig. 7).

11. The formation of high resistance. The FLG is carried out: they protect the region of high-resistance resistances and then perform RIT SiO ₂ .

12. The formation of titanium silicide. The formation of titanium silicide begins with Ti deposition and TiN deposition. A two-stage heat treatment is necessary to obtain the TiSi ₂ compound (Fig. 8).

13. Formation of contacts. The precipitation of borophosphor glass ("BPTEOS-SiO ₂ "), its melting and deposition of "SATEOS-SiO ₂ " followed by CMP are carried out. Form contacts: for this, conduct FC “Contacts”, then perform the process of thermal suppression and conduct RIT SiO ₂ (Figure 9). The following is the process of deposition of Ti / TiN barrier layers. The deposition of tungsten (W) and then perform the CMP layer W / TiN / Ti to SiO ₂ (Figure 10).

14. The formation of the first level of metallization (wiring). The next step is the deposition of Ti / Al / Ti / TiN. Perform FC "MET1" and RIT TiN / Ti / Al / Ti (Fig.11). Next, a thick layer of inter-level dielectric is deposited (“SATEOS-SiO ₂ ” and “PECVD-SiO ₂ ”). Conduct HMP "PECVD OXIDE" (Fig.12).

15. The formation of "VIA-1". Then perform the FC "VIA-1". RIT SiO _{2 is} carried out over the entire thickness. Next, perform the process of deposition of Ti / TiN and deposition of W and CMP layer W / TiN / Ti to SiO ₂ (Fig.13).

16. The formation of the second level of metallization. The next step is the deposition of Ti / Al / Ti / TiN. Perform FC "MET2" and RIT layer TiN / Ti / Al / Ti (Fig). In the next step, a thick inter-level dielectric (SATEOS-SiO ₂ and PECVD-SiO ₂ ) is precipitated and a VECW-SiO ₂ CMP is performed.

17. The formation of "VIA-2". At the next stage, FC VIA-2 is performed. RIT SiO _{2 is} carried out over the entire thickness. Next, a Ti / TiN sputtering, deposition of W and HMP of a W / TiN / Ti layer to SiO _{2 is} carried out.

Then, in a similar manner, they implement:

18. The formation of the third level of metallization.

19. The formation of "VIA-3".

20. The formation of the fourth level of metallization. At this technological stage, Ti and Al are sprayed. Perform FC "MET4" and the method of RIT remove Al / Ti to silicon oxide (Fig.15).

21. The formation of a protective dielectric layer. A "SATEOS SiO ₂ " layer is precipitated and "PECVD SiN" is precipitated. Then, FC Passivation is performed and RITs of the layers “PECVD SiN”, “SATEOS-SiO ₂ ” are carried out. Finish this step with Al. On Fig shows the final structure of the generated VLSI CMOS / SOI technology with n ⁺ - p ⁺ polysilicon gates.

2. Implementation of the technological route of manufacturing "MRAM".

The process of crystal production consists of several main blocks, which in turn comprise more than 400 complex operations. Since the elevated temperature affects the quality of the memory cell and its operation, to reduce the impact of this factor, the formation of "MRAM" will occur at the upper level of metallization. The problem of the heterogeneity of the properties of Ws is explained by the imperfection of the production process. In the proposed method for the implementation of technological routes, the production of ZW is realized between the third and fourth metallization levels, the formation processes of which are carried out at low temperatures.

2.1. Formation of a “MRAM” cell of a film multilayer ferromagnetic structure Au / Ta / Co / TaO _x / Co / Au using explosive PLG.

In general, the method of manufacturing an element can be described as follows: on the conducting Au / Ta sublayer, cells are formed from a film multilayer ferromagnetic structure Au / Ta / Co / TaO _x / Co / Au by ion etching in an argon atmosphere in a complex combined mask using a negative electron resist determining the shape of the particles. The dielectric interlayer is formed by the natural oxidation of a thin Ta film using the atmosphere inlet into the magnetron sputtering chamber. To allow good contact, the upper magnetic layer of the particles is coated with Au. Then the whole sample is covered with a layer of a dielectric Ta ₂ O ₅ , then it is removed from the tops of the magnetic particles by explosion of the mask remaining after ion etching. Thus, bilayer ferromagnetic cells are placed in a dielectric matrix, and the upper gold layer of cells has an exit to the surface.

In more detail, the manufacturing method is as follows.

19-0 ^∗) . ( ^∗) In the double stage numbering “X-Y”, “X” means the sequence number of the stage from the beginning of the formation of the LSI structure of the CMOS / SOI technology, “Y” means the serial number of the stage of formation of one of the two “MRAM” options, starting from the formation stage 3 level of metallization, adopted as "O".)

The formation of the third level of metallization (p. 18 VLSI). As the initial structure, the VLSI structure of the CMOS / SOI technology with STI insulation was used, the manufacturing method of which is described in Section 0 ... 18. On Fig shows the procedure for the formation of the "third level of metallization +" VIA-3 "", which is a continuation of the process of forming the final structure of the VLSI technology CMOS / SOI with storage cells (ZA) based on the elements of "MTJ".

20-1. The formation of the lower non-magnetic conductive electrode. A multilayer Au / Ta structure is applied over the entire surface by magnetron sputtering (FIG. 18). This structure is the lower non-magnetic conductive electrode (Fig.19). Tantalum provides high adhesion to the substrate and relieves stress in the multilayer structure, and gold, in turn, provides high electrical conductivity of the structure.

21-2. The formation of successive cell layers. The first ferromagnetic layer (Co) is applied to the surface of the multilayer structure by magnetron sputtering and coated with a thin layer of Ta (FIG. 20). The Ta layer is naturally oxidized through chamber evacuation or oxygen injection. This layer is a dielectric layer between two magnetic layers. On the surface of oxidized tantalum TaO _x by magnetron sputtering, a second ferromagnetic layer (Co) is deposited, followed by an Au layer. The upper layer of gold allows you to provide a small resistance between the ferromagnetic layer and the expanded contact pad (Fig.21).

22-3. The formation of multilayer magnetic cells. To make multilayer magnetic cells from a Co / TaO _x / Co / Au layer, a combined mask is applied onto the surface of the sample, including the surface of the upper layer of the Au structure, consisting of: 1) a heat-treated negative electron resist (P1); 2) a multilayer metal mask (Cu / V / Cu); 3) standard negative electronic resistor FP-9102 (based on phenolaldehyde resins) ("P2"). With an additional layer of resist, before applying a metal mask to it, heat treatment is carried out, which makes it resistant to a standard alkaline developer (Fig. 22).

Lithography (LH) is carried out: the structure is exposed to the electron beam of the lithographic system. Processing the sample in the developer leads to the formation of islands in the upper layer of the mask — the negative electron resist, that is, the resist regions that were processed by the electron beam remain. These resist islands are in the form of future cells. In this case, the lower layer of the mask — the heat-treated resist — does not change (Fig. 23). Conduct sequential ion etching (IT) of the layers of the metal mask (Fig.24): IT Cu (in an argon atmosphere); IT V (in the atmosphere of Freon) (in this case, the lower layer of copper serves as the so-called “stop-layer”); IT Cu (in argon atmosphere). As a result, a negative electron resist layer remains open on the sample surface, and a metal mask Cu / V / Cu lies on it with the shape of future magnetic cells. Then, the heat-treated resist is removed from the entire surface of the sample (with the exception of areas covered by Cu / V / Cu) using IT in an oxygen atmosphere. In this case, “P2” and the upper layer of Cu are removed. The vanadium layer is practically not changed. As a result, islands consisting of Cu and V resist layers with a lateral shape of future particles are left on the surface of the Co / TaO _x / Co / Au film structure (FIG. 25). Ion etching of the ferromagnetic structure of Au / Ta / Co / TaO _x / Co / Au is carried out in an argon atmosphere in a Cu / V mask. As a result, a multilayer Co / TaO _x / Co / Au / resist / Cu / V cell is formed on the surface of the lower supply electrode (Fig. 26).

23-4. The formation of isolation. The magnetic cell must be surrounded by a dielectric layer to separate the lower and upper pads. A Ta ₂ O ₅ dielectric layer is applied over the entire surface of the sample, equal to the thickness of the Co / TaO _x / Co / Au layer (Fig. 27).

24-5. Explosive photolithography. The “lift-off” process is carried out, namely, the remaining mask with a heat-treated resist on the surface of the magnetic particles is removed in a special alkali solution (analogue of “remover”). As a result, magnetic cells are formed, packed in a dielectric matrix and having an exit to the surface (Fig. 28).

25-6. The formation of the fourth level of metallization. At this process stage, Ti / Al is sprayed. Perform FC "MET4" and the method of RIT remove Al / Ti (Fig.29).

26-7. The formation of a protective dielectric layer. A “SATEOS-SiO ₂ ” layer is precipitated and “PECVD-SiN” is precipitated. Then, FC Passivation is performed and RITs of the layers “PECVD-SiN”, “SATEOS-SiO ₂ ” are carried out (Fig. 30).

On Fig shows the final structure of "MRAM" on the VLSI technology CMOS / SOI with n ⁺ - p ⁺ polysilicon gates.

2.1. Formation of the “MRAM” cell operating in the switching mode by the Savchenko method from a film multilayer ferromagnetic structure.

The Savchenko switching mode is based on the unique behavior of the composite antiferromagnetic free layer (“SAF”), which is formed from two ferromagnetic layers separated by the thinnest non-magnetic layer connecting them together. The memory cell itself and the microcircuit based on it are a multilayer structure consisting of the following layers (Fig. 32-a)): base electrode; antiferromagnet (“Pinning” layer); stable layer (ferromagnet, Ru interlayer, ferromagnet); dielectric tunnel layer (Al ₂ O ₃ ); free layer (ferromagnet, Ru interlayer, ferromagnet); upper electrode. In addition, the individual memory elements must be combined into a memory matrix, determined by the architecture of the chip (Fig.32-b)).

A method of manufacturing this structure includes the following process steps.

19-0. The formation of the third level of metallization. As the initial structure used VLSI CMOS / SOI technology with insulation "STI", the production route of which is discussed in paragraphs 0-21 for VLSI, until the stage of formation of the fourth metallization level (Fig. 33). A multilayer Au / Ta structure is applied over the entire surface by magnetron sputtering (Fig. 18). This structure is the lower non-magnetic conductive electrode (Fig. 34). Tantalum provides high adhesion to the substrate and relieves stress in the multilayer structure, and gold, in turn, provides high electrical conductivity of the structure.

20-1. Formation of a stable cell layer. On the surface of the multilayer structure by the method of magnetron sputtering, a first antiferromagnetic layer (“Pinning”) is applied, a layer of a ferromagnet is applied, then a layer of Ru and a layer of a ferromagnet (Fig. 35).

21-2. Formation of a tunneling layer of a dielectric and a free layer of a cell. The dielectric Al ₂ O _{3 is} precipitated. The thickness of the tunnel layer between the ferromagnetic electrodes is chosen to the optimum thickness with the possibility of passing current through the MTJ element with a resistance of the order of 10 ⁵ Ω · μm ² . Next, by a method of magnetron sputtering, a layer of a ferromagnet is applied, then a layer of Ru, a layer of a ferromagnet and then a layer of Au (Fig. 36).

22-3. The formation of multilayer magnetic cells. Further, multilayer magnetic cells are formed from the layer obtained in p.21-2. On the surface of the sample, including on the surface of the upper layer of the Au structure, a DF is deposited, a FC is made according to the "cells" photo template (FS) and the DF is thermally suppressed. Spend IT multilayer ferromagnetic structure (Fig.37). Remove the FR.

23-4. The formation of insulation (Fig.40). The magnetic cell must be surrounded by a dielectric layer to separate the lower and upper pads. To do this, a dielectric layer of Ta ₂ O ₅ is applied to the entire surface of the sample, equal to the thickness of the cell layers (Fig. 38). Apply a thick layer of FR (Fig. 39). To planarize the surface, the PCT process of the FR and Ta ₂ O ₅ layers is performed, in which the same etching rate of these materials is selected.

24-5. The formation of the fourth level of metallization. At this stage, Ti and Al are precipitated. Perform FC "MET4" and the method of RIT remove Al / Ti (Fig.41).

25-6. The formation of a protective dielectric layer. Precipitate the "SATEOS-S702" layer and precipitate "PECVD-S7JV". Next, perform FC "Passivation" and conduct RIT layers "PECVD-SiN", "SATEOS-SiO ₂ " (Fig. 42).

According to the proposed method, two-layer magnetic particles Au / Ta / Co / TaO _x / Co / Au with electrodes for transmitting current were made from a multilayer film to test the technology and control the topology of the magnetoresistive element, and the current-voltage characteristic (IVC) was measured, which is represented on Fig. As follows from the data of FIG. 43, the I – V characteristic is nonlinear, which indicates the presence of a tunnel barrier between the electrodes. The resistance of the structure was about 10 ⁴ Ohms with a submicron area of the particle. To check the quality and quantity of the materials that make up the element under study, structural studies of the film structure, which underlies the MTJ element, were carried out by secondary ion mass spectrometry (SIMS). The measurements were carried out on a setup equipped with a time-of-flight mass analyzer. A typical detection limit of elements in a SIMS installation is 10 ¹⁶ at / cm ³ . This made it possible to separate the individual layers in the structure — the upper Au layer about 40 nm thick, then the Co layer — 15 nm, Ta (TaO) —2–4 nm, Co — 15 nm, five alternating Au / Ta layers with a total thickness of 40 nm, and finally - Si substrate.

The most technologically challenging is the region of the Co / TaO / Co structure; the manufacturing quality of this gap largely determines the magnetotransport properties of the structure as a whole. The SIMS facility allows one to detect both elementary Ta ions and its clusters with oxygen - TaO ^- . That is present in the same concentration in several layers of the structure. At the same time, TaO ^- ion in a significant amount is observed only in the interval between two layers of Co. The data obtained allow us to characterize this part of the structure precisely as Co / TaO / Co. The TaO layer width measured at half maximum of the profile is 4 nm.

Fig. 44 shows the distribution of impurity elements with the highest concentration in the structure. Elements Al, Cr, Fe correlate with Co and Ta layers. Apparently, their source is Co and Ta targets used in magnetron sputtering. Al has the highest concentration among these elements; it was about 10 ¹⁹ at / cm ³ . Impurities C and O correlate with Ta layers; their most probable source is the residual atmosphere of the deposition chamber. The maximum value of the concentration of atoms was about 5 · 10 ²⁰ at / cm ³ in two regions of the structure at the transitions “Si substrate - layer” and “layer 5 · (Au / Ta) - Co”. Impurity C is also present, and in lesser amounts F and Cl. The source of these impurities, apparently, was the residual atmosphere of the chamber. 12 MTJ structures were fabricated and brought to current measurements. The first 7 samples differed mainly in the methods of forming tunnel barriers. They were made by the method using Au as contact materials. The ferromagnetic particles in these magnetoresistive elements had a size of 300 × 500 nm or more. The second and third Co / TaO _x / Co samples showed the presence of magnetoresistance of the order of 1% and 3%, respectively. The fabrication of these samples differed in pressure during the oxidation of the Ta interlayer — 0.1 and 1.0 atm of oxygen, respectively. The optimum TaO _x barrier thickness was determined. If the tunneling barrier was made of Ta film with a thickness of less than 2 nm, then the BAX images had a linear (non-tunneling character). Sample No. 7 was formed in the same way as No. 3, and had the same galvanic-magnetic properties, showed the same magnetoresistance - about 3%. This allows us to talk about creating a reproducible method of forming multilayer elements with magnetoresistance.

Production of magnetoresistive elements and rulers from the same type of elements. 15 iterations of samples of magnetoresistive elements of various designs and sizes were made. Each of the samples - chips - consisted of about 100 independent magnetoresistive elements. For definiteness, each element has a number consisting of the row number and the serial number of the element in the row. All elements had a common (lower) electrode and at the top, a separate contact area was formed above each element. To carry out experiments on the magnetization reversal of magnetoresistive elements by the field of the flowing current and to study the effect of external fields on the magnetic state of the element and the safety of information in it using electron lithography on a base conductor, chains of ferromagnetic particles of submicron size were made. As shown by studies in an external magnetic field using a magnetic force microscope (MSM), the coercive particle field is about 200-250 G.

The results of the study of the electrophysical parameters of magnetic multilayer structures. The dependence of the magnetoresistance of one of the magnetic elements on the magnetic field applied along the long axis of the magnetic element, elliptical shape (size 300 × 200 nm) is shown in Fig. 45 (voltage drop 100 mV). The magnitude of magnetoresistance was about 3%. The structure resistance was ~ 10 kOhm; measurements were carried out with a current passing of ~ 1-50 μA (voltage drop of 10-500 mV). The magnitude of magnetoresistance was ~ 3% at a voltage drop of 10 mV and gradually decreased with increasing measuring current. The shape of the magnetoresistance curves can be explained as follows: when an external magnetic field of the order of 500 Oe is applied, the magnetizations of the layers become collinear. If the magnetic field is reduced, then the magnetizations of the layers begin to unfold relative to each other, i.e. an angular state occurs. This reversal occurs to a magnetic field of the order of zero oersted. With a change in the direction of the external field on the R (H) curve of the jumps, the particle passed into the antiferromagnetic state, the magnetizations of the layers are oppositely directed. This state is stable up to fields of the order of 500 Oe; with an increase in the field, the magnetoresistance R (H) abruptly decreases, which corresponds to the transition of a particle to a state with ferromagnetic ordering of the layers.

With a decrease in the size of the magnetoresistive element, it was possible to achieve that only two stable states exist in an external magnetic field. The dependence of the magnetoresistance of one of the magnetic elements on the magnetic field applied along the long axis of the magnetic element, elliptical shape (size 200 × 100 nm) is shown in Fig. 46. The magnitude of magnetoresistance was about 2%. In fact, this element allows you to store information when you turn off the field. The results of measuring the dependence of resistance on a magnetic field directed along the short axis of the particle are presented in Fig. 47. These measurements show that the resistance of the system is proportional to the cosine of the angle between the magnetic moments of the layers. Thus, the possibility of observing magnetoresistance in a two-layer magnetic structure Au / Co / TaO _x / Co / Au has been demonstrated. The results obtained make it possible to develop the design of magnetoresistive elements of storage devices based on the effect of tunnel magnetoresistance. This result was achieved thanks to the development and development of a method for manufacturing magnetoresistive elements with dimensions of 100 × 200 nm, placed between the supply electrodes.

Measurement of current-voltage characteristics (BAX) of multilayer structures. A procedure was developed for measuring the current-voltage characteristics in the presence or absence of an external magnetic field in the temperature range from 77 K to 300 K. With an expected resistance of the magnetoresistive element of the order of 10 kOhm, this measurement technique allows you to register a change in the resistance of structures with a maximum error of ± 0.1-0 , 3%.

The most characteristic positive BAX measurements of multilayer magnetoresistive structures are presented in FIG. 43. It can be seen that the BAX of all the given samples (sample 7, elements on the chip are chosen arbitrarily) are essentially nonlinear, i.e. really tunnel heterostructures are made. It can also be seen that the BAX of various samples (manufactured in different technological cycles) are close, which indicates the reproducibility of the results and the accuracy of the sample production methodology.

The spread of resistance across the chip is about 20%, which is associated with a linear change in particle size over the sample, due to the features of the electronic lithography mode used, i.e. changing the area of an element.

Figures 48 and 49 show BAX obtained by digital methods, and the dependence of the element resistance on voltage R (U) for four randomly selected magnetoresistive elements located on the same chip. As follows from the analysis of the obtained data, the dependences of the measured parameters for all experimental conditions for different elements are close to each other.

Research of processes of magnetization reversal of memory elements. To study the possibility of magnetization reversal of ferromagnetic nanoparticles by an electric current field, a series of test samples was made. Each sample included a chain of ferromagnetic nanoparticles. Samples were prepared by photolithography on a silicon substrate. Using electronic lithography on a base conductor, a chain of elliptic ferromagnetic particles with different lengths of the semiaxes of the ellipse and a thickness of 25 nm was fabricated. The size, shape and thickness of the particles were chosen so that their ground state was uniformly magnetized. On Fig shows the image on the AFM test sample with particles located on it. Experiments on magnetization reversal of ferromagnetic nanoparticles by a magnetic field of an electric current were carried out in a vacuum chamber of a scanning probe microscope (SPM). To do this, wires were brought into the vacuum chamber through a lock in which voltage was applied to the sample. The chosen experimental design provided, firstly, the possibility of passing current through the sample (in other words, creating a magnetic field by electric current). Secondly, the application of an external magnetic field with an induction value of up to 800 Gs using the built-in electromagnet. Thirdly, using magnetic force microscopy (MSM), it was possible to directly monitor the magnetic states of the studied ferromagnetic nanoparticles. Initially, estimates of the coercive field of the manufactured particles were made. As shown by MSM studies of MSM, the application of an external magnetic field by induction of 300 G along the long axis of the particles is sufficient for magnetization reversal of the entire chain of particles. On Fig shows a plot of an array of ferromagnetic particles after magnetization in a magnetic field with an induction value of 300 G. The direction of the long axis of the particles coincides with the horizontal axis in the figure. The direction of the applied magnetic field from left to right ("+ direction"). When a magnetic field is applied in the opposite orientation (from right to left, or "- direction"), a magnetization reversal of one particle occurs with an induction of -250 G (Fig. 52). Thus, the coercive particle field is of the order of 250-280 G. Next, experiments were conducted on the magnetization reversal of ferromagnetic nanoparticles with a magnetic field created by direct current. The scheme of the experiment for transmitting current is shown in Fig. 53. As follows from Fig. 53, the geometry of the structure is selected so that the lines of the magnetic field created by the direct current coincide with the long axis of the particles (axis of easy magnetization). Since the direction of the magnetic field of the current was not initially known, the demagnetized state of the particle chain, in which particles with different directions of the magnetization vector were present, was chosen as the initial state. It was shown that magnetization reversal of particles does not occur up to a current of 120 mA (which corresponds to a current density of ~ 10 ⁷ A / cm ² ), with a further increase in current, the wire was destroyed. Experiments were carried out on magnetization reversal by current in a pulsed mode (pulse duration 200 ns). It is shown that with a pulse amplitude of 40 V, magnetization reversal does not occur, with an increase in the pulse amplitude to 50 V (which corresponds to a current density of ~ 10 ⁸ A / cm ² ), the wire is destroyed. The magnetization reversal of particles was realized in a pulsed mode in an external magnetizing magnetic field. The subsequent stages of the experiment are shown in Fig. 54. A section of the chain with particles 500 nm by 300 nm in size was selected, and coercive particle fields were studied in this section. For magnetization reversal by a current, the central particle in Fig. 54 with a coercive field of 250 G was selected (stage 1). The magnetization reversal by the current of this particle occurred when pulses with an amplitude of 25 V were applied (the pulse amplitude was specially chosen two times less than the threshold amplitude of 50 V at which the metallization was destroyed) and a magnetizing external magnetic field coinciding in direction with the current magnetic field of 50 G. (stage 2). Thus, the magnitude of the inductance of the magnetic field generated by the current in this mode was about 200 G.

The measurements indicate the implementation of the "MTJ" effect on the formed magnetic elements with lateral dimensions of 100 × 200 × 25 nm, which allows you to integrate these elements into the structure of "MRAM", with the formation of electric buses for controlling the processes of recording / reading information in electronic form.

The magnetization reversal procedure “MRAM” with architecture according to the Savchenko method is implemented in a similar way.

The proposed technical solutions based on the integration of STT-MRAM memory matrix formation technology with improved magnetic hysteresis of magnetic elements into the VLSI structure of the “complementary-metal-oxide-semiconductor / silicon-on-insulator” (CMOS / SOI) technology allow unified VLSI "STT-MRAM / CMOS / SOI" structure with wide functional capabilities: FPGA, microprocessor with RAM and ROM, etc.

APPENDIX A: METHOD FOR PRODUCING LATERALLY LIMITED MAGNETIC MULTILAYER STRUCTURES

In order for the magnetoresistive element to serve as a memory cell, only two magnetic states corresponding to “0” and “1” must be stable in it. It was proposed to make the magnetic part of the magnetoresistive element in the form of a thin two-layer elliptical particle with submicron lateral dimensions, consisting of two ferromagnetic layers separated by a thin non-magnetic dielectric layer. Such a proposal is not original, for example, see / 2, 3, 4 /.

Anisotropy of the shape creates a light axis along the long axis of the ellipse. With a suitable choice of the geometric parameters of the particle, the ratio of lateral sizes and thickness, each of the magnetic layers of the particle will always be uniformly magnetized along the easy axis of anisotropy. In this case, it is possible to realize two states with ferromagnetic and antiferromagnetic ordering between the layers.

Using an elliptical shape. It should be noted that the antiferromagnetic state can be realized in two ways: either in the magnetostatic interaction between the layers of particles, or in the formation of a soft magnetic (free) and magnetically hard (highly coercive) layer. As part of this technical solution, attempts have been made to implement antiferromagnetic ordering in both ways. Ferromagnetic ordering between layers can always be achieved in large fields of magnetization.

The manufacture of a magnetoresistive element can be divided into two parts. The first is the manufacture of the main part of the element - a two-layer ferromagnetic particle, consisting of two ferromagnetic layers separated by a thin non-magnetic dielectric layer. The second part is the manufacture of electrodes to the particle, providing the possibility of passing current through a magnetic particle (magnetoresistive element).

The lateral dimensions of the element should be 0.1-1 microns. The manufacture of ferromagnetic particles with similar sizes was carried out by electronic lithography using the “lift-off” (explosion) process.

1st stage. Initially, to fulfill the initial requirements, it was proposed to use particles with submicron sizes, elliptical shape and with magnetostatic interaction between the layers. The manufacture of two-layer magnetic particles without current electrodes is a significantly less laborious task and allows us to study the magnetization of the layers already at the first steps of developing a method for manufacturing magnetoresistive structures.

Bilayer ferromagnetic particles were prepared by electron beam lithography using a positive PMMA electronic resist (polymethyl methacrylate). The exposure of the electron resist was carried out in an electron microscope with a lithographic attachment. The metal mask used for etching was fabricated using a “lift-off” process.

In general terms, the initial manufacturing procedure can be described as follows: particles are formed from a film ferromagnetic multilayer structure by etching in an argon atmosphere in a mask of negative resist, which determines the shape of the particles. The first structures were made of a three-layer Co / Si / Co film. Subsequently, the nonmagnetic silicon interlayer, which is dielectric at a thickness of several nanometers, was replaced by tantalum oxide (TaO _x ) with the possibility of controlled oxidation.

The main steps of the manufacturing method of the magnetoresistive element are presented in Fig. 55.

1. Co / Si / Co films, one after another, were deposited onto a substrate by magnetron sputtering; A film of the PMMA electron resist is applied to the surface of this three-layer structure using a centrifuge. The residual vacuum in the chamber during magnetron sputtering is about 10 ^-5 Torr. The structure is illuminated by the electron beam of the lithographic system.

2. Processing the PMMA film - a positive resist in the developer (MIBK based on isopropyl alcohol) led to the formation of wells ("holes") in the PMMA film, i.e. areas of the resist that were illuminated by the electron beam are removed. Wells are in the form of future particles.

3. The resulting structure with a developed relief was covered with a V film by magnetron sputtering.

4. The “lift-off” process was carried out. The remaining PMMA film coated with V was removed in a remover (remover, “remover”), which was used as acetone.

As a result, islands V with the shape of future particles remained on the surface of the Co / Si / Co film.

5. Ion etching of the Co / Si / Co ferromagnetic structure in an argon atmosphere was carried out.

Using the above methodology, a structure consisting of 9 modules of ferromagnetic particles was manufactured. A general view of the sample is shown in Fig. 56.

The manufacture of contact pads was carried out by photolithography methods. Using the developed patterns on one substrate, it was possible to form a lattice of 10 × 10 magnetoresistive elements.

At the second stage, the method of manufacturing the element was modified: particles of a film multilayer ferromagnetic structure Au / Ta / Co / TaO _x / Co / Au were formed on the conducting sublayer by ion etching in an argon atmosphere in a complex combined mask using a negative electron resist that determines the shape of the particles. The dielectric interlayer was formed by the natural oxidation of a thin Ta film with the help of the atmosphere being poured into the chamber. To allow good contact, the upper magnetic layer of the particle is coated with Au. Then, the entire sample was covered with a layer of a dielectric Ta ₂ O ₅ , and it was removed from the tops of the particles by an explosion of the mask remaining after ion etching. Thus, bilayer ferromagnetic particles were placed in a dielectric matrix, the upper gold layer of particles had an exit to the surface (Fig. 55-a)). Consecutive expansion of the contact pads with submicron particle sizes of up to 400 microns was carried out (see Fig. 55-b), c)).

Literature

1. A method of manufacturing a layer of a magnetic tunnel junction in a magnetic random access memory device / Patent of the Republic of Korea, No. KR 20030002142, publ. 01/08/2003.

2. Magnetic random access memory and data recording method / Japanese Patent, No. JP 2005327988, publ. 11/24/2005.

3. A method of forming a magnetic tunnel junction (MTJ) for a magnetoresistive magnetic random access memory / US Patent No. US 2005277206, publ. 12/15/2005.

4. Goikhman A.Yu., Zenkevich A.V., Lebedinsky Yu.Yu. A method of forming structures of magnetoresistive tunnel junctions for magnetoresistive magnetic random access memory and the structure of a magnetoresistive tunnel junction for magnetoresistive magnetic random access memory (options) / Patent RF № RU 2367057 C2, publ. 09/10/2009.

Claims (36)

1. “MRAM” memory built into the CMOS / SOI basic technological route, including the base electrode, a fixed magnetization ferromagnetic layer (“FS”) made of a film ferromagnetic structure, a tunnel insulating layer (“IS”) located on it, made of TaO _x , located on top of the “IS”, a freely magnetizable ferromagnetic layer (“SS”) made of a ferromagnetic structure, a two-layer ferromagnetic structure on top is equipped with a conductive Au layer with access to the surface to provide contact with write / read control buses, and the entire two-layer ferromagnetic Au / Ta / Co / TaO _x / Co / Au structure is placed in a Ta ₂ O ₅ dielectric matrix, characterized in that the memory structure is “MRAM” (with transmission of spin torque “ STT-MRAM ”) is formed on the surface of the third metallization layer“ MET3 ”of the planar heterostructure of the VLSI CMOS / SOI technology with an additional Au / Ta intermediate layer deposited on top of it, and to achieve the maximum magnetoresistive effect, the SS and FS ferromagnetic layers are made of Co using binding uyuschego (pinning) sublayer of Co or granulated using a known disintegrating Co-Cu metal solution on top of the two-layered ferromagnetic structure is applied a fourth metallization layer "MET4" and dielectric passivation coating. 2. The MRAM memory built into the CMOS / SOI basic technological route, made according to the Savchenko method, including the base electrode, the fixed magnetization ferromagnetic layer (FS), the free magnetization ferromagnetic layer (SS), the dielectric tunnel layer or an insulating layer (“IS”) made of Al ₂ O ₃ located between “SS” and “FS”, the two-layer ferromagnetic structure on top is equipped with a conductive Au layer with access to the surface to ensure contact with the write / read control buses, and all two Leuna ferromagnetic structure is placed in a matrix of dielectric Ta ₂ O _5, characterized in that the memory structure «MRAM» (with Spin Transfer Torque «STT-MRAM») by the method Savchenko formed on the surface of the third layer of metallization "MET3" planar heterostructure VLSI Technology CMOS / SOI with an additional Au / Ta intermediate layer deposited on top of it, and to achieve the greatest magnetoresistive effect, the SS and FS ferromagnetic layers are made on the basis of a multilayer ferromagnet-interlayer pinning structure Single Ru-ferromagnet ", on top of the two-layer structure of a ferromagnetic layer applied to the fourth metallization" MET4 "and dielectric passivation coating. 3. A method of manufacturing a built-in CMOS / SOI memory “MRAM” embedded in the basic technological route, characterized in that, in order to form the initial planar heterostructure of the VLSI CMOS / SOI technology with “STI” insulation used as a substrate, and subsequent formation of a memory on it “MRAM” (with transfer of spin torque “STT-MRAM”), sequentially form in the instrument layer Si the SOI heterostructure of the region of n- and p-pockets, insulation “STI”, n ⁺ and p ⁺ -silicon gates for n- and p-channel transistors respectively koomnyh drains and sources of the MOS transistors, p ⁺ -Stock reaching to the bottom layer of the instrument, as well as self-aligned titanium silicide layers and reliable system of multilevel metallization structure is then formed on VLSI after the third metallization layer is also formed by planar technology memory «MRAM», comprising a freely remagnetizable ferromagnetic layer (“SS”), a ferromagnetic layer with a fixed magnetization (“FS”) and a tunnel insulating layer (“IS”) located between “SS” and “FS”, then form the fourth level etallizatsii and protective dielectric layer. 4. The method according to claim 3, characterized in that, in order to form a VLSI heterostructure of CMOS / SOI technology with silicon oxide insulation with small grooves ("STI"), a SOI plate with an instrument layer thickness p ^{- is} used as the initial structure for it -type about 200 nm, the thickness of the buried silicon oxide is about 200-400 nm and the orientation of the substrate is (100). 5. The method according to claim 4, characterized in that, in order to form active transistor structures of the MOS VLSI heterostructure, a buffer oxide is grown on the SOI plate and a Si ₃ N ₄ layer is deposited, after which Active Areas photolithography is performed and the sides of the islands are acidified . 6. The method according to claim 5, characterized in that, in order to form the “STI” insulation in the VLSI heterostructure, a SiO ₂ layer is deposited by plasma chemical vapor deposition (“HDP”), compaction (annealing) is performed, then “Inversion of active” photolithography is performed areas ”to create insulation“ STI ”, perform chemical-mechanical polishing, then etch Si ₃ N ₄ in hot phosphoric acid and etch SiO ₂ , and then carry out the oxidation process to form a buffer oxide. 7. The method according to claim 6, characterized in that, in order to form an n-pocket in the VLSI heterostructure, perform a photocopying operation for the n-pocket and ion doping with phosphorus, and then the photoresist is removed. 8. The method according to claim 7, characterized in that, in order to form a p-pocket, a p-pocket photocopying operation is performed and ion doping with boron is performed, followed by plasmochemical removal of the photoresist. 9. The method according to claim 8, characterized in that, in order to form the polysilicon gates of the MOS transistors in the VLSI heterostructure, their formation is realized by removing buffer oxide, growing the gate oxide and depositing undoped Si with the subsequent performance of the Shutters photolithography operation. 10. The method according to claim 9, characterized in that, in order to form high-resistance n ^- stocks using ion-beam doping ("LDD") in the VLSI heterostructure, photocopying "n ^- stocks" and ion doping with phosphorus and arsenic is carried out . 11. The method according to claim 10, characterized in that, in order to form high-resistance p ^- sinks using "LDD" in the VLSI heterostructure, photocopying the "p ^- sinks" and ion doping using the BF ₂ compound are performed. 12. The method according to claim 11, characterized in that, in order to form interconnects (spacers) in the VLSI heterostructure, a layer of "silicon hydride-silicon dioxide"("Silane-SiO ₂ ") is deposited by the technology of chemical vapor deposition (" LPTEOS ”) and then react-ion etch the“ Silane-SiO ₂ + SiO ₂ ”layer. 13. The method according to p. 12, characterized in that, in order to form n ⁺ -stocks in the VLSI heterostructure, they perform oxidation followed by photocopying the “n ⁺ -stocks” and carry out ion doping with As ⁺ ions. 14. The method according to p ^. 13, characterized in that, in order to form p ⁺ -stocks in the VLSI heterostructure, photocopy the “p ⁺ -stocks” and perform ion doping with boron, which leads to doping of the gate of the p-channel transistor (p ⁺ polysilicon gate), then, using the technology of chemical vapor deposition from the gas phase, an “LPTEOS-SiO ₂ ” layer is formed, then annealing is performed and fast annealing is performed, which stimulates the diffusion of effluents. 15. The method according to 14, characterized in that, in order to form high-resistance resistances in the VLSI heterostructure, photolithography is performed to protect the region of these resistances and then react-ion etching of the SiO ₂ layer is carried out. 16. The method according to p. 15, characterized in that, in order to form a titanium silicide layer in the VLSI heterostructure, Ti is deposited and TiN is deposited, and two-stage heat treatment is used to obtain TiSi ₂ compound. 17. The method according to clause 16, characterized in that, in order to form contacts in the VLSI heterostructure, precipitate borophosphor glass ("BPTEOS-SiO ₂ "), fuse it with "SATEOS-SiO ₂ " followed by a chemical-mechanical polishing procedure, next, contacts are formed, for which the “Contacts” photocopying operation is carried out, then the thermal suppression process is carried out and reactive-ion etching of the SiO ₂ layer is carried out, then the Ti / TiN barrier layers are sprayed, the tungsten (W) is deposited and the chemical-mechanical polishing is carried out page W / TiN / Ti structures to SiO ₂ . 18. The method according to 17, characterized in that, in order to form the first metallization level in the VLSI heterostructure, the MET1 photocopy and the TiN / Ti / Al / Ti reactive-ion etching process are performed, then a thick inter-level dielectric PECVD- is deposited SiO ₂ ", melt it with" SATEOS-SiO ₂ "and carry out chemical-mechanical polishing of the layer" PECVD-SiO ₂ ". 19. The method according to p. 18, characterized in that, in order to form a VIA-1 bonding layer with metallization in the VLSI heterostructure, VIA-1 photocopying is performed, reactive-ion etching of SiO _{2 is} carried out over the entire thickness of the layer, then perform the process of deposition of Ti / TiN and deposition of W and chemical-mechanical polishing of the layer W / TiN / Ti to SiO ₂ . 20. The method according to claim 19, characterized in that, in order to form the second metallization level “MET2” in the VLSI heterostructure, Ti / Al / Ti / TiN is deposited, photocopying “MET2” is performed, and TiN / Ti is reactively ion etched / Al / Ti, then a thick inter-level dielectric PECVD-SiO ₂ is deposited, fused with SATEOS-SiO ₂ and chemically-mechanically polished with PECVD-SiO ₂ . 21. The method according to claim 20, characterized in that, in order to form a “VIA-2” layer bonding to metallization in the VLSI heterostructure, photocopying “VIA-2” is performed, reactive-ion etching of SiO _{2 is} carried out over the entire thickness of the layer, then sputtering Ti / TiN, deposition of W and carry out chemical-mechanical polishing of W / TiN / Ti to SiO ₂ . 22. The method according to item 21, wherein, in order to form a third metallization level in the VLSI heterostructure, Ti / Al / Ti / TiN is deposited, “MET3” photocopying is performed, and TiN / Ti / Al / is reactively ion etched Ti, then a thick inter-level dielectric “PECVD-SiO ₂ ” is deposited, it is fused with “SATEOS-SiO ₂ ” and chemical-mechanical polishing is carried out with “PECVD-SiO ₂ ”. 23. The method according to p. 22, characterized in that, in order to form a VIA-3 bonding layer with metallization in the VLSI heterostructure, photocopying of VIA-3 is performed, reactive-ion etching of SiO _{2 is} carried out over the entire thickness of the layer, then sputtering Ti / TiN, deposition of W and carry out chemical-mechanical polishing of W / TiN / Ti to SiO ₂ . 24. The method according to claim 3 or 23, characterized in that, in order to reduce the temperature effect on the subsequent process of forming the memory "MRAM" (with the transfer of spin torque "STT-MRAM"), this process is implemented between the third and fourth levels of metallization VLSI heterostructures of CMOS / SOI technology at low temperatures. 25. The method according to p. 24, characterized in that between the third and fourth metallization levels of the VLSI heterostructure, an MRAM memory is formed (with transmission of spin torque “STT-MRAM”), including a base electrode, a fixed magnetization ferromagnetic layer (“FS ") made of a ferromagnetic thin film structure disposed thereon a tunnel insulating layer (" IC ") formed of TaO _x, disposed on top of the" IP "remagnetizing free ferromagnetic layer (" MOP "), made of a ferromagnetic structure Double top ferromagnetic structure is provided with a conductive layer Au with access to the surface for contact with the control read / write buses, and the whole two-layer Au / Ta / Co / TaO _x / Co / Au ferromagnetic structure is placed in a dielectric matrix of Ta ₂ O _5. 26. The method according A.25, characterized in that, in order to pair the structures of CMOS / SOI and "MRAM", the overall manufacturing process of the memory "MRAM" (with the transfer of spin torque "STT-MRAM") is implemented after the formation of the third level of metallization VLSI heterostructures of CMOS / SOI technology by forming the next conductive sublayer on which the MRAM memory (with transmitting spin torque "STT-MRAM") is formed from a film multilayer ferromagnetic structure of Au / Ta / Co / TaO _x / Co / Au ion etching in an argon atmosphere in a complex combined mask using negative electron resist defining the particles, the dielectric layer is formed naturally by oxidation Ta thin film via inlet air into the chamber, then to ensure good contact of the upper magnetic layer of the particles coated with Au, and then the entire structure is covered by a dielectric layer Ta ₂ O ₅ and then they are removed from the tops of the ferromagnetic particles by explosion of the mask remaining after ion etching, the two-layer ferromagnetic cells are thus placed in the dielectric matrix, and the upper the cells are coated with Au to reach the surface. 27. The method according to p. 24, characterized in that between the third and fourth metallization levels of the VLSI heterostructure, an MRAM memory is formed (with transmission of spin torque "STT-MRAM") according to the Savchenko method, which includes a base electrode, a ferromagnetic layer with a fixed magnetization (“FS”), a free-magnetization ferromagnetic layer (“SS”), a dielectric tunnel layer, or an insulating layer (“IS”) made of Al ₂ O ₃ located between “SS” and “FS”, a two-layer ferromagnetic the structure on top is provided with a conductive layer of Au with Exit to the surface for making contact with the control read / write buses, and the whole two-layer ferromagnetic structure is placed in a matrix of dielectric Ta ₂ O _5, and the memory structure «MRAM» (with Spin Transfer Torque «STT-MRAM») is formed on the surface of the third metallization layer “MET3” of the planar heterostructure of the VLSI CMOS / SOI technology with an additional Au / Ta intermediate layer deposited on top of it, and to achieve the greatest magnetoresistive effect, the ferromagnetic layers “SS” and “FS” are based on many gosloynoy pinning structure "ferromagnetic-Ru-ferromagnetic layer" on top of the two-layered ferromagnetic structure is applied to the fourth metallization layer "MET4" and dielectric passivation coating. 28. The method according to item 27, wherein, in order to form the lower base conductive electrode, on the VLSI heterostructure CMOS / SOI technology with "STI" insulation, prior to the step "formation of the fourth metallization level + VIA3", a multilayer Au / Ta structure is deposited by magnetron sputtering. 29. The method according to p. 28, characterized in that, in order to form a ferromagnetic layer with a fixed magnetization ("FS"), the first antiferromagnetic layer (Pinning) is applied to the surface of the multilayer structure by magnetron sputtering, then a layer of ferromagnet is applied, then a layer of Ru and a layer of ferromagnet. 30. The method according to clause 29, wherein in order to form a tunneling layer of dielectric, an Al ₂ O ₃ dielectric _of optimum thickness is deposited onto the surface of the structure, allowing a current to pass through an element with a resistance of the order of 10 ⁵ Ω · μm ² . 31. The method according to p. 30, characterized in that, in order to form a ferromagnetic layer with free magnetization ("CC"), a layer of a ferromagnet is applied to the surface of the insulating layer ("IC"), then a layer of Ru and a layer of ferromagnet. 32. The method according to p. 31, characterized in that, in order to ensure contact with the control bus write / read on the surface of the ferromagnetic layer with free magnetization ("CC") is applied to the Au layer. 33. The method according to p. 32, characterized in that, in order to form multilayer magnetic cells, a photoresist is applied to the surface of the structure, including the surface of the upper layer of the Au structure, photocopying is performed using the "Cell" photo template and the photoconduct is thermally suppressed , then etching the multilayer ferromagnetic structure is performed and the photoresist is removed. 34. The method according to p. 33, characterized in that, in order to form the dielectric insulation of the storage cells, a Ta ₂ O ₅ dielectric layer is applied to the structure surface with a thickness equal to the thickness of the layers of the ferromagnetic cell, a thick photoresist layer is applied, and the process is performed to planarize the surface plasma-chemical etching of the photoresist and Ta ₂ O ₅ layers, in which the same etching rate of these materials is selected. 35. The method according to p. 26 or p. 34, characterized in that, in order to form the fourth metallization level, a Ti / Al layer is deposited, then “MET4” is photocopied and Ti / Al is removed to the oxide by reactive ion etching. 36. The method according to claim 35, characterized in that, in order to form a protective dielectric layer, a SATEOS-SiO ₂ layer is deposited and PECVD-57M is deposited, then passivation is photocopied and reactive-ion etching of the layers is performed PECVD-SiN "," SATEOS-SiO ₂ ".

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