CN112435983A - 金属内连线结构及其制作方法 - Google Patents

金属内连线结构及其制作方法 Download PDF

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CN112435983A
CN112435983A CN202011082669.1A CN202011082669A CN112435983A CN 112435983 A CN112435983 A CN 112435983A CN 202011082669 A CN202011082669 A CN 202011082669A CN 112435983 A CN112435983 A CN 112435983A
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metal interconnect
metal
thickness
interconnect structure
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CN112435983B (zh
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周逸豪
傅子豪
谢宗殷
张志圣
蔡世群
何坤展
林泱佐
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United Microelectronics Corp
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Abstract

本发明公开一种金属内连线结构及其制作方法，其中该金属内连线结构主要包含第一金属内连线设于一基底上的一金属间介电层内且第一金属内连线上表面切齐金属间介电层上表面、一第二金属内连线设于第一金属内连线上以及一遮盖层设于第一金属内连线以及第二金属内连线之间，其中遮盖层包含一导电层以及U形接触该第一金属内连线以及该第二金属内连线。

Description

金属内连线结构及其制作方法
本申请是中国发明专利申请(申请号：201810933058.X，申请日：2018年08月16日，发明名称：金属内连线结构及其制作方法)的分案申请。
技术领域
本发明涉及一种金属内连线结构，尤其是涉及一种具有不同厚度遮盖层的金属内连线结构。
背景技术
随着集成电路的集成度(integration)增加以及高性能的需求，低电阻的多重金属内连线(multilevel interconnects)的制作便逐渐成为许多半导体集成电路制作工艺所必须采用的方式。而铜双镶嵌(dual damascene)技术搭配低介电常数材料所构成的金属间介电层(inter-metal dielectric,IMD)是目前最受欢迎的金属内连线制作工艺组合，尤其针对高集成度、高速逻辑集成电路芯片制造以及0.18微米以下的深次微米(deep sub-micro)半导体制作工艺，铜金属双镶嵌内连线技术在集成电路制作工艺中已日益重要，而且势必将成为下一世代半导体制作工艺的标准内连线技术。
然而在现今铜金属双镶嵌内连线制作工艺中可能因蚀刻制作工艺的因素使接触洞导体(via conductor)底部靠近下方沟槽导体(trench conductor)的位置发生铜金属不连续(discontinuous)的情形，进而影响元件效能。因此如何改良方前金属内连线制作工艺以解决此问题即为现今一重要课题。
发明内容
本发明一实施例揭露一种制作金属内连线结构的方法。首先形成一第一金属内连线于一基底上的一第一金属间介电层内，然后形成一遮盖层于第一金属内连线上，形成一第二金属间介电层于遮盖层上，进行一第一蚀刻制作工艺去除部分第二金属间介电层以形成一开口，进行一等离子体处理制作工艺，再进行一第二蚀刻制作工艺去除部分遮盖层。
本发明另一实施例揭露一种金属内连线结构，其主要包含第一金属内连线设于一基底上的一金属间介电层内且第一金属内连线上表面切齐金属间介电层上表面、一第二金属内连线设于第一金属内连线上以及一遮盖层设于第一金属内连线以及第二金属内连线之间，其中遮盖层包含一导电层以及U形接触该第一金属内连线以及该第二金属内连线。
附图说明
图1至图5为本发明优选实施例制作一金属内连线结构的方法示意图；
图6为本发明一实施例的一金属内连线结构的结构示意图。
主要元件符号说明
12 基底 14 层间介电层
16 第一金属间介电层 18 金属内连线
20 阻障层 22 衬垫层
24 金属层 26 遮盖层
28 停止层 30 第二金属间介电层
32 图案化掩模 34 第一蚀刻制作工艺
36 开口 38 聚合物
40 等离子体处理制作工艺 42 第二蚀刻制作工艺
44 阶梯部 46 阻障层
48 衬垫层 50 金属层
52 金属内连线 54 气孔
T1 第一厚度 T2 第二厚度
T3 第三厚度 W1 第一宽度
W2 第二宽度 W3 第三宽度
具体实施方式
请参照图1至图5，图1至图5为本发明优选实施例制作一金属内连线结构的方法示意图。如图1所示，首先提供一基底12，例如一由半导体材料所构成的基底12，其中半导体材料可选自由硅、锗、硅锗复合物、硅碳化物(silicon carbide)、砷化镓(gallium arsenide)等所构成的群组。基底12上可包含例如金属氧化物半导体(metal-oxide semiconductor,MOS)晶体管等主动(有源)元件、被动(无源)元件、导电层以及例如层间介电层(interlayerdielectric,ILD)14等介电层覆盖于其上。更具体而言，基底12上可包含平面型或非平面型(如鳍状结构晶体管)等MOS晶体管元件，其中MOS晶体管可包含金属栅极以及源极/漏极区域、间隙壁、外延层、接触洞蚀刻停止层等晶体管元件，层间介电层较可设于基底12上并覆盖MOS晶体管，且层间介电层可具有多个接触插塞电连接MOS晶体管的栅极以及/或源极/漏极区域。由于平面型或非平面型晶体管以及层间介电层等相关制作工艺均为本领域所熟知技术，在此不另加赘述。
然后在层间介电层14上依序形成金属内连线结构电连接前述的接触插塞，其中金属内连线结构较佳包含一选择性停止层(图未示)设于层间介电层14上、一第一金属间介电层16以及至少一金属内连线18镶嵌于第一金属间介电层16内，且各金属内连线18上表面较佳切齐第一金属间介电层16上表面。需注意的是，本实施例虽仅在第一金属间介电层16内形成单一金属内连线18为例，但所设置的金属内连线18数量并不局限于此，而可视制作工艺需求调整。
其次金属内连线结构中的金属内连线18虽较佳由单一沟槽导体(trenchconductor)所构成，但不局限于此，依据本发明其他实施利各金属内连线18又可包含沟槽导体、接触洞导体(via conductor)、或其组合，且各金属内连线18均较佳依据双镶嵌制作工艺镶嵌于第一金属间介电层16以及/或停止层内并彼此电连接。由于双镶嵌制作工艺是本领域所熟知技术，在此不另加赘述。从结构来看，金属内连线18较佳包含一阻障层20、一衬垫层22设于阻障层20上以及一金属层24设于衬垫层22上，其中阻障层20以及衬垫层22较佳为U形且三者上表面均较佳切齐第一金属间介电层16上表面。从材料来看阻障层20较佳包含氮化钽(tantalum nitride,TaN)，衬垫层22较佳包含钴(cobalt,Co)，金属层24则较佳包含铜，第一金属间介电层16较佳包含氧化硅，而停止层则包含氮化硅，但均不局限于此。
接着形成一遮盖层26并覆盖于第一金属间介电层16与金属内连线18表面，
然后进行一光刻曁蚀刻制作工艺去除位于第一金属间介电层16上的部分遮盖层26，使剩余的遮盖层26覆盖于金属内连线18表面且遮盖层26边缘较佳切齐金属内连线18边缘并再次暴露出两旁的第一金属间介电层16上表面。在本实施例中，遮盖层26较佳与金属内连线18中的衬垫层22包含相同材料，例如两者均包含由钴所构成的导电或金属材料。随后依序形成一停止层28以及一第二金属间介电层30于遮盖层26上，其中停止层28较佳共形地覆盖于第一金属间介电层16上表面以及遮盖层26上表面与侧壁，而第二金属间介电层30则完全覆盖于停止层28上。在本实施例中，停止层28可包含例如氮化硅所构成的介电材料，第二金属间介电层30与第一金属间介电层16可包含相同材料，例如两者均可由氧化硅所构成。
如图2所示，然后先形成一图案化掩模32于第二金属间介电层30表面，再进行一第一蚀刻制作工艺34依序去除部分第二金属间介电层30以及部分停止层28以形成一开口36。在本实施例中，图案化掩模32可包含由图案化光致抗蚀剂所构成的单层结构，或可包含由一有机介电层(organic dielectric layer,ODL)、一含硅硬掩模与抗反射(silicon-containing hard mask bottom anti-reflective coating,SHB)层以及一图案化光致抗蚀剂所构成的三层结构，其中于图案化掩模32中形成开口36的步骤可利用图案化光致抗蚀剂为掩模去除部分含硅硬掩模与抗反射层与部分有机介电层来达成。
另外本阶段所进行的第一蚀刻制作工艺34较佳包含一干蚀刻制作工艺，其较佳利用含氟气体，例如四氟化碳(CF4)来去除部分第二金属间介电层30以及部分停止层28并暴露出遮盖层26表面形成开口36。需注意的是，本阶段利用第一蚀刻制作工艺34或干蚀刻制作工艺去除部分第二金属间介电层30形成开口36并暴露出遮盖层26顶部的时候可能使部分由钴所构成的遮盖层26产生氧化，进而形成由氧化钴(cobalt oxide,CoO)或含氟所构成的聚合物38堆积在开口36底部，特别是开口36底部位于停止层28及遮盖层26所接触的角落。
如图3所示，接着进行一等离子体处理制作工艺40去除开口36内经由第一蚀刻制作工艺34时所产生的聚合物38。更具体而言，本阶段所进行的等离子体处理制作工艺40较佳利用例如由氢气以及/或氮气所构成的气体或气体组合降低堆积于开口36底部的聚合物38含量，使后续遮盖层26的厚度不致因此降低。需注意的是，在理想状况下本阶段所进行的等离子体处理制作工艺40虽较佳去除大部分的聚合物38，但实际上在等离子体处理制作工艺40结束后可能仍有一小部分的聚合物38残留在开口36底部的角落处。在本实施例中，等离子体处理制作工艺40所使用的氮气流量较佳约略50每分钟标准毫升(standard cubiccentimeter per minute,sccm)而氢气流量约略100每分钟标准毫升。
随后如图4所示，进行一第二蚀刻制作工艺42再次去除堆积于开口36底部，特别是完全去除开口36底部角落所残留的聚合物38。在本实施例中，第二蚀刻制作工艺42较佳包含一湿蚀刻制作工艺，其较佳在旋转基底12或半导体晶片的情况下利用包含例如过氧化氢(hydrogen peroxide,H2O2)的蚀刻剂来去除堆积于开口36底部角落处的聚合物38，其中第二蚀刻制作工艺42或湿蚀刻制作工艺进行时的用来承载基底12或半导体晶片的吸盘(chuck)转速较佳介于每分钟200至2000转(rpm)，而蚀刻剂如过氧化氢的流量(flow rate)则较佳介于每分钟0.5至2.0公升。
值得注意的是，本实施例利用第二蚀刻制作工艺42去除剩余聚合物38的时候较佳同时去除开口36正下方的部分遮盖层26但不暴露出遮盖层26下方的金属内连线18，使开口36正下方的剩余遮盖层26上表面略低于两侧的遮盖层26上表面。此外又需注意的是，本实施例利用第二蚀刻制作工艺42去除开口36正下方部分遮盖层26的时候可能因扩散效应(diffusion effect)又同时去除开口36两侧的一小部分遮盖层26而形成阶梯部44。
从细部来看，本实施例进行完第二蚀刻制作工艺42后覆盖于金属内连线18表面的剩余遮盖层26较佳包含三种厚度，其中开口36正下方的遮盖层26包含第一厚度T1，第一厚度T1两侧受到前述蚀刻剂扩散影响的部分遮盖层26包含第二厚度T2，而第二厚度T2两侧直到切齐金属内连线18边缘的遮盖层26则包含第三厚度T3，其中第一厚度T1较佳小于第二厚度T2且第二厚度T2又较佳小于第三厚度T3。
在本实施例中，第一厚度T1较佳介于8～25埃，第二厚度T2较佳介于15～50埃，第三厚度T3则较佳介于20～100埃。另外从宽度范围来看第一厚度T1由左侧至右侧较佳包含一第一宽度W1，第二厚度T2由左侧至右侧包含一第二宽度W2，而第三厚度T3由左侧至右侧或整个金属内连线宽度18则包含一第三宽度W3，其中第一宽度W1较佳约34纳米，第二宽度W2较佳约68纳米，而第三宽度W3则较佳大于100纳米。
需注意的是，本实施例虽较佳于前述图2进行第一蚀刻制作工艺34或干蚀刻制作工艺时不去除任何遮盖层26直到图4的第二蚀刻制作工艺42才去除部分遮盖层26，但不局限于此，依据本发明一实施例又可选择在第一蚀刻制作工艺34去除部分第二金属间介电层30与部分停止层28形成开口36的时候同时去除部分遮盖层26，使开口36正下方的遮盖层26略低于两侧遮盖层26形成阶梯部44。之后再依序进行图3的等离子体处理制作工艺40以及图4的第二蚀刻制作工艺42或湿蚀刻制作工艺以形成如图4中所示具有三种厚度的遮盖层26，此变化型也属本发明所涵盖的范围。
如图5所示，随后去除图案化掩模32，再依序形成一阻障层46于开口36内，形成一衬垫层48于阻障层46上以及形成一金属层50于衬垫层48上并填满开口36，接着进行一平坦化制作工艺，例如利用化学机械研磨(chemical mechanical polishing,CMP)制作工艺去除部分金属层50、部分衬垫层48以及部分阻障层46以形成另一金属内连线52或更具体而言一接触洞导体。如同下方金属内连线18或沟槽导体的组成，阻障层46较佳包含氮化钽(tantalum nitride,TaN)，衬垫层48较佳包含钴(cobalt,Co)，金属层50则较佳包含铜，但均不局限于此。至此即完成本发明一实施例的一金属内连线结构的制作。
请再参照图5，图5又揭露本发明一实施例的一半导体元件的结构示意图。如图5所示，半导体元件主要包含金属内连线18设于第一金属间介电层16内，另一金属内连线52设于金属内连线18上方，一遮盖层26设于金属内连线18表面并直接接触金属内连线18、52，一停止层28覆盖并接触第一金属间介电层16与遮盖层26上表面以及一第二金属间介电层30设于停止层28上并环绕金属内连线52。
从细部来看遮盖层26包含一第一厚度T1位于金属内连线18以及金属内连线52之间、一第二厚度T2位于第一厚度T2两侧以及一第三厚度T3位于第二厚度T2两侧，其中第一厚度T1较佳小于第二厚度T2且第二厚度T2又较佳小于第三厚度T3。从材料面来看遮盖层26以及金属内连线18、52中的衬垫层22、48较佳包含相同材料，例如三者均包含由钴所构成的导电或金属材料，停止层28则可由氮化硅或氮碳化硅等介电材料所构成。
请参照图6，图6为本发明一实施例的一金属内连线结构的结构示意图。如图6所示，本发明于图4去除部分遮盖层26至图5填入阻障层46、衬垫层48以及金属层50形成金属内连线52时又可依据制作工艺需求调整制作工艺参数以于金属内连线52两侧的遮盖层26内形成分别形成气孔54。从结构上来看，各气孔54较佳由遮盖层26、阻障层46以及停止层28所环绕。另需注意的是，本实施例的气孔54上表面虽约略切齐遮盖层26上表面，但不局限于此，依据本发明其他实施例气孔54上表面又可选择略高或略低于遮盖层26上表面，这些变化型均属本发明所涵盖的范围。
一般而言，现有金属内连线制作工艺中利用蚀刻去除金属间介电层形成金属内连线开口时通常因蚀刻过程无法精准控制会将金属内连线顶部由钴所构成的遮盖层一同去除，进而形成不连续的遮盖层并使后续所填入的导电材料直接接触下层的金属内连线，其中不连续的遮盖层有可能影响整批元件的可靠性(reliability)并产生电迁移(electrical migration)现象。为了解决此问题本发明较佳先进行第一蚀刻制作工艺或干蚀刻制作工艺去除部分金属间介电层形成开口，接着利用等离子体处理制作工艺去除大部分堆积于开口底部角落的聚合物，然后进行第二蚀刻制作工艺或湿蚀刻制作工艺并同时调整蚀刻的转速与所通入的蚀刻剂流量，在不蚀刻穿遮盖层的情况下去除剩余的聚合物，最后再填入导电材料于开口内直接接触遮盖层并形成金属内连线。依据本发明的优选实施例，覆盖于下层金属内连线表面的剩余遮盖层在结构上较佳在蚀刻过程中形成不同高低厚度，或从另一角度来看产生一个以上阶梯部，但整体而言仍为一连续的遮盖层覆盖于金属内连线表面。如此即可提升元件的整体可靠度并降低元件失效(failure)的机率。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (10)

1.一种金属内连线结构，其特征在于，包含：
第一金属内连线，设于基底上的金属间介电层内，其中该第一金属内连线上表面切齐该金属间介电层上表面；
第二金属内连线，设于该第一金属内连线上；以及
遮盖层，设于该第一金属内连线以及该第二金属内连线之间，其中该遮盖层包含导电层以及U形接触该第一金属内连线以及该第二金属内连线。
2.如权利要求1所述的金属内连线结构，其中该遮盖层包含第一厚度于该第一金属内连线以及该第二金属内连线之间以及第二厚度于该第一厚度两侧。
3.如权利要求2所述的金属内连线结构，其中该第二厚度大于该第一厚度。
4.如权利要求2所述的金属内连线结构，其中该遮盖层包含第三厚度位于该第二厚度两侧。
5.如权利要求4所述的金属内连线结构，其中该第三厚度大于该第二厚度。
6.如权利要求1所述的金属内连线结构，其中该第二金属内连线包含：
阻障层，接触该遮盖层；
衬垫层，设于该阻障层上；以及
金属层，设于该衬垫层上。
7.如权利要求6所述的金属内连线结构，其中该阻障层以及该衬垫层为U形。
8.如权利要求6所述的金属内连线结构，其中该遮盖层以及该衬垫层包含相同材料。
9.如权利要求6所述的金属内连线结构，其中该遮盖层以及该衬垫层包含钴。
10.如权利要求1所述的金属内连线结构，另包含气孔，设于该遮盖层内。
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CN116314012A (zh) 2023-06-23
US11450558B2 (en) 2022-09-20
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US20200373198A1 (en) 2020-11-26
CN112435983B (zh) 2023-12-19

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