CN112433981A - Miniaturized software radio platform for high-speed intelligent signal processing - Google Patents
Miniaturized software radio platform for high-speed intelligent signal processing Download PDFInfo
- Publication number
- CN112433981A CN112433981A CN202011315929.5A CN202011315929A CN112433981A CN 112433981 A CN112433981 A CN 112433981A CN 202011315929 A CN202011315929 A CN 202011315929A CN 112433981 A CN112433981 A CN 112433981A
- Authority
- CN
- China
- Prior art keywords
- zynq
- processing board
- acquisition
- platform
- linux
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
- G06F15/7817—Specially adapted for signal processing, e.g. Harvard architectures
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N3/00—Computing arrangements based on biological models
- G06N3/02—Neural networks
- G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
- G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Biophysics (AREA)
- Health & Medical Sciences (AREA)
- Life Sciences & Earth Sciences (AREA)
- Software Systems (AREA)
- Mathematical Physics (AREA)
- Biomedical Technology (AREA)
- Computing Systems (AREA)
- Molecular Biology (AREA)
- Neurology (AREA)
- General Health & Medical Sciences (AREA)
- Evolutionary Computation (AREA)
- Data Mining & Analysis (AREA)
- Computational Linguistics (AREA)
- Artificial Intelligence (AREA)
- Signal Processing (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Transceivers (AREA)
Abstract
The invention provides a miniaturized software radio platform for high-speed intelligent signal processing. The platform comprises a physical layer and a hardware abstraction layer, wherein the physical layer comprises: the device comprises a ZYNQ acquisition processing board, a DSP processing board, an AD/DA daughter card and an external DDR4 memory; a RapidIO2.0 protocol is adopted between the ZYNQ acquisition processing board and the DSP processing board; a JESD204B bus protocol is adopted between the ZYNQ acquisition and processing board and the AD/DA daughter card; the ZYNQ acquisition processing board comprises a plurality of on-chip computing units and a DDR4 memory, wherein each on-chip computing unit comprises a deep learning accelerator, and data interaction is carried out between each deep learning accelerator and the DDR4 memory through hardware DMA. The invention integrates a deep learning accelerator, high-speed transmission and high-speed acquisition of AD/DA, and meets the application requirements of intellectualization and miniaturization on the premise of controlling the cost.
Description
Technical Field
The invention relates to the technical field of wireless communication, in particular to a miniaturized software radio platform for high-speed intelligent signal processing.
Background
With the rapid development of wireless communication technology, the traditional single-system communication mode can not meet the modern communication requirements for a long time. The development of software radio brings a wireless communication solution which is more flexible, lower in cost and free from the restriction of hardware, so that the wireless communication platform achieves the purposes of self-adaption and expandability. But the universality scale of the platform causes the appearance of power consumption and cost problems, in recent years, many theoretical verifications have been carried out on the aspects of traditional signal processing in machine learning and deep learning, but a reconfigurable, flexible and extensible special DSP which can meet the requirements of the software radio field does not appear in the market.
As is known, one of the purposes of software radio is to simplify the design of the radio frequency front end and make the AD/DA as close as possible to the antenna, so that the advantage of this is that the radio signal can be converted into a digital signal as early as possible, and the subsequent digital signal processing is performed by software to meet various functional indexes, so that the hardware platform has better universality and usability. However, the high sampling rate AD/DA also causes cost increase, and generally, the rf analog signal can be sampled in two ways, namely low-pass sampling and band-pass sampling based on nyquist sampling theorem, where the band-pass sampling can be divided into rf direct band-pass sampling and wideband if band-pass sampling, and thus, the architecture of the software defined radio mainly has three architectures: short-wave direct radio frequency low-pass sampling architecture shown in fig. 1, radio frequency direct band-pass sampling architecture shown in fig. 2, and broadband intermediate frequency band-pass sampling architecture shown in fig. 3.
Currently, there is also a popular zero if architecture, as shown in fig. 4. The zero-if architecture, which is adopted by devices in series such as AD9361, AD9364, AD9371, for a receiver, has the greatest benefit of reducing the bandwidth requirement of the AD by half, and the mixer directly shifts the signal to the zero frequency. The AD9364 of a zero intermediate frequency architecture is mainly adopted in the design and implementation of a small-sized low-power-consumption software radio platform in the literature [ D ].2018 ]. However, inherent disadvantages of the zero-if architecture are also apparent, such as dc offset due to limited demodulator isolation, IQ mismatch due to imbalance of the demodulator with the AD; even order distortion caused by device non-linearity. Although the zero if has been used in the terminal for many years, in the base station field, an extremely demanding SNR performance is required, and the zero if technology is commercially available from only a few manufacturers. Solving these problems requires algorithm support while requiring better performing device support.
With the rapid development of digital signal processing chips, software radio technology has also been rapidly developed, but software radio platforms are generally designed to be bulky due to compatibility considerations, and thus the use of software radio platforms is limited in harsh environments.
Disclosure of Invention
Aiming at the problem of large volume of the existing software radio platform, the invention provides a miniaturized software radio platform for high-speed intelligent signal processing by relying on the software radio thought under the condition of not reducing the universality and the real-time property of the platform.
The invention provides a miniaturized software radio platform oriented to high-speed intelligent signal processing, which comprises a physical layer and a hardware abstraction layer, and is characterized in that the physical layer comprises: the device comprises a ZYNQ acquisition processing board, a DSP processing board, an AD/DA daughter card and an external DDR4 memory;
a RapidIO2.0 protocol is adopted between the ZYNQ acquisition processing board and the DSP processing board; a JESD204B bus protocol is adopted between the ZYNQ acquisition and processing board and the AD/DA daughter card;
the ZYNQ acquisition processing board comprises a plurality of on-chip computing units and a DDR4 memory, wherein each on-chip computing unit comprises a deep learning accelerator, and data interaction is carried out between each deep learning accelerator and the DDR4 memory through hardware DMA.
Further, the ZYNQ acquisition processing board and the external DDR4 memory are connected through an MIG interface.
Further, the AD/DA daughter card employs DAQ 2.
Further, the on-chip computing unit further includes: the system comprises a multi-rate conversion module and a digital signal processing algorithm accelerator module; the multi-rate conversion module and the digital signal processing algorithm accelerator module both adopt a multi-core and multiplexing parallel operation architecture.
Further, the AD/DA daughter card is connected to a DDR4 memory through the multi-rate conversion module.
Further, the hardware abstraction layer includes: a Linux/Windows host and software deployed on the ZYNQ acquisition and processing board; the ZYNQ acquisition and processing plate is divided into a PS end and a PL end;
a Linux system is loaded at the PS end of the ZYNQ acquisition and processing board; a Libiio TCP/IP server program is deployed on the Linux system; a Libiio TCP/IP client program is deployed on the Linux/Windows host;
and the Linux/Windows host and the ZYNQ acquisition and processing board perform data interaction through a Libiio TCP/IP server program and a Libiio TCP/IP client program.
Further, Linux DMA API is adopted for data interaction between the PS end and the PL end of the ZYNQ acquisition and processing board.
Further, the Linux/Windows host end and the PS end of the ZYNQ acquisition and processing board adopt ADI IIO frames.
Furthermore, a gigabit Ethernet RJ45 interface for remotely connecting the Linux/Windows host is also arranged at the PS end of the ZYNQ acquisition and processing board.
Furthermore, a vitas AI compiling framework is deployed at the Linux/Windows host end and the PS end of the ZYNQ acquisition and processing board.
The invention has the beneficial effects that:
(1) the invention adopts the XilinxZYNQ series chip with higher monolithic system integration level, thereby meeting the miniaturization requirement; and different from the existing software radio platform based on ZYNQ, the invention integrates a deep learning accelerator, high-speed transmission and high-speed acquisition AD/DA, and meets the application requirements of intellectualization and miniaturization on the premise of controlling the cost.
(2) By adopting the high-sampling-rate AD/DA daughter card, higher signal bandwidth is met as much as possible, the radio frequency bandwidth is expanded, and meanwhile, a multi-rate conversion module and a high-speed serial embedded bus Rapidio2.0 protocol are realized on the FPGA, so that the transmission bandwidth requirements of various high-speed signal processing tasks are met.
(3) The Linux which is an open source operating system is transplanted at the ARM end, and the development and the transplantation of a software radio framework are greatly facilitated due to the flexibility and the usability of the Linux.
(4) In consideration of edge machine learning inference application for comparing consumed computing resources with storage bandwidth, a deep learning accelerator DPU is introduced to an FPGA side in a platform to meet real-time intelligent processing tasks of signals, and an upper compiling tool is matched to conveniently transplant a new deep learning algorithm to meet the requirements of new-generation edge intelligent application;
(5) the invention redesigns a software radio framework facing intelligent signal processing, and introduces a vitas AI compiling framework to improve the platform usability to the maximum extent.
Drawings
Fig. 1 is a schematic diagram of a short-wave direct radio frequency low-pass sampling architecture provided in the prior art;
fig. 2 is a radio frequency direct bandpass sampling architecture provided by the prior art;
fig. 3 is a broadband if bandpass sampling architecture provided by the prior art;
FIG. 4 is a zero IF architecture provided by the prior art;
FIG. 5 is a schematic diagram of a hardware abstraction layer architecture of a miniaturized software radio station oriented to high-speed intelligent signal processing according to an embodiment of the present invention
Fig. 6 is a schematic diagram of a hardware abstraction layer architecture of a high-speed intelligent signal processing-oriented miniaturized software radio station according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly described below with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Example 1
As shown in fig. 1, an embodiment of the present invention provides a miniaturized software radio platform for high-speed intelligent signal processing, including a physical layer and a hardware abstraction layer, where the physical layer includes: the device comprises a ZYNQ acquisition processing board, a DSP processing board, an AD/DA daughter card and an external DDR4 memory;
a RapidIO2.0 protocol is adopted between the ZYNQ acquisition processing board and the DSP processing board; a JESD204B bus protocol is adopted between the ZYNQ acquisition and processing board and the AD/DA daughter card; the ZYNQ acquisition processing board is connected with the external DDR4 memory through an MIG interface;
the ZYNQ acquisition processing board comprises a plurality of on-chip computing units and a DDR4 memory, wherein each on-chip computing unit comprises a deep learning accelerator (DPU), and data interaction is carried out between each deep learning accelerator and the DDR4 memory through hardware DMA.
As an implementation, the on-chip computing unit further includes: the system comprises a multi-rate conversion module and a digital signal processing algorithm accelerator module; the multi-rate conversion module and the digital signal processing algorithm accelerator module both adopt a multi-core and multiplexing parallel operation architecture.
As one possible implementation, the AD/DA daughter card is connected to DDR4 memory through the multi-rate conversion module.
As one possible implementation, the AD/DA daughter card employs a high sampling rate DAQ 2; the DAQ2 AD highest sampling rate is 1Gsps, the DA conversion rate is 2.8Gsps, the sampling bandwidth is larger by using the device, data of more frequency bands can be obtained at one time, and the post-stage parallel processing can be facilitated.
The software radio platform needs to consider real-time performance, which comprises two aspects of throughput and time delay. In the aspect of improving the real-time performance, compared with the prior art, the embodiment of the invention mainly makes 4 improvements:
(1) the deep learning accelerator and the DDR are mutually transmitted by adopting a hardware DMA, so that the bandwidth in a chip can be greatly improved, the throughput is improved, and the delay is reduced.
(2) The embedded high-speed transmission interface Rapidio2.0 protocol is adopted for transmission between the ZYNQ acquisition processing board and the DSP processing board, so that the external data transmission bandwidth cannot become a bottleneck when the application realizes real-time performance.
(3) The multi-rate conversion module, the digital signal processing algorithm accelerator module and the like adopt a multi-core and multiplexing parallel operation architecture, and the throughput can be improved.
(4) Interaction of a ZYNQ acquisition and processing board (FPGA part) and an AD/DA daughter card adopts a JESD204B bus protocol to carry out high-speed real-time transmission, and one frame of data is not lost while the real-time performance is ensured; in addition, by adding the multi-rate conversion module after the AD/DA daughter card with a high sampling rate, the processing load of the post stage can be avoided from being too large.
From the above, it can be seen that, unlike the existing ZYNQ-based software radio platform, the software radio platform provided by the embodiment of the present invention integrates a deep learning accelerator, high-speed transmission, and high-speed acquisition of AD/DA, and meets the application requirements of intellectualization and miniaturization on the premise of controlling cost.
Example 2
On the basis of the above embodiment 1, the present invention further provides a miniaturized software radio platform oriented to high-speed intelligent signal processing, where a hardware abstraction layer of the platform includes: a Linux/Windows host and software deployed on the ZYNQ acquisition and processing board; the ZYNQ acquisition and processing plate is divided into a PS end and a PL end;
a Linux system is loaded at the PS end of the ZYNQ acquisition and processing board; a Libiio TCP/IP server program is deployed on the Linux system; a Libiio TCP/IP client program is deployed on the Linux/Windows host;
and the Linux/Windows host and the ZYNQ acquisition and processing board perform data interaction through a Libiio TCP/IP server program and a Libiio TCP/IP client program.
As an implementation manner, data interaction between the PS end and the PL end of the ZYNQ acquisition and processing board employs a Linux DMA API.
As an implementation mode, the Linux/Windows host machine end and the PS end of the ZYNQ acquisition and processing board adopt ADI IIO frames.
As an implementation manner, a gigabit ethernet RJ45 interface for remotely connecting the Linux/Windows host is further disposed at the PS end of the ZYNQ acquisition and processing board.
As an implementation manner, a vitas AI compilation framework is also deployed at the Linux/Windows host end and the PS end of the ZYNQ collection processing board.
On the basis of meeting the real-time performance, the software radio platform also needs to consider usability. The software radio platform provided by the embodiment of the invention innovatively adds an intelligent application interface in a hardware abstraction layer while taking the advantages of the traditional software radio platform into consideration.
The hardware abstraction layer of the platform provided by the embodiment of the invention is divided into a Linux/Windows host part and a ZYNQ acquisition and processing board part, the ZYNQ acquisition and processing board part is divided into a PS end and a PL end, and the platform can conveniently interact with the Linux/Windows host part by loading a Linux system at the PS end (namely an ARM side) of the ZYNQ acquisition and processing board. The PL end (namely the FPGA side) of the ZYNQ acquisition and processing board is mainly responsible for realizing a hardware driving logic and an algorithm acceleration hardware module.
By using an ADI IIO frame at a Linux/Windows host end and a PS end of a ZYNQ acquisition processing board, the complex AD/DA hardware driver at the bottom layer is isolated from the upper application, and AD acquisition data of the hardware at the bottom layer can be conveniently called; the data acquisition process is simplified by using Python, C + +, and C API, and parameters such as sampling rate, point number, mixing frequency and the like can be conveniently modified; the RJ45 interface of the gigabit Ethernet at the PS end of the ZYNQ acquisition and processing board can be remotely connected with a Linux/Windows host, and the interface has a good interactive interface, so that a user can remotely call data at the Linux/Windows host side and can directly call the data on the ZYNQ acquisition and processing board.
Meanwhile, the platform provided by the embodiment of the invention can also be accessed to a Matlab/Simulink interface of a Linux/Windows host, so that the ZYNQ hardware platform is abstracted into a Simulink module, and the algorithm prototype development can be rapidly carried out.
The data interactive transmission part of the middle PS end and the PL end of the ZYNQ acquisition and processing board uses the packaged Linux DMA control API, so that the user can call the data conveniently, the data transmission between the ZYNQ acquisition and processing board and other embedded boards (such as a DSP processing board) is transmitted through the FPGA side Rapidio2.0 module, and the user only needs to operate the DMA API.
A user can use mainstream deep learning frameworks such as Tensorflow, Pythrch and the like to develop a neural network on a Linux/Windows host; the vitas AI compilation frame is respectively deployed at a Linux/Windows host end and a PS end of the ZYNQ acquisition and processing board, and the deep learning accelerator (DPU) is deployed at the FPGA side, so that a user can conveniently and quickly perform network optimization compilation (compilation is divided into steps of quantization, cutting and the like), and the like, and then the user can conveniently use the vitas AI compilation frame to perform deployment verification. The vitas AI compiling framework is provided with a corresponding deep learning operation API which can be called quickly, and the user hardware can accelerate the IP to accelerate the deep learning application conveniently.
Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (10)
1. A miniaturized software radio platform oriented to high-speed intelligent signal processing, comprising a physical layer and a hardware abstraction layer, wherein the physical layer comprises: the device comprises a ZYNQ acquisition processing board, a DSP processing board, an AD/DA daughter card and an external DDR4 memory;
a RapidIO2.0 protocol is adopted between the ZYNQ acquisition processing board and the DSP processing board; a JESD204B bus protocol is adopted between the ZYNQ acquisition and processing board and the AD/DA daughter card;
the ZYNQ acquisition processing board comprises a plurality of on-chip computing units and a DDR4 memory, wherein each on-chip computing unit comprises a deep learning accelerator, and data interaction is carried out between each deep learning accelerator and the DDR4 memory through hardware DMA.
2. The platform of claim 1, wherein a MIG interface is used between the ZYNQ acquisition processing board and the external DDR4 memory.
3. The platform of claim 1, wherein the AD/DA daughter card employs DAQ 2.
4. The platform of claim 1, wherein the on-chip computing unit further comprises: the system comprises a multi-rate conversion module and a digital signal processing algorithm accelerator module; the multi-rate conversion module and the digital signal processing algorithm accelerator module both adopt a multi-core and multiplexing parallel operation architecture.
5. The platform of claim 4, wherein the AD/DA daughter card is connected to DDR4 memory through the multi-rate conversion module.
6. The platform of any of claims 1 to 5, wherein the hardware abstraction layer comprises: a Linux/Windows host and software deployed on the ZYNQ acquisition and processing board; the ZYNQ acquisition and processing plate is divided into a PS end and a PL end;
a Linux system is loaded at the PS end of the ZYNQ acquisition and processing board; a Libiio TCP/IP server program is deployed on the Linux system; a Libiio TCP/IP client program is deployed on the Linux/Windows host;
and the Linux/Windows host and the ZYNQ acquisition and processing board perform data interaction through a Libiio TCP/IP server program and a Libiio TCP/IP client program.
7. The platform of claim 6, wherein data interaction between the PS side and the PL side of the ZYNQ acquisition and processing board employs a Linux DMA API.
8. The platform of claim 6, wherein the Linux/Windows host side and the PS side of the ZYNQ collection and processing board employ ADI IIO framework.
9. The platform of claim 6, wherein a gigabit Ethernet RJ45 interface for remotely connecting the Linux/Windows host is further provided at the PS end of the ZYNQ acquisition and processing board.
10. The platform of claim 6, wherein a vitas AI compilation framework is further deployed at the Linux/Windows host side and the PS side of the ZYNQ collection processing board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011315929.5A CN112433981A (en) | 2020-11-22 | 2020-11-22 | Miniaturized software radio platform for high-speed intelligent signal processing |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011315929.5A CN112433981A (en) | 2020-11-22 | 2020-11-22 | Miniaturized software radio platform for high-speed intelligent signal processing |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN112433981A true CN112433981A (en) | 2021-03-02 |
Family
ID=74693371
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011315929.5A Pending CN112433981A (en) | 2020-11-22 | 2020-11-22 | Miniaturized software radio platform for high-speed intelligent signal processing |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112433981A (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106228238A (en) * | 2016-07-27 | 2016-12-14 | 中国科学技术大学苏州研究院 | The method and system of degree of depth learning algorithm is accelerated on field programmable gate array platform |
-
2020
- 2020-11-22 CN CN202011315929.5A patent/CN112433981A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106228238A (en) * | 2016-07-27 | 2016-12-14 | 中国科学技术大学苏州研究院 | The method and system of degree of depth learning algorithm is accelerated on field programmable gate array platform |
Non-Patent Citations (4)
| Title |
|---|
| 余成宇等: "一种高效的稀疏卷积神经网络加速器的设计与实现", 智能系统学报 * |
| 和爽等: "基于JESD204B的射频信号高速采集系统设计", 电子器件 * |
| 蔡恒雨等: "基于RapidIO的多DSP互联仿真实现", 计算机系统应用 * |
| 赵莉等: "基于ZYNQ和AD9361的软件无线电平台设计与实现", 移动通信 * |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US20120044927A1 (en) | Radio channel aggregation and segmentation | |
| CN108491157A (en) | A kind of general signal processing platform | |
| CN101882953B (en) | Baseband signal processing device and method of multiple-mold communication system | |
| CN104242981B (en) | A kind of embedded communication device based on software radio | |
| CN110855996A (en) | Image coding and decoding and network transmission method and device based on FPGA | |
| Putra et al. | System-on-chip architecture for high-speed data acquisition in visible light communication system | |
| CN108490803A (en) | A kind of test emulation system | |
| CN101894086A (en) | Serial hub and multi-serial high-speed communication method | |
| CN110620599B (en) | Microminiature unmanned aerial vehicle data link terminal equipment | |
| CN201699992U (en) | System sharing base station bandwidth by wireless access point | |
| CN112433981A (en) | Miniaturized software radio platform for high-speed intelligent signal processing | |
| CN201893784U (en) | Digital radiofrequency remote system based on network cable transmission | |
| CN104639474A (en) | Ultra-wideband analog base band processing unit for millimeter-wave communication system | |
| CN209281395U (en) | A kind of restructural signal processing platform of wide frequency ranges | |
| CN208477509U (en) | A kind of general signal processing platform | |
| CN203722645U (en) | Radio monitoring receiving system based on ARM technology | |
| CN201796361U (en) | Serial interface hub | |
| CN112468162B (en) | Dual-generation tera-network intermediate-frequency signal processor, dual-path system and data transmission method | |
| CN103152111A (en) | Software radio test platform based on universal serial bus (USB) interface | |
| CN201048369Y (en) | Digital signal processor | |
| CN114422410A (en) | Multi-channel signal processing device and method | |
| CN202551015U (en) | Intermediate frequency digital processing board with parallel interfaces | |
| CN109257805B (en) | Extensible low-power-consumption multi-service transceiver system | |
| Tachwali et al. | Adaptability and configurability in cognitive radio design on small form factor software radio platform | |
| CN203368730U (en) | High fidelity 5.1 channel wireless audio system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |