CN209281395U - A kind of restructural signal processing platform of wide frequency ranges - Google Patents
A kind of restructural signal processing platform of wide frequency ranges Download PDFInfo
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- CN209281395U CN209281395U CN201920277131.2U CN201920277131U CN209281395U CN 209281395 U CN209281395 U CN 209281395U CN 201920277131 U CN201920277131 U CN 201920277131U CN 209281395 U CN209281395 U CN 209281395U
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Abstract
The utility model discloses a kind of restructural signal processing platforms of wide frequency ranges, belong to integrated circuit fields, the restructural signal processing platform of wide frequency ranges uses GPPA technology, chip is handled using match Sentos Zynq-7000 series A ll Programmable SoC, completes system control and base band signal process function；Radio frequency and baseband front-end processing function are realized using ADI company high-performance transceiver AD9361 chip；Outbound data interaction passes through gigabit network interface.The platform possesses ultra-wide band radio-frequency processing capacity, and functional module can recombinate, is expansible, supports full platform on-line reorganization, is adaptable to different application scene.
Description
Technical field
The utility model belongs to integrated circuit field more particularly to a kind of restructural signal processing platform of wide frequency ranges.
Background technique
Signal processing it is most basic in have transformation, filtering, modulation, demodulation, detection and spectrum analysis and estimation etc..Transformation
Fourier transformation, sine transform, cosine transform, Walsh transformation of type etc.；Filtering includes high-pass filtering, low pass filtered
Wave, bandpass filtering, Wiener filtering, Kalman filtering, linear filtering, nonlinear filtering and adaptive-filtering etc.；Spectrum analysis side
Face includes the analysis of deterministic signal and the analysis of random signal, usually study it is most common be random signal analysis, also referred to as unite
Signal analysis or estimation are counted, its usual and heterogeneous linear Power estimation and nonlinear spectral are estimated；Power estimation has cyclic graph estimation, maximum entropy
Power estimation etc.；With the complication of signal type, the signal of analysis is being required not to be able to satisfy the items such as Gaussian Profile, non-minimum phase
When part, and there is the method for high order equilibrium.High order equilibrium can provide the phase information of signal, non-gaussian category information and non-
Linear information；Adaptive-filtering with it is balanced be also application study a big field.Adaptive-filtering includes that transverse direction LMS is adaptively filtered
Wave, lattice adaptive-filtering, adaptive cancellation filtering and adaptive equalization etc..In addition, for array signal, there are also array letters
Number processing etc..
Different signal processing modes needs to be realized with special hardware platform in practical applications, causes so certain
The waste of material resource and human resources.The utility model provides a versatility platform for signal processing.By developing not
With application program from programmable logic cells are programmed to different signal processings.
Utility model content
Input signal amplification filtered quadrature is down-converted to baseband signal by the content of the present invention, and baseband signal carries out modulus
It is admitted to core programmable logic unit, the design philosophy for the function modoularization that Platform Designing uses after conversion, while selecting height
Integrated chip is spent, circuit size is greatly reduced, the performance of board hardware resource abundant and powerful signal processing is nothing
Line signal processing system provides effective Platform Solution.
The utility model uses following technical scheme to solve above-mentioned technical problem:
A kind of restructural signal processing platform of wide frequency ranges, comprising radio frequency and baseband analog front end, micro controller module,
Storage unit, data interaction unit, next stage platform and storage array, extension mouth and power supply unit；
The radio frequency and baseband analog front end include the change up and down of signal impedance matching module, signal pre-processing module, radio frequency
Frequency processing module, modulus/number touch conversion module and video input and output interface；
Output becomes up and down to radio frequency signal is transmitted to signal impedance matching module after being accessed by video input and output interface after
Frequency processing module carries out signal processing；Signal RF Up/Down Conversion processing module processing after again after signal impedance matching module by
Video input and output interface output；
Micro controller module includes control unit, programmable logic cells, and control unit can be compiled by parameter configuration control
Journey logic unit carries out series of processes to digital signal；
Programmable logic cells are connect by chip I/O Interface with control unit I/O interface physical, and control unit instruction is logical
It crosses the register of each functional module of I/O interface access platform and is written and read；
Data interaction unit includes gigabit networking data interaction module, communication port module, wireless network transmissions mould
Block, modules, which work independently from each other, provides a variety of paths for system external data interaction；
Storage unit includes the synchronous random access memories of SDRAM and external ROM read-only memory；SDRAM is synchronized at random
Dynamic memory is responsible for reading and writing data, program loading operation space, and external ROM read-only memory is responsible for storage system parameter, leads to
It crosses SDRAM and reads the progress program operation of ROM system parameter；
Wherein, radio frequency and baseband analog front-end processing unit, for Signal Pretreatment such as amplification, filtering, impedance matching,
Down coversion, analog-to-digital conversion signal access channel, dac signal output channel；
Radio frequency input/output interface, for being signal input output end mouth；
Signal impedance matching module carries out impedance matching for accessing output to various types of signal；
Signal pre-processing module, for amplifying, filtering to signal, the pretreatment such as amplitude modulation；
Radio frequency Up/Down Conversion processing module, for carrying out up-conversion extremely to output signal to access signal in orthogonal down coversion
Radio frequency；
Modulus/number touches conversion module, for the analog signal analog-to-digital conversion to access to digital signal, to the number of output
Signal digital-to-analogue conversion is to analog signal；
Programmable logic cells, for being used for the bottom layer treatment and analysis of digital signal for platform core cell；
Control unit instructs for other platforms of responding and analyzing or itself platform and is issued to corresponding each unit mould
Block ensures that each item instruction can obtain the execution of effective；
SDRAM random access memories read and write data for storing ephemeral data；
ROM read-only memory is external, is used for reading platform prefab data；
Gigabit networking data interaction module is used for the wire transmission of platform high-speed data；
Wireless network transmission module is based on Transmission Control Protocol, is wirelessly transferred for platform data；
Communication port is used for platform slow data transmission；
Universal serial bus connects peripheral hardware such as keyboard, mouse, display for platform；
Power supply unit, for being platform each unit module for power supply；
Mouth is extended, expansion platform programmable logic cells are used for.
The invention adopts the above technical scheme compared with prior art, has following technical effect that
1, input signal amplification filtered quadrature is down-converted to baseband signal by the utility model, and baseband signal carries out modulus and turns
Core programmable logic unit is admitted to after changing, core cell carries out bottom layer treatment to data according to different application scene and divides
Analysis, and data are transmitted to upper layer device or software by Peripheral Interface, entire platform circuitry is mainly made of three parts, is put down
The design philosophy for the function modoularization that platform design uses, while Highgrade integration chip is selected, it is greatly reduced circuit size,
Board hardware resource abundant and powerful signal handling capacity provide effective platform for wireless signal processing system and solve
Scheme；
2, the realization of the core unit module function of the utility model relies on Zynq -7000 All
Programmable SoC, the series of products have redefined the design of hardware and software method of embedded system, are System Architect
New solution is released with software developer, provides a flexible platform, while being tradition ASIC and SoC user
Provide a complete programmable alternative；Double-core ARM Cortex-A9 processor and it is leading, have height
Power dissipation ratio of performance 28nm programmable logic is ingenious integrated, the far super discrete processors of the power consumption and performance rate of realization and FPGA system
System.Zynq-7000 SoC is the pioneer in first All Programmable SoC of industry and similar product market；By most
High-performance, price and power dissipation ratio, the product become the optimal selection in many Embedded Application fields.In order to improve system resource,
Using high Kintex -7 FPGA of resourceful cost performance, which realizes optimum cost/property in 28nm node
Energy/power-consumption balance, while high DSP rate, high performance-price ratio encapsulation are provided, and support various high speed mainstream interface standards；
3, the radio frequency processing module of the utility model selects AD9361, and AD9361 is a towards 3G and 4G base station applies
Radio frequency (RF) Agile Transceiver agile transceiver of high-performance, high integration；The programmability of the device and broadband
Ability becomes the ideal chose of a variety of transceiver applications；The device front end collection RF is with flexible mixed signal baseband part
One integrates frequency synthesizer, provides configurable digital interface for processor, imports to simplify design；AD9361 receiver
LO operating frequency range is 70 MHz to 6.0 GHz, and transmitter LO operating frequency range is 47 MHz to 6.0 GHz, is covered big
Part charter and unlicensed band, the bandwidth chahnel range of support are 200 kHz to 56 MHz.Two independent direct changes
Frequency receiver possesses premier noise coefficient and the linearity；
4, the utility model has external interface abundant.
Detailed description of the invention
Fig. 1 is the utility model letter processing platform structure schematic diagram；
Fig. 2 is the utility model radio frequency and baseband analog front-end processing unit-impedance matching principle figure；
Fig. 3 radio frequency and baseband analog front-end processing unit-circuit diagram；
Fig. 4 programmable logic cells and control unit-operational process；
Fig. 5 data interaction unit-data transmit-receive schematic diagram；
Fig. 6 data interaction unit-Wi-Fi data interaction module schematic diagram.
Specific embodiment
The technical solution of the utility model is described in further detail with reference to the accompanying drawing:
Input signal amplification filtered quadrature is down-converted to baseband signal by the present invention, and baseband signal carries out quilt after analog-to-digital conversion
It is sent into core programmable logic unit, core cell carries out bottom layer treatment and analysis to data according to different application scene, and will
Data are transmitted to upper layer device or software by Peripheral Interface, and entire platform circuitry is mainly made of three parts, Platform Designing
The design philosophy of the function modoularization of use, while Highgrade integration chip is selected, it is greatly reduced circuit size, board is rich
The performance of rich hardware resource and powerful signal processing handles resolution system for wireless signal and provides effective platform solution party
Case；
As shown in Figure 1, a kind of restructural signal processing platform of wide frequency ranges, comprising radio frequency and baseband analog front end, micro-
Controller module, storage unit, data interaction unit, next stage platform and storage array, extension mouth and power supply unit；
The radio frequency and baseband analog front end include the change up and down of signal impedance matching module, signal pre-processing module, radio frequency
Frequency processing module, modulus/number touch conversion module and video input and output interface；
Output becomes up and down to radio frequency signal is transmitted to signal impedance matching module after being accessed by video input and output interface after
Frequency processing module carries out signal processing；Signal RF Up/Down Conversion processing module processing after again after signal impedance matching module by
Video input and output interface output；
Micro controller module includes control unit, programmable logic cells, and control unit can be compiled by parameter configuration control
Journey logic unit carries out series of processes to digital signal；
Programmable logic cells are connect by chip I/O Interface with control unit I/O interface physical, and control unit instruction is logical
It crosses the register of each functional module of I/O interface access platform and is written and read；
Data interaction unit includes gigabit networking data interaction module, communication port module, wireless network transmissions mould
Block, modules, which work independently from each other, provides a variety of paths for system external data interaction；
Storage unit includes the synchronous random access memories of SDRAM and external ROM read-only memory；SDRAM is synchronized at random
Dynamic memory is responsible for reading and writing data, program loading operation space, and external ROM read-only memory is responsible for storage system parameter, leads to
It crosses SDRAM and reads the progress program operation of ROM system parameter；
Wherein, radio frequency and baseband analog front-end processing unit, for Signal Pretreatment such as amplification, filtering, impedance matching,
Down coversion, analog-to-digital conversion signal access channel, dac signal output channel；
Radio frequency input/output interface, for being signal input output end mouth；
Signal impedance matching module carries out impedance matching for accessing output to various types of signal；
Signal pre-processing module, for amplifying, filtering to signal, the pretreatment such as amplitude modulation；
By S1(SMA interface) access after be transmitted to T1(impedance matching) export afterwards to AD9361 carry out signal processing, wherein
C1, C2 are capacitance；
Signal output: signal is through T2(impedance matching after AD9361 processing) after by S2(SMA interface)) output, wherein C4, C5
For capacitance, C3, C6, L31, L32 constitute signal and export DC bias networks.
Radio frequency Up/Down Conversion processing module, for carrying out up-conversion extremely to output signal to access signal in orthogonal down coversion
Radio frequency；
Modulus/number touches conversion module, for the analog signal analog-to-digital conversion to access to digital signal, to the number of output
Signal digital-to-analogue conversion is to analog signal；
Programmable logic cells, for being used for the bottom layer treatment and analysis of digital signal for platform core cell；
Control unit instructs for other platforms of responding and analyzing or itself platform and is issued to corresponding each unit mould
Block ensures that each item instruction can obtain the execution of effective；
SDRAM random access memories read and write data for storing ephemeral data；
ROM read-only memory is external, is used for reading platform prefab data；
Gigabit networking data interaction module is used for the wire transmission of platform high-speed data；
Wireless network transmission module is based on Transmission Control Protocol, is wirelessly transferred for platform data；
Communication port is used for platform slow data transmission；
Universal serial bus connects peripheral hardware such as keyboard, mouse, display for platform；
Power supply unit, for being platform each unit module for power supply；
Mouth is extended, expansion platform programmable logic cells are used for.
Working platform process are as follows:
Signal input service process: radio frequency of DC ~ 6GHz radiofrequency signal through radio frequency and baseband analog front-end processing unit is defeated
Enter output interface input → signal impedance matching module carry out signal impedance matching → signal pre-processing module carry out it is low to signal
Signal is down-converted to base band letter by the pretreatments → radio frequency Up/Down Conversion processing modules such as noise amplification, filtering, amplitude modulation, amplitude balance
Number → radio frequency and baseband analog front-end processing unit digital-to-analogue/analog-to-digital conversion module carry out analog-to-digital conversion to baseband signal, AD is sampled
→ other platforms instruction that the program instruction or data interaction unit of control unit responding and analyzing storage unit receive → can
The instruction that programmed logic unit response control unit is parsed carries out bottom layer treatment and analysis such as FFT sampling, playback, number to signal
Data to next stage platform or store battle array by gigabit networking or wireless network transmissions after word processing, modulation /demodulation etc. → processing
Column.
Signal output services process: other platforms of control unit responding and analyzing or the inputted letter of platform storage unit itself
The instruction that number → programmable logic cells response control unit is parsed carries out digital processing → radio frequency and base band to signal
AFE(analog front end) processing unit to after signal digital-to-analogue conversion, up-conversion, amplification, filtering, impedance matching through signal output module by SMA
Output.
Platform each unit with and respective modules function:
Radio frequency and baseband analog front-end processing unit are for Signal Pretreatment such as amplification, filtering, impedance matching, up and down change
Frequently, analog-to-digital conversion (signal access channel), digital-to-analogue conversion (signal output channels) etc..
Wherein SMA interface is signal input output end mouth；
Signal impedance matching module accesses output to various types of signal and carries out impedance matching；
The pretreatments such as signal pre-processing module amplifies signal, filters, amplitude modulation；
Radio frequency Up/Down Conversion processing module carries out up-conversion to radio frequency to access signal in orthogonal down coversion, to output signal.
Modulus/number touches conversion module to the analog signal analog-to-digital conversion of access to digital signal, to the digital signal of output
Digital-to-analogue conversion is to analog signal.
Programmable logic cells are the bottom layer treatment and analysis that platform core cell is used for digital signal.Such as modulation /demodulation,
Discrete Fu
In Ye Bianhua, adaptive-filtering etc..
Control unit is that the brain of platform is instructed for other platforms of responding and analyzing or itself platform and is issued to corresponding
Each list
Element module ensures that each item instruction can obtain the execution of effective, and hardware support is double-core ARMcortex-
A9。
Storage unit is stored and is read and write for platform data.
Wherein SDRAM random access memories read and write data for storing ephemeral data；
ROM read-only memory (external) reading platform prefab data.
Data interaction unit is the bridge of data interaction between platform and other platforms or storage array.
Wherein gigabit networking data interaction module is based on ICP/IP protocol, is used for the wire transmission of platform high-speed data；
Wireless network transmission module is based on Transmission Control Protocol, is wirelessly transferred for platform data；
Communication port is used for platform slow data transmission；
Universal serial bus is for platform connection peripheral hardware such as keyboard, mouse, display etc..
Power supply unit is used to be platform each unit module for power supply.
It extends mouth and is used for expansion platform programmable logic cells.Increase its resource.
Such as Fig. 2 radio frequency and baseband analog front-end processing unit integrated circuit schematic diagram-impedance matching principle figure.
Signal access: by S1(SMA interface) access after be transmitted to T1(impedance matching) export afterwards to AD9361 carry out signal
Processing, wherein C1, C2 are capacitance；
Signal output: signal is through T2(impedance matching after AD9361 processing) after by S2(SMA interface)) output, wherein C4, C5
For capacitance, C3, C6, L31, L32 constitute signal and export DC bias networks.
AD9361 chip: the integrated chip multiple signal processing modules, each functional module correspond to different compile
Journey I/O interface circuit, the chip I/O Interface are connect with control unit I/O interface physical, and control unit instruction passes through I/O interface
The register of each functional module of access chip is simultaneously written and read, and AD9361 receives instruction by register and transfers each function of chip
It can every processing of the module execution to access output signal.
Radio frequency and baseband analog front-end processing unit signal access AD9361 pretreatment process.
Low noise amplification, mixing phase demodulation, filtering, secondary filtering, analog-to-digital conversion.
Radio frequency and baseband analog front-end processing unit signal export AD9361 pretreatment process.
Digital-to-analogue conversion, filtering, secondary filtering, mixing phase demodulation, power amplification.
Fig. 3 radio frequency and baseband analog front-end processing unit-AD9361 schematic diagram.
In pin name containing alphabetical VDDA be chip supply input pin and platform power unit power supply output establish connect
It connects；
Pin name CTRL_IN0 ~ CTRL_IN3 controls input pin, establishes connection with control unit I/O interface and receives control
Manual RX(access is realized in unit processed instruction) gain and TX(output) adjustable attenuation input pin；
Pin name CTRL_OUT0 ~ CTRL_OUT7 is control output pin, is established with programmable logic cells I/O interface
Connection.Control unit receives this group of signal control output data analysis processing, obtains chip various functions state；
Pin name RX_FRAME receives numerical data output pin, establishes connection with programmable logic cells I/O interface.
Whether effective it is used to indicate RX output data；
Pin name TX_FRAME emits numerical data output pin, establishes connection with programmable logic cells I/O interface.
When effective it is used to indicate TX data.
Pin name RX1A receiving channel input pin establishes connection with the output of impedance matching module receiving channel.It is core
Piece signal input.
Pin name TX1A transmission channel output pin establishes connection with the output of impedance matching module transmission channel.It is core
The signal output of piece.
Pin name DATA_CLK receives data clock output, establishes connection with programmable logic cells I/O interface.For RX
Data provide reference clock.
Pin name FB_CLK emits data clock input, establishes connection with programmable logic cells I/O interface.For TX number
According to offer reference clock.
Pin name CLK_OUT clock output establishes connection with programmable logic cells I/O interface.It can be compiled for synchronizing
Journey logic unit and interface clock.
Pin name EN_AGC control input.Connection is established with programmable logic cells I/O interface.Receive programmable logic
Cell data enables chip automatic gain control function.
Pin ENABLE control input.Connection is established with programmable logic cells I/O interface.Receive programmable logic cells
Instruction makees state (suspend mode, high-performance etc.) for switching chip operation.
Pin TX_D0 ~ TX_D5 emits input bus.Connection is established with programmable logic cells I/O interface.Emit link
Upper reception programmable logic cells operating instruction.
Pin RX_D0 ~ RX_D5 emits input bus.Connection is established with programmable logic cells I/O interface.Receives link
Upper reception programmable logic cells operating instruction.
The chip belongs to Zynq -7000 All Programmable (complete programmable) SoC(double-core RAM+FPGA frame
Structure).
Fig. 4 programmable logic cells and control unit-operational process
The unit is platform core, and it is mono- to be issued to AD9361 for generation configuration parameter after the instruction of double-core ARM executing application
Member, programmable logic cells；AD9361, which is executed instruction, is sent into programmable logic list to formation sampled signal after access signal processing
Member, at the same the digital signal for receiving programmable logic cells handled after export；It is corresponding according to different application scenarios burnings
Configuration file to programmable logic cells, the parameter configuration instruction that programmable logic cells are issued according to ARM is completed corresponding
Signal processing；The platform operating system is Linux.
Fig. 5 data interaction unit-data transmit-receive schematic diagram.
Platform data link layer data and physical layer (such as light are realized by gigabit Ethernet transceiving chip (88E1111)
Fibre, copper cable) data interaction.Physical layer data passes through Ethernet interface (gigabit networking) or wireless transport module and external device
Carry out data interaction.
Fig. 6 data interaction unit-Wi-Fi data interaction module schematic diagram.
Platform data and extraneous realization wireless interaction are realized by radio receiving transmitting module HLK-RM04.
Platform Designing is following module by the technical solution of realization: core unit module (believe by system control, base band
Number processing), radio frequency processing module, external interface module.Modules complete respective function, and work compound.
The realization of core unit module function relies on Zynq -7000 All Programmable (complete programmable)
SoC, the series of products have redefined the design of hardware and software method of embedded system, are System Architect and software developer
New solution is released, provides a flexible platform, while providing one for tradition ASIC and SoC user and entirely may be used
The alternative of programming.Double-core ARM Cortex-A9 processor and it is leading, have high-performance power dissipation ratio 28nm
Programmable logic is ingenious integrated, the far super discrete processors of the power consumption and performance rate of realization and FPGA system.Zynq-7000 SoC
It is the pioneer in first All Programmable SoC of industry and similar product market.By peak performance, price and power consumption
Than the product becomes the optimal selection in many Embedded Application fields.In order to improve system resource, using resourceful sexual valence
Than high Kintex -7 FPGA, which realizes optimum cost/performance/power-consumption balance in 28nm node, provides simultaneously
High DSP rate, high performance-price ratio encapsulation, and support various high speed mainstream interface standards.
It is a high-performance towards 3G and 4G base station applies that radio frequency processing module, which selects AD9361, AD9361, highly integrated
Radio frequency (RF) Agile Transceiver agile transceiver of degree.The programmability and broadband ability of the device become
The ideal chose of a variety of transceiver applications.The device integrates the front end RF and flexible mixed signal baseband part, integrated frequency
Rate synthesizer provides configurable digital interface for processor, imports to simplify design.AD9361 receiver LO working frequency model
It encloses for 70 MHz to 6.0 GHz, transmitter LO operating frequency range is 47 MHz to 6.0 GHz, covers most of charter
And unlicensed band, the bandwidth chahnel range of support are 200 kHz down toward 56 MHz.Two independent direct converting receiving devices
Possess premier noise coefficient and the linearity.Each reception (RX) subsystem is owned by independent automatic growth control
(AGC), DC maladjustment correction, quadrature alignment and digital filter function, provide these functions to eliminate in digital baseband
Necessity.The AD9361 also possesses flexible manual gain mode, supports external control.It is dynamic that two height are carried in each channel
The I signal received and Q signal are first carried out digitized processing, are then transmitted through configurable by state range analog-todigital converter (ADC)
As a result decimation filter and 128 tap finite impulse response (FIR) filters generate 12 output letters with corresponding sample rate
Number.Transmitter is using Direct Conversion framework, it can be achieved that higher modulation accuracy and ultralow noise.This transmitter design is brought
Industry optimal TX Error Vector Magnitude (EVM), numerical value can be stayed less than 40 dB for the selection of external power amplifier (PA)
Considerable system margin out.Onboard transmitting (TX) power monitor may be used as power detector, to realize high precision
TX power measurement.Fully-integrated phaselocked loop (PLL) can provide the fractional-N divide of low-power consumption for all receptions and transmission channel
Frequency synthesis.The channel separation of frequency division duplex (FDD) system needs is integrated in design.Also it is integrated with all VCO and loop filter
Wave device device.
The platform has external interface abundant: USB interface form: MiniUSB(USB2.0 version), interface quantity: 1
It is a；Serial interface form: MiniUSB(USB turns serial ports), interface quantity: 1；Ethernet interface interface form: RJ45, interface
Quantity: 1, network interface rate: gigabit；Memory card interface form: SD card or TF card, interface quantity: 1, memory capacity: 64GB
(system file occupies the space 1GB)；Radio frequency interface 1) rf input interface form: SMA；Interface quantity: 1；2) radio frequency exports
Interface form: SMA；Interface quantity: 1.
Claims (4)
1. a kind of restructural signal processing platform of wide frequency ranges, it is characterised in that: include radio frequency and baseband analog front end, micro-control
Device module, storage unit, data interaction unit, next stage platform and storage array processed, extension mouth and power supply unit；
The radio frequency and baseband analog front end include signal impedance matching module, signal pre-processing module, at radio frequency Up/Down Conversion
Reason module, modulus/number touch conversion module and video input and output interface；
Signal exports after being transmitted to signal impedance matching module after being accessed by video input and output interface to radio frequency Up/Down Conversion
It manages module and carries out signal processing；After the processing of signal RF Up/Down Conversion processing module again after signal impedance matching module by video
Input/output interface output；
Micro controller module includes control unit, programmable logic cells, and control unit is patrolled by the way that parameter configuration control is programmable
It collects unit and series of processes is carried out to digital signal；
Programmable logic cells are connect by chip I/O Interface with control unit I/O interface physical, and control unit instruction passes through I/
The register of each functional module of O Interface access platform is simultaneously written and read；
Data interaction unit includes gigabit networking data interaction module, communication port module, wireless network transmission module, respectively
A module, which works independently from each other, provides a variety of paths for system external data interaction；
Storage unit includes the synchronous random access memories of SDRAM and external ROM read-only memory；SDRAM synchronizes stochastic and dynamic
Memory is responsible for reading and writing data, program loading operation space, and external ROM read-only memory is responsible for storage system parameter, is passed through
SDRAM reads ROM system parameter and carries out program operation；
Wherein, radio frequency and baseband analog front-end processing unit, for Signal Pretreatment such as amplification, filtering, impedance matching, up and down change
Frequently, analog-to-digital conversion signal accesses channel, dac signal output channel；
Radio frequency input/output interface, for being signal input output end mouth；
Signal impedance matching module carries out impedance matching for accessing output to various types of signal；
Signal pre-processing module, for amplifying, filtering to signal, the pretreatment such as amplitude modulation；
Radio frequency Up/Down Conversion processing module, for carrying out up-conversion to radio frequency to output signal to access signal in orthogonal down coversion；
Modulus/number touches conversion module, for the analog signal analog-to-digital conversion to access to digital signal, to the digital signal of output
Digital-to-analogue conversion is to analog signal；
Programmable logic cells are used for the bottom layer treatment and analysis of digital signal for platform core cell；
Control unit instructs for other platforms of responding and analyzing or itself platform and is issued to corresponding each unit module, protects
Hinder each item and instructs the execution that can obtain effective；
SDRAM random access memories read and write data for storing ephemeral data；
ROM read-only memory is external, is used for reading platform prefab data；
Gigabit networking data interaction module is used for the wire transmission of platform high-speed data；
Wireless network transmission module is based on Transmission Control Protocol, is wirelessly transferred for platform data；
Communication port is used for platform slow data transmission；
Universal serial bus connects peripheral hardware such as keyboard, mouse, display for platform；
Power supply unit, for being platform each unit module for power supply；
Mouth is extended, expansion platform programmable logic cells are used for.
2. the restructural signal processing platform of a kind of wide frequency ranges according to claim 1, it is characterised in that: the video
Input/output interface uses SMA interface.
3. the restructural signal processing platform of a kind of wide frequency ranges according to claim 1, it is characterised in that: the control
Unit uses double-core ARM Cortex-A9 processor.
4. the restructural signal processing platform of a kind of wide frequency ranges according to claim 1, it is characterised in that: the radio frequency
The chip model of Up/Down Conversion processing module is AD9361.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111308906A (en) * | 2019-11-01 | 2020-06-19 | 北京航空航天大学 | General hardware platform for satellite navigation system simulation |
| CN112433970A (en) * | 2020-12-02 | 2021-03-02 | 上海集成电路研发中心有限公司 | Euse controller, chip and efuse read-write system |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111308906A (en) * | 2019-11-01 | 2020-06-19 | 北京航空航天大学 | General hardware platform for satellite navigation system simulation |
| CN112433970A (en) * | 2020-12-02 | 2021-03-02 | 上海集成电路研发中心有限公司 | Euse controller, chip and efuse read-write system |
| CN112433970B (en) * | 2020-12-02 | 2024-02-20 | 上海集成电路研发中心有限公司 | efuse controller, chip and efuse read-write system |
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