CN112420840A - 半导体装置结构 - Google Patents
半导体装置结构 Download PDFInfo
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- CN112420840A CN112420840A CN202010849573.7A CN202010849573A CN112420840A CN 112420840 A CN112420840 A CN 112420840A CN 202010849573 A CN202010849573 A CN 202010849573A CN 112420840 A CN112420840 A CN 112420840A
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Abstract
一种半导体装置结构,包括鳍状结构、硬掩模层、栅极结构及源极/漏极结构。鳍状结构形成于基板之上;硬掩模层形成于鳍状结构之上;栅极结构,形成围绕硬掩模层及鳍状结构,且栅极结构的部分介于鳍状结构及硬掩模层之间;源极/漏极结构形成于邻近栅极结构。
Description
技术领域
本发明实施例涉及一种半导体装置的制造方法,尤其涉及一种环绕栅极结构的形成方法。
背景技术
电子工业经历了对于更小及更快的电子装置需求不断增加,其可同时支持更多的越来越复杂的功能。因此,半导体工业的具有制造低成本、高效能及低功率集成电路(integrated circuits,ICs)的持续趋势。截至目前为止,通过缩小半导体集成电路尺寸(例如最小部件尺寸)可达成大部分这些目标,且因此改善了制造效率及降低了相关成本。然而,如此缩小使得半导体制造工艺中复杂性增加。因此,实现半导体集成电路及装置持续进展需要半导体制造工艺及科技也有类似的发展。
近来,提出了多栅极装置以通过增加栅极-通道耦合、减少截止状态电流以及减少短通道效应(short-channel effects(SCEs)来改善栅极控制。所提出的这样的多栅极装置之一为环绕栅极晶体管(gate-all around transistor,GAA)。环绕栅极装置之名来自于因栅极可延伸环绕通道区域,提供从二或四侧进接至通道。环绕栅极装置与常规的互补式金属氧化物半导体(complementary metal-oxide-semiconductor,CMOS)工艺相容。然而,整合制造环绕栅极部件围绕纳米线可能具有挑战性。例如,尽管现行方法在许多方面都令人满意,但仍需要持续的改善。
发明内容
本发明实施例的目的在于提供一种半导体装置结构,以解决上述至少一个问题。
本发明实施例包括一种半导体装置结构,包括鳍状结构、硬掩模层、栅极结构及源极/漏极结构。鳍状结构形成于基板之上;硬掩模层形成于鳍状结构之上;栅极结构形成围绕硬掩模层及鳍状结构,且栅极结构的部分介于鳍状结构及硬掩模层之间;源极/漏极结构形成于邻近栅极结构。
本发明实施例的有益效果在于,半导体装置结构可包括形成硬掩模层于鳍状结构之上,以及形成栅极结构包围硬掩模层及鳍状结构,且部分栅极结构可介于鳍状结构及硬掩模层之间。硬掩模层在形成栅极结构时可保护鳍状结构。因此,可降低半导体装置的临界电压变异,且可增加半导体装置的效能。
附图说明
以下将配合所附附图详述本发明实施例。应注意的是,各种特征部件并未按照比例绘制且仅用以说明例示。事实上,元件的尺寸可能经放大或缩小,以清楚地表现出本发明实施例的技术特征。
图1A至图1O是根据一些实施例示出形成半导体装置结构的各阶段的透视图。
图2A及图2B是根据一些实施例示出形成如图1L及图1M所示出的半导体装置结构的各阶段剖面图。
图2C-1及图2C-2是根据一些实施例示出形成如图1N所示出的半导体装置结构的剖面图。
图3A至图3D是根据一些实施例示出形成半导体装置结构的各阶段的透视图。
图4A-1及图4A-2是根据一些实施例示出形成如图3D所示出的半导体装置结构的剖面图。
图5A至图5D是根据一些实施例示出形成半导体装置结构的各阶段的透视图。
图6A-1及图6A-2是根据一些实施例示出形成如图5D所示出的半导体装置结构的剖面图。
附图标记如下:
100a,100b,100c:半导体装置结构
102:基板
104:第一半导体材料
104’,104”:蚀刻的第一半导体层
106:第二半导体材料
106’:第二半导体层
107:堆叠结构
108:硬掩模材料
108’,108”:硬掩模层
109:光刻胶层
110:鳍状结构
112,112’:沟槽
114:衬层
116:隔离结构
118:虚置栅极介电材料
118’:虚置栅极介电层
120:虚置栅极电极层
122:虚置栅极结构
124:氧化物层
126:氮化物层
128:硬掩模层
130,130’:沟槽
132:栅极间隔物层
132’:栅极间隔物
134:内间隔物
136:源极/漏极结构
138:接点蚀刻停止层
140:层间介电结构
142:沟槽
144:间隙
146:界面层
148:高介电常数层
150:功函数层
152:栅极电极层
154:金属盖层
156:栅极结构
158:硬掩模层
160:硅化物层
162:接点
I-I,II-II:线
L:长度
T1,T2,T3,T4,T5:厚度
具体实施方式
以下的公开内容提供许多不同的实施例或范例以实施本案的不同特征。以下的公开内容叙述各个构件及其排列方式的特定范例,以简化说明。当然,这些特定的范例并非用以限定。例如,若是本发明实施例叙述了一第一特征部件形成于一第二特征部件之上或上方,即表示其可能包含上述第一特征部件与上述第二特征部件是直接接触的实施例,亦可能包含了有附加特征部件形成于上述第一特征部件与上述第二特征部件之间,而使上述第一特征部件与第二特征部件可能未直接接触的实施例。此外,本发明实施例可在各范例重复使用标号及/或文字。这样的重复是为了简洁及清楚起见,而并非表示所讨论的各实施例及/或形态之间的关系。
描述了一些本发明实施例。通过各视图及所述的实施例,相似的元件可使用相似的标号表示。应理解的是,可在这些实施例所述的阶段之前、之中及/或之后提供额外的操作。不同的实施例可取代或消除所述的一些阶段。
可以任何适合的方法图案化下述的环绕栅极(gate all around,GAA)晶体管结构。例如,使用一或多种光刻工艺,包括双重图案化工艺或多重图案化工艺图案化结构。一般而言,双重图案化或多重图案化工艺组合了光刻及自对准工艺,允许创造具有例如相较于使用单一直接光刻工艺可得的更小节距的图案。例如,在一实施例中,形成牺牲层于基板之上并使用光刻工艺图案化。使用自对准工艺沿着图案化牺牲层形成间隔物。接着移除牺牲层,且余留的间格物可用以图案化环绕栅极结构。
提供了半导体装置结构(例如环绕栅极结构)及其形成方法。半导体装置结构可包括硬掩模层形成于鳍状结构之上,以及栅极结构环绕硬掩模层及鳍状结构,以及栅极结构的一部分可介于鳍状结构及硬掩模层之间,因此,在制造过程中,可通过硬掩模层保护鳍状结构及部分的栅极结构。
图1A至图1O是根据一些实施例示出形成半导体装置结构100a的各阶段的透视图。图2A及图2B是根据一些实施例示出形成如图1L及图1M所示出的半导体装置结构100a的各阶段剖面图。
图2C-1及图2C-2是根据一些实施例示出形成如图1N所示出的半导体装置结构100a的剖面图。图2A、图2B及图2C-1是根据一些实施例示出沿图1L、图1M及图1N的线I-I截取的剖面图。图2C-2是根据一些实施例示出沿图1N的线II-II截取的剖面图。
根据一些实施例,如图1A所示出,得到了基板102。基板102可为半导体晶片例如硅晶片。替代或附加地,基板102可包括元素半导体材料、化合物半导体材料及/或合金半导体材料。元素半导体材料的范例包括但不限于晶体硅、多晶硅、非晶硅、锗及钻石。化合物半导体材料的范例可包括但不限于碳化硅(silicon carbide)、砷化镓(gallium arsenic)、磷化镓(gallium phosphide)、磷化铟(indium phosphide)、砷化铟(indium arsenide)及锑化铟(indium antimonide)。合金半导体材料的范例可包括但不限于SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP及GaInAsP。
在一些实施例中,基板102包括外延层。例如,基板102具有覆盖块材半导体的外延层。在一些实施例中,基板102为绝缘体上覆半导体(semiconductor-on-insulator,SOI),其可包括半导体基板、基板上的埋藏氧化层以及埋藏氧化层上的半导体层。
根据一些实施例,如图1A所示出,形成堆叠结构107于基板102之上。在一些实施例中,堆叠结构107包括以第二组成的第二半导体材料106插入的第一组成的第一半导体材料104,使得第一半导体材料104及第二半导体材料106在后续蚀刻工艺中具有不同的蚀刻率。在一些实施例中,第一半导体材料104及第二半导体材料106以交替的方式堆叠。
在一些实施例中,第一半导体材料104及第二半导体材料106包括Si、Ge、SiGe、GaAs、InSb、GaP、GaSb、InAlAs、InGaAs、GaSbP、GaAsSb或InP。在一些实施例中,第一半导体材料104为SiGe及第二半导体材料106为Si。
在一些实施例中,使用低压化学气相沉积(low pressure chemical vapordeposition,LPCVD)工艺、外延成长工艺、其他合适的工艺或上述的组合形成第一半导体材料104及第二半导体材料106。在一些实施例中,外延成长工艺包括分子束外延(molecularbeam epitaxy,MBE)、金属有机化学气相沉积(metal organic chemical vapordeposition,MOCVD)或气相外延(vapor phase epitaxy,VPE)。
第一半导体材料104或其部分可作为定义后续形成的半导体装置结构100a相邻的通道区域之间的间隙距离,以及第二半导体材料106或其部分可作为后续形成的半导体装置结构100a的通道区域。例如,第二半导体材料可称为用以形成半导体装置结构100a例如环绕栅极装置的通道区域的“纳米线”。
应注意的是,虽然在图1A中示出五层第一半导体材料104及四层第二半导体材料106,第二半导体材料106的数目可在由2至10的范围内,且第一半导体材料104的总数目比第二半导体材料106的总数目多一层。
根据一些实施例,如图1A所示出,此外,形成硬掩模材料108于堆叠结构107之上,且形成图案化的光刻胶层109于硬掩模材料108之上。在一些实施例中,硬掩模材料108包括一或多种介电材料,例如碳化硅(silicon carbide)、氧化硅(silicon oxide)、氮化硅(silicon nitride)、氮氧化硅(silicon oxynitride)、其他合适的介电材料或上述的组合。
可依照装置效能及制造的考虑来选择硬掩模材料108的材料。在一些实施例中,硬掩模材料108包括具介电常数(k值)小于7的介电材料,例如SiCN、SiOC、SiOCN或上述的组合。在一些实施例中,硬掩模材料108包括高介电常数介电材料(例如k>7),例如HfO2、ZrO2、HfAlOx、Al2O3或上述的组合。
在一些实施例中,硬掩模材料108为多层结构。例如,硬掩模材料108可包括下层,其以氧化硅制成,以及上层,其以氮化硅制成。在一些实施例中,可以沉积工艺形成硬掩模材料108,其可包括化学气相沉积(chemical vapor deposition,CVD)工艺、高密度等离子体化学气相沉积(high-density plasma chemical vapor deposition,HDPCVD)工艺、旋转涂布工艺、溅镀工艺及其他适用的工艺。
此外,图案化的光刻胶层109,其形成于硬掩模材料108之上,可以沉积工艺及后续的图案化工艺形成。形成图案化的光刻胶层109的沉积工艺可包括化学气相沉积工艺、高密度等离子体化学气相沉积工艺、旋转涂布工艺、溅镀工艺及其他适用的工艺。形成图案化的光刻胶层109的图案化工艺可包括光刻工艺及蚀刻工艺。光刻工艺可包括光刻胶涂布(例如旋转涂布)、软烘烤、掩模对齐、曝光、曝光后烘烤、显影光刻胶、清洗及干燥(例如硬烘烤)。蚀刻工艺可包括干蚀刻工艺或湿蚀刻工艺。
根据一些实施例,如图1B所示出,在形成图案化的光刻胶层109之后,使用图案化的光刻胶层109作为掩模,图案化硬掩模材料108以形成硬掩模层108’。根据一些实施例,形成硬掩模层108’之后,移除了图案化的光刻胶层109。在一些实施例中,硬掩模层108’为非功能性虚置通道层。在一些实施例中,硬掩模层108’为保护层,其保护下方的结构在后续的工艺中免于受损害。
接着,根据一些实施例,使用硬掩模层108’作为掩模,对堆叠结构107及基板102进行蚀刻工艺以形成鳍状结构110。具体而言,根据一些实施例,蚀刻工艺移除了堆叠结构107由硬掩模层108’露出的部分,且更凹蚀基板102以形成第一半导体层104’、第二半导体层106’及鳍状结构110之间的沟槽112。
根据一些实施例,在蚀刻工艺之后,基板102具有沟槽112之间的突出部分,其形成鳍状结构110的下部,以及第一半导体层104’及第二半导体层106’形成鳍状结构110的上部。在一些实施例中,蚀刻工艺包括干蚀刻工艺,例如反应离子蚀刻(reactive-ionetching,RIE)或中性束蚀刻(neutral-beam etching,NBE)、湿蚀刻工艺或上述的组合。
根据一些实施例,如图1C所示出,在形成鳍状结构110之后,形成衬层114及隔离结构116于沟槽112之中。在一些实施例中,形成衬层114及隔离结构116的方法包括形成衬里材料顺应性地覆盖基板102、鳍状结构110及硬掩模层108’,且形成绝缘材料于衬里材料之上以及填充沟槽112。之后,部分移除绝缘材料及衬里材料以形成减少的沟槽112’于衬里材料及绝缘材料的余留部分(即衬层114及隔离结构116)之上。
在一些实施例中,衬层114及隔离结构116以氧化硅、氮化硅、氮氧化硅、其他适用的绝缘材料或上述的组合制成。在一些实施例中,使用热氧化工艺、化学气相沉积工艺、原子层沉积(atomic layer deposition,ALD)工艺、低压化学气相沉积工艺、等离子体增强化学气相沉积(plasma enhanced CVD,PECVD)工艺、高密度等离子体化学气相沉积工艺、可流动化学气相沉积(flowable CVD,FCVD)工艺、其他适用的工艺或上述的组合形成衬层114及隔离结构116。
应注意的是,即使是在衬层114及隔离结构116形成之后,并未移除硬掩模层108’,且根据一些实施例,如图1D所示出,形成虚置栅极介电材料118以顺应性地覆盖硬掩模层108’的顶表面及侧壁。在一些实施例中,以虚置栅极介电材料118顺应性地覆盖鳍状结构110的侧壁及上部、隔离结构116的顶表面及衬层114的顶表面。
在一些实施例中,虚置栅极介电材料118包括一或多种介电材料,例如氧化硅、氮化硅、氮氧化硅或上述的组合。在一些实施例中,虚置栅极介电层118为具有高介电常数(k值)例如大于3.9的介电材料。在一些实施例中,高介电常数介电材料包括HfO2、HfZrO、HfSiO、HfTiO、HfAlO、其他适用的高介电常数介电材料或上述的组合。在一些实施例中,使用热氧化、化学气相沉积、原子层沉积、物理气相沉积(physical vapor deposition,PVD)、其他适用的方法或上述的组合形成介电材料。
之后,根据一些实施例,如图1E所示出,形成虚置栅极结构122跨过鳍状结构110及硬掩模层108’。在一些实施例中,形成硬掩模层128于虚置栅极结构122之上。硬掩模层128可用以作为形成虚置栅极结构122的蚀刻掩模。
在一些实施例中,每一虚置栅极结构122包括虚置栅极介电层118’及虚置栅极电极层120,以及硬掩模层128包括氧化物层124(例如氧化硅)及形成于氧化物层124之上的氮化物层126(例如氮化硅)。此外,根据一些实施例,形成沟槽130于虚置栅极结构122之间。
在一些实施例中,形成虚置栅极结构122包括形成虚置栅极电极材料于虚置栅极介电材料118之上且以虚置栅极电极材料填充减少的开口112’,以及形成硬掩模层128于虚置栅极电极材料之上。可以沉积工艺及图案化工艺形成硬掩模层128。接着,根据一些实施例,移除了以硬掩模层128露出的虚置栅极电极材料部分以及虚置栅极介电材料118部分以露出硬掩模层108’。
在形成虚置栅极结构122的虚置栅极电极材料及虚置栅极介电材料118的部分移除工艺(例如蚀刻工艺)时,可能不易控制虚置栅极结构122的轮廓。例如,在部分移除工艺之后,虚置栅极结构122可能具有逐渐从顶部至底部增加的宽度(也就是竹状问题),使得漏电路径可能发生于栅极结构的底部,其在后续的工艺中替代了虚置栅极结构122。然而,若虚置栅极电极材料及虚置栅极介电材料118被重度蚀刻以形成具有从顶部至底部大抵相同宽度的虚置栅极结构122,可能增加损害鳍状结构110的风险。
因此,在一些实施例中,由于硬掩模层108’形成于鳍状结构110之上,在形成虚置栅极结构122的重度部分移除工艺时可以硬掩模层108’保护鳍状结构110。因此,即使由于结构的缩小而使鳍状物节距及栅极长度相对较小时,可同时避免竹状问题和对于鳍状结构110的损害。
应注意的是,根据一些实施例,硬掩模层108’的顶表面及侧壁以虚置栅极结构122之间的沟槽130部分露出。此外,在一些实施例中,第一半导体层104’的侧壁及第二半导体层106’的侧壁部分露出。
在一些实施例中,虚置栅极电极层120以导电材料制成。在一些实施例中,导电材料包括多晶硅(polycrystalline-silicon,poly-Si)、多晶硅锗(poly-crystallinesilicon-germanium,poly-SiGe)、金属氮化物、金属硅化物、金属或上述的组合。在一些实施例中,以沉积工艺,例如化学气相沉积、物理气相沉积或上述的组合,以及后续的蚀刻工艺形成虚置栅极电极层120。
根据一些实施例,如图1F所示出,在形成虚置栅极结构122之后,形成栅极间隔物层132于虚置栅极结构122的顶表面及侧壁上。在一些实施例中,硬掩模层108’的顶表面和侧壁、鳍状结构110的侧壁及隔离结构116的顶表面被栅极间隔物层132顺应性地覆盖,如此可得到虚置栅极结构122之间的减少的沟槽130’,且形成栅极间隔物层132衬于沟槽130的侧壁上。
在一些实施例中,栅极间隔物层132以介电材料制成,例如氧化硅(siliconoxide,SiO2)、氮化硅(silicon nitride,SiN)、碳化硅(silicon carbide,SiC)、氮氧化硅(silicon oxynitride,SiON)、碳氮化硅(silicon carbon nitride,SiCN)、碳氮氧化硅(silicon oxide carbonitride,SiOCN)或上述的组合。在一些实施例中,以使用化学气相沉积(例如低压化学气相沉积、等离子体增强化学气相沉积或次大气压化学气相沉积(sub-atmospheric CVD,SACVD))、原子层沉积、其他适用的方法或上述的组合形成栅极间隔物层132。
接着,根据一些实施例,如图1G所示出,由栅极间隔物层132所形成的成对的栅极间隔物132’形成于虚置栅极结构122的相对侧壁上,且移除了从虚置栅极结构122及栅极间隔物132’露出的鳍状结构110的部分。在一些实施例中,以移除栅极间隔物132在硬掩模层128上的部分以及移除栅极间隔物层132在硬掩模层108’顶表面上的部分。在一些实施例中,移除了栅极间隔物层132在隔离结构116顶表面上的部分。栅极间隔物层的部分移除工艺可包括干蚀刻工艺、湿蚀刻工艺或上述的组合。
根据一些实施例,在形成栅极间隔物132’之后,移除了从虚置栅极结构122及栅极间隔物132’露出的鳍状结构110部分。鳍状结构110的部分移除工艺可包括干蚀刻工艺、湿蚀刻工艺或上述的组合。
在一些实施例中,在鳍状结构110的部分移除工艺之后基板102的顶表面与隔离结构116的顶表面及第一半导体层104’的底表面齐平。在一些实施例中,在进行了鳍状结构110的部分移除工艺之后,基板102的顶表面低于隔离结构116的顶表面以及第一半导体层104’的底表面,取决于部分移除工艺的参数。
根据一些实施例,如图1H所示出,之后,横向蚀刻被硬掩模层108’覆盖的第一半导体层104’,以得到蚀刻的第一半导体层104”。在一些实施例中,移除了第一半导体层104’的外部,且保留被虚置栅极结构122直接覆盖的第一半导体层104’的内部作为蚀刻的第一半导体层104”。
在一些实施例中,横向蚀刻第一半导体层104’包括干蚀刻工艺、湿蚀刻工艺或上述的组合。在一些实施例中,蚀刻的第一半导体层104”的侧壁未对齐第二半导体层106’的侧壁。
根据一些实施例,如图1I所示出,在横向蚀刻第一半导体层104’之后,形成内间隔物134于蚀刻的第一半导体层104”的侧壁之上。根据一些实施例,内间隔物134以介电材料制成,其介电常数值(k-value)小于6,例如在约2至约6的范围。在一些实施例中,内间隔物134是用以降低栅极结构及后续形成的源极/漏极(source/drain,S/D)结构之间的寄生电容。如果内间隔物134的介电常数值太高,内间隔物134可能无法帮助降低寄生电容。
在一些实施例中,以碳氧化硅(silicon oxycarbide,SiOC)、碳氮氧化硅(siliconoxide carbonitride,SiOCN)、碳氮化硅(silicon carbon nitride,SiCN)或上述的组合制成内间隔物134。在一些实施例中,以沉积工艺及后续的回蚀工艺形成内间隔物134。沉积工艺可包括化学气相沉积(例如低压化学气相沉积、等离子体增强化学气相沉积、次大气压化学气相沉积或可流动化学气相沉积)、原子层沉积工艺、其他适用的方法或上述的组合。回蚀工艺可包括干蚀刻工艺或湿蚀刻工艺。
在一些实施例中,蚀刻的第一半导体层104”及内间隔物134之间的界面直接位于虚置栅极结构122之下。在一些实施例中,蚀刻的第一半导体层104”及内间隔物134之间的界面与虚置栅极结构122及栅极间隔物132’之间的界面对齐。
根据一些实施例,如图1J所示出,在形成内间隔物134之后,形成源极/漏极(source/drain,S/D)结构136于虚置栅极结构122的相对侧壁之上。在一些实施例中,源极/漏极结构136以栅极间隔物132’与虚置栅极结构122相隔,且源极/漏极结构136以内间隔物134与蚀刻的第一半导体层104”相隔。此外,根据一些实施例,源极/漏极结构136直接接触第二半导体层106’。
在一些实施例中,源极/漏极结构136以Ge、Si、SiGe、InAs、InGaAs、InSb、GaAs、GaSb、InAlP、InP、AlGaAs、GaAsP、SiP、SiC、SiCP、其他适用的材料或上述的组合制成。在一些实施例中,使用一或多道外延成长工艺,例如分子束外延、金属有机化学气相沉积、气相外延、其他适用的外延成长工艺或上述的组合形成源极/漏极结构136。
在一些实施例中,在外延成长工艺时原位掺杂源极/漏极结构136。例如,源极/漏极结构136可为以硼(boron,B)掺杂的外延成长SiGe。在一些实施例中,在外延成长工艺后的一或多道注入工艺中掺杂源极/漏极结构136。
在一些实施例中,以退火工艺活化源极/漏极结构136。在一些实施例中,退火工艺包括快速热退火(rapid thermal annealing,RTA)、激光退火工艺、其他适用的退火工艺或上述的组合。
之后,形成接点蚀刻停止层(contact etching stop layer,CESL)138于源极/漏极结构136之上,且形成层间介电(interlayer dielectric,ILD)结构140于接点蚀刻停止层138之上。在一些实施例中,形成接点蚀刻停止层138以顺应性地覆盖源极/漏极结构136的顶表面,且接点蚀刻停止层138延伸于栅极间隔物132’的侧壁及硬掩模层108’的侧壁之上。
在一些实施例中,以介电材料例如氮化硅、氧化硅、氮氧化硅、其他合适的介电材料或上述的组合制成接点蚀刻停止层138。在一些实施例中,以化学气相沉积(例如等离子体蚀刻化学气相沉积、高选择比工艺(high aspect ratio process,HARP)或上述的组合)、原子层沉积、其他适用的方法或上述的组合形成接点蚀刻停止层138。
在一些实施例中,层间介电结构140包括以多介电材料例如氧化硅、氮化硅、氮氧化硅、磷硅酸盐玻璃(phosphosilicate glass,PSG)、硼磷硅酸盐玻璃(borophosphosilicate glass,BPSG)、低介电常数材料及/或其他适用的介电材料制成的多层。低介电常数材料的范例包括但不限于氟硅酸盐玻璃(fluorinated silica glass,FSG)、碳掺杂氧化硅、非晶质氟化碳(amorphous fluorinated carbon)、聚对二甲苯(parylene)、双苯并环丁烯(bis-benzocyclobutenes,BCB)及聚酰亚胺(polyimide)。此外,可以化学气相沉积、物理气相沉积、原子层沉积、旋转涂布或其他适用的工艺形成层间介电结构140。
之后,根据一些实施例,如图1K所示出,进行平坦化工艺于层间介电结构140上直至露出虚置栅极结构122的顶表面。在平坦化工艺之后,虚置栅极结构122的顶表面及栅极间隔物132’的顶表面可与层间介电结构140大抵齐平。在一些实施例中,平坦化工艺包括研磨工艺、化学机械研磨(chemical mechanical polishing,CMP)工艺、蚀刻工艺、其他适用的工艺或上述的组合。
接着,根据一些实施例,如图1L及图2A所示出,移除虚置栅极结构122以在层间介电结构140中形成沟槽142。图2A为沿图1L的线I-I截取的剖面图。更具体而言,形成每一沟槽142于每一对栅极间隔物132’之间,且从沟槽142部分露出硬掩模层108’。在一些实施例中,以蚀刻工艺例如干蚀刻工艺或湿蚀刻工艺移除了虚置栅极结构122的虚置栅极介电层118’及虚置栅极电极层120。
根据一些实施例,如图1M及图2B所示出,在形成沟槽142之后,移除蚀刻的第一半导体层104”以形成间隙144。根据一些实施例,图2B为沿图1M的线I-I截取的剖面图。在一些实施例中,移除工艺包括选择性蚀刻工艺。根据一些实施例,选择性蚀刻工艺移除了蚀刻的第一半导体层104”并保留了第二半导体层106’作为“纳米线”,用以形成半导体装置结构100a的通道区域。
在一些实施例中,移除蚀刻的第一半导体层104”的选择性蚀刻工艺包括湿蚀刻工艺、干蚀刻工艺或上述的组合。在一些实施例中,选择性蚀刻工艺为无等离子体干化学蚀刻工艺。在一些实施例中,干化学蚀刻工艺的蚀刻剂包括自由基例如HF、NF3、NH3、H2或上述的组合。
应注意的是,在一些实施例中,移除蚀刻的第一半导体层104”的选择性蚀刻工艺时,蚀刻了沟槽142露出的硬掩模层108’部分,使得获得了蚀刻的硬掩模层108”。在一些实施例中,栅极间隔物132’正下方的蚀刻的硬掩模层108”部分的高度大于沟槽142露出的蚀刻的硬掩模层108”部分的高度。此外,根据一些实施例,第二半导体层106’(即纳米线)的侧壁大抵与蚀刻的硬掩模层108”的侧壁对齐。
此外,根据一些实施例,一些间隙144形成于蚀刻的硬掩模层108”及第二半导体层106’之间,以及其他的一些间隙144形成于第二半导体层106’之间。此外,在一些实施例中,间隙144介于内间隔物134之间。
根据一些实施例,如图1N、图2C-1及图2C-2所示出,在形成间隙144之后,形成栅极结构(或金属栅极结构)156包围蚀刻的硬掩模层108”及第二半导体层106’。根据一些实施例,图2C-1为沿图1N的线I-I截取的剖面图,且图2C-2为沿图1N的线II-II截取的剖面图。
根据一些实施例,栅极结构156可为多层结构。每一栅极结构156包括界面层146、高介电常数介电层148、功函数层150、栅极电极层152及金属盖层154。在一些实施例中,第二半导体层106’被界面层146包围,且直接接触界面层146,且界面层146被高介电常数层148包围。在一些实施例中,并未形成界面层146包围蚀刻的硬掩模层108”,且蚀刻的硬掩模层108”被高介电常数层148包围,且直接接触高介电常数层148。
在一些实施例中,以氧化硅制成界面层146,且以热氧化形成界面层。在一些实施例中,每一高介电常数层148以一或多层介电材料制成,例如HfO2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、氧化锆(zirconium oxide)、氧化铝(aluminum oxide)、氧化钛(titaniumoxide)、二氧化铪-氧化铝合金(hafnium dioxide-alumina alloy,HfO2-Al2O3)、其他适用的高介电常数介电材料或上述的组合。在一些实施例中,使用化学气相沉积、原子层沉积、其他适用的方法或上述的组合形成高介电常数层148。
此外,根据一些实施例,以功函数层150包围高介电常数层148,且形成栅极电极层152于功函数层150之上。应注意的是,根据一些实施例,蚀刻的硬掩模层108”下的间隙144以界面层146填充,高介电常数层148及功函数层150及栅极电极层152并未填入间隙144之中。此外,在一些实施例中,栅极电极层152未被蚀刻的硬掩模层108”覆盖。
在一些实施例中,功函数层150以金属材料制成,且金属材料可包括N型功函数金属或P型功函数金属。N型功函数金属可包括钨(tungsten,W)、铜(copper,Cu)、钛(titanium,Ti)、银(silver,Ag)、铝(aluminum,Al)、钛铝合金(TiAl)、氮化铝钛(titaniumaluminum nitride,TiAlN)、碳化钽(tantalum carbide,TaC)、氮化碳钽(tantalum carbonnitride,TaCN)、氮化硅钽(tantalum silicon nitride,TaSiN)、锰(manganese,Mn)、锆(zirconium,Zr)或上述的组合。P型功函数金属可包括氮化钛(titanium nitride,TiN)、氮化钨(tungsten nitride,WN)、氮化钽(tantalum nitride,TaN)、钌(ruthenium,Ru)或上述的组合。
在一些实施例中,每一栅极电极层152以一或多层导电材料例如多晶硅、铝、铜、钛、钽、钨、钴、钼、氮化钽、硅化镍、硅化钴、TiN、WN、TiAl、TiAlN、TaCN、TaC、TaSiN、金属合金、其他适用的材料或上述的组合。在一些实施例中,使用化学气相沉积、原子层沉积、电镀、其他适用的方法或上述的组合形成栅极电极层152。
此外,根据一些实施例,如图1N、图2C-1及图2C-2所示出,形成金属盖层154于栅极电极层152之上,且形成硬掩模层158于栅极结构156的金属盖层154之上。
在一些实施例中,金属盖层154以钨(tungsten,W)及/或其他导电金属材料制成。在一些实施例中,使用化学气相沉积、高密度等离子体化学气相沉积工艺、金属有机化学气相沉积,等离子体增强化学气相沉积、其他适用的工艺或上述的组合形成金属盖层154。根据一些实施例,在形成金属盖层154之后,以蚀刻工艺凹蚀(回蚀)栅极结构156,并形成硬掩模层158于栅极结构156之上。
在一些实施例中,硬掩模层158以氧化物、氧化硅、氮化硅、碳氮化硅、碳氮氧化硅、SiLK或上述的组合制成。在一些实施例中,在沉积工艺例如化学气相沉积工艺、原子层沉积工艺或其他适用的工艺中形成硬掩模层158。此外,每一硬掩模层158可为以单一沉积工艺形成的单层,或多重沉积工艺形成的多层。
更具体而言,在一些实施例中,填充栅极结构156于蚀刻的硬掩模层108”及第二半导体层106’之间,且亦填充栅极结构156于第二半导体层106’之间的间隙144之中。第二半导体层106’之间栅极结构156的部分具有厚度T1,且蚀刻的硬掩模层108”与第二半导体层106’之间栅极结构156的部分具有厚度T2。
在一些实施例中,由于蚀刻的硬掩模层108”形成于第二半导体层106之上,且栅极结构156延伸于蚀刻的硬掩模层108”及第二半导体层106’之间,厚度T2与厚度T1大抵相同。
在一些实施例中,包围第二半导体层106’(即纳米线)及被蚀刻的硬掩模层108”覆盖的栅极结构156的部分的厚度为均匀的(即厚度T1大抵与厚度T2相同)。因此,半导体元件的临界电压(threshold voltage,Vt)变异可能减少。
此外,以蚀刻的硬掩模层108”覆盖第二半导体层106’(即纳米线)。因此,可保护第二半导体层106’使其在半导体装置不同区域中形成栅极结构156的多重图案化工艺时免于被蚀刻或损害。
此外,蚀刻的硬掩模层108”被栅极结构156直接覆盖且包围的部分具有厚度T3,且第二半导体层106’具有厚度T4。在一些实施例中,厚度T3与厚度T4大抵相同。此外,如图2C-2所示出,蚀刻的硬掩模层108”的另一部分被具有厚度T5的栅极间隔物132’直接覆盖。根据一些实施例,由于在形成间隙144的工艺时部分蚀刻了硬掩模层108’,厚度T5大于厚度T3。
在一些实施例中,厚度T3在约3nm至约10nm的范围,且厚度T5在约0至约30nm的范围。在一些实施例中,厚度T3相对厚度T5的比例大于或等于约0.1且小于1。若上述比例太小(也就是小于0.1),厚度T3太小(也就是小于3nm),在半导体装置结构的不同区域中形成栅极结构156的多重图案化工艺时第二半导体层106’可能未被蚀刻的硬掩模层108”保护。如果厚度T3太大(也就是大于10nm),栅极结构156的总高度可能增加,其降低了半导体装置的效能。此外,根据一些实施例,厚度T5为0,其将于后根据图5A至图5D详述。
形成了硬掩模层158之后,移除了部分接点蚀刻停止层138及部分层间介电结构140以形成接点开口,其露出了源极/漏极结构136。之后,根据一些实施例,如图1O所示出,形成硅化物层160于源极/漏极结构136露出的表面上,且形成接点162于硅化物层160之上。更具体而言,硅化物层160位于源极/漏极结构136及接点162之间。在一些实施例中,接点162穿过硅化物层160电性连接至源极/漏极结构136。硅化物层160可用以降低接点162及源极/漏极结构136之间的接点电阻(Rcsd)。
在一些实施例中,以沉积工艺形成阻挡层(未示出)于源极/漏极结构136之上,且对阻挡层进行退火工艺以形成硅化物层160。阻挡层首先可为U型,且阻挡层的底部可与源极/漏极结构136反应以形成硅化物层160。
在一些实施例中,硅化物层160以硅化钴(cobalt silicide)、硅化钛(titaniumsilicide)、硅化钽(tantalum silicide)、硅化镍(nickel silicide)、硅化铜(coppersilicide)、硅化钨(tungsten silicide)、硅化钼(molybdenum silicide)、其他适用的金属硅化物或上述的组合制成。在一些实施例中,阻挡层的沉积工艺包括物理气相沉积工艺、原子层沉积工艺或其他适用的工艺。在一些实施例中,在约300℃至约800℃的温度下进行退火工艺。在退火工艺之后,可移除阻挡层未反应的部分。
在一些实施例中,接点162以钨(tungsten,W)、钴(cobalt,Co)、钛(titanium,Ti)、铝(aluminum,Al)、铜(copper,Cu)、钽(tantalum,Ta)、铂(platinum,Pt)、钼(molybdenum,Mo)、银(silver,Ag)、锰(manganese,Mn)、锆(zirconium,Zr)、钌(ruthenium,Ru)或其他适用的材料制成。在一些实施例中,以沉积工艺例如化学气相沉积工艺、物理气相沉积工艺、原子层沉积工艺、电镀工艺或其他适用的工艺形成接点162。在形成接点162之后,得到了半导体装置结构100a。此外,根据一些实施例,如图1O所示出,硬掩模层108”具有长度L,且长度L与半导体装置结构100a的通道长度大抵相同。
在形成半导体装置结构100a的方法的实施例中,在形成虚置栅极结构122之前形成硬掩模层108’于鳍状结构110之上。因此,在形成虚置栅极结构122的重度部分移除工艺时可保护鳍状结构110。
此外,在半导体装置结构100a的实施例中,由于第二半导体层106’(也就是纳米线)被蚀刻的硬掩模层108”覆盖,栅极结构156包围第二半导体层106’部分的厚度可为均匀的(也就是厚度T1与厚度T2大抵相同)。因此,可降低半导体装置的临界电压变异,且在半导体装置结构的不同区域中形成栅极结构156的多重图案化工艺时可保护第二半导体层106’免于被蚀刻或损害。
根据一些实施例,图3A至图3D示出形成半导体装置结构100b的各阶段透视图。图3A至图3D所示出的形成半导体装置结构100b的步骤可与图1E、图1F、图1G及图1O所示出的形成半导体装置结构100a的步骤相似或相同,且之间的不同为于图3A中更进一步凹蚀以虚置栅极结构122露出的硬掩模层108’部分。
在一些实施例中,如图3A所示出,由于形成虚置栅极结构122的重度部分移除工艺,更进一步凹蚀了虚置栅极结构122所露出的硬掩模层108’部分。结果,根据一些实施例,硬掩模层108’及虚置栅极电极层120之间的界面高于虚置栅极结构122所露出的硬掩模层108’的顶表面。
之后,根据一些实施例,如图3B所示出,以栅极间隔物层132覆盖硬掩模层108’更进一步凹蚀的顶表面。接着,根据一些实施例,如图3C所示出,从栅极间隔物层132形成成对的栅极间隔物132’于虚置栅极结构122的相对侧壁之上,且移除了由虚置栅极结构122及栅极间隔物132’露出的鳍状结构110部分。
之后,形成半导体装置结构100b的后续工艺与形成半导体装置结构100a的工艺相似或相同,于此不重述,且根据一些实施例,得到了如图3D所示出的半导体装置结构100b。
根据一些实施例,图4A-1及图4A-2示出如图3D所示出的半导体装置结构100b的剖面图。图4A-1为沿图3D的线I-I截取的剖面图,且图4A-2为沿图3D的线II-II截取的剖面图。
即使在形成第二半导体层106’之间的间隙144的工艺时蚀刻了沟槽142所露出的硬掩模层108’的部分,可在先前步骤形成虚置栅极结构122的重度部分移除工艺更进一步凹蚀虚置栅极结构122所露出的硬掩模层108’的部分,且形成虚置栅极结构122的硬掩模层108’的凹蚀量大于形成第二半导体层106’之间的间隙144的凹蚀量。因此,根据一些实施例,被栅极结构156包围且在栅极电极层152正下方的厚度T3大于栅极间隔物132’正下方的厚度T5。
此外,根据一些实施例,由于厚度T2大抵与厚度T1相同,栅极结构156包围第二半导体层106’(也就是纳米线)且被蚀刻的硬掩模层108”覆盖的部分的厚度为均匀的。因此,可降低半导体装置的临界电压(threshold voltage,Vt)变异。
根据一些实施例,图5A至图5D示出形成半导体装置结构100c各阶段的透视图。图5A至图5D所示出的形成半导体装置结构100c的步骤可与图1E、图1F、图1G及图1O所示出的形成半导体装置结构100a的步骤相似或相同,且之间的不同为于图5A中完全移除了由虚置栅极结构122露出的硬掩模层108’部分。
在一些实施例中,如图5A所示出,由于形成虚置栅极结构122的重度部分移除工艺,完全移除了虚置栅极结构122所露出的硬掩模层108’部分。因此,根据一些实施例,部分露出了第一半导体层104’的顶表面。
之后,根据一些实施例,如图5B所示出,第一半导体层104’的顶表面以栅极间隔物层132覆盖。接着,根据一些实施例,如图5C所示出,从栅极间隔物层132形成成对的栅极间隔物132’于虚置栅极结构122的相对侧壁上,且移除了虚置栅极结构122及栅极间隔物132’露出的鳍状结构110部分。
之后,形成半导体装置结构100c的后续工艺与形成半导体装置结构100a的工艺相似或相同,于此不重述,且根据一些实施例,得到了如图5D所示出的半导体装置结构100c。
根据一些实施例,图6A-1及图6A-2示出如图5D所示出的半导体装置结构100c的剖面图。图6A-1为沿图5D的线I-I截取的剖面图,且图6A-2为沿图5D的线II-II截取的剖面图。
根据一些实施例,由于在先前步骤中形成虚置栅极结构122的重度部分移除工艺完全移除了虚置栅极结构122所露出的硬掩模层108’部分,硬掩模层108’在栅极间隔物132’的正下方没有任何部分。此外,根据一些实施例,栅极间隔物132’直接接触内间隔物134。根据一些实施例,相较于图2C-2及图4A-2中的半导体装置结构100a及100b,如图6A-2所示出,半导体装置结构100c的蚀刻的硬掩模层108”不具有厚度T5。
在半导体装置结构100a、100b及100c(也就是环绕栅极结构)的实施例中,以蚀刻的硬掩模层108”覆盖鳍状结构110,且因此在形成虚置栅极结构122的重度移除工艺时可以硬掩模层108’保护鳍状结构110。
此外,由于第二半导体层106’(也就是纳米线)被蚀刻的硬掩模层108”覆盖,且栅极结构156延伸于蚀刻的硬掩模层108”及第二半导体层106’之间,第二半导体层106’之间的栅极结构156部分的厚度与第二半导体层106’及蚀刻的硬掩模层108”之间的栅极结构156部分的厚度可为均匀的(也就是厚度T1与厚度T2大抵相同)。因此,可降低半导体装置临界电压(Vt)变异,且在形成半导体装置的不同区域中的栅极结构156的多重图案化工艺时可保护第二半导体层106’使其免于被蚀刻或损害。
提供了半导体装置结构及其形成方法。半导体装置结构可包括形成硬掩模层于鳍状结构之上,以及形成栅极结构包围硬掩模层及鳍状结构,且部分栅极结构可介于鳍状结构及硬掩模层之间。硬掩模层在形成栅极结构时可保护鳍状结构。因此,可降低半导体装置的临界电压(Vt)变异,且可增加半导体装置的效能。
在一些实施例中,提供了一种半导体装置结构。半导体装置结构包括鳍状结构形成于基板之上,以及硬掩模层形成于鳍状结构之上。半导体装置结构亦包括栅极结构形成围绕硬掩模层及鳍状结构,且栅极结构的一部分介于鳍状结构及硬掩模层之间。半导体装置结构还包括源极/漏极结构,形成于邻近栅极结构。在一实施例中,栅极结构还包括:高介电常数介电层围绕硬掩模层及鳍状结构,以及功函数层围绕高介电常数介电层,硬掩模层及鳍状结构以高介电常数介电层及功函数层相隔。在一实施例中,半导体装置结构还包括:接点蚀刻停止层形成于源极/漏极结构之上,以及层间介电结构形成于接点蚀刻停止层之上,硬掩模层的侧壁与接点蚀刻停止层及层间介电结构直接接触。在一实施例中,硬掩模层的侧壁与鳍状结构的侧壁大抵对齐。在一实施例中,半导体装置结构还包括:内间隔物形成于栅极结构及源极/漏极结构之间,内间隔物沿栅极结构部分的侧壁形成。在一实施例中,硬掩模层的厚度与鳍状结构的厚度大抵相同。
在一些实施例中,提供了一种半导体装置结构。半导体装置结构包括鳍状结构形成于基板之上。鳍状结构包括多个纳米线。半导体装置结构亦包括栅极结构形成于鳍状结构之上。栅极结构的第一部分延伸于多个纳米线之间。半导体装置结构还包括源极/漏极结构形成邻近栅极结构,以及虚置通道层形成于鳍结构之上。鳍状结构以栅极结构的第二部分与虚置通道层相隔。在一实施例中,多个纳米线之间栅极结构的第一部分的厚度与栅极结构的第二部分的厚度大抵相同。在一实施例中,半导体装置结构还包括:内间隔物形成于栅极结构的第二部分以及源极/漏极结构之间,内间隔物以虚置通道层覆盖。在一实施例中,半导体装置结构还包括:栅极间隔物形成于栅极结构侧壁之上,内间隔物及栅极间隔物以虚置通道层的第一部分相隔。在一实施例中,虚置通道层的第二部分位于栅极结构的第二部分的正上方,以及虚置通道层的第一部分的高度与虚置通道层的第二部分的高度不同。在一实施例中,半导体装置结构还包括:栅极间隔物形成于栅极结构的侧壁以及虚置通道层的侧壁之上,栅极间隔物与内间隔物直接接触。在一实施例中,虚置通道层的长度与半导体装置结构的通道长度大抵相同。
在一些实施例中,提供了形成半导体装置结构的方法。此方法包括形成鳍状结构于基板之上,其中鳍状结构包括交替的多个第一半导体层以及多个第二半导体层。形成半导体装置结构的方法亦包括形成保护层于多个第一半导体层的最顶层之上,且形成虚置栅极结构于保护层之上。形成半导体装置结构的方法还包括形成栅极间隔物于虚置栅极结构的侧壁之上,并移除虚置栅极结构及多个第一半导体层以形成沟槽。此外,形成半导体装置结构的方法包括形成金属栅极结构于沟槽中。保护层被金属栅极结构围绕。在一实施例中,在形成沟槽的步骤时部分蚀刻了保护层,且在形成金属栅极结构之后,保护层具有被栅极间隔物覆盖的第一部分以及被金属栅极结构覆盖的第二部分,第一部分的第一高度大于第二部分的第二高度。在一实施例中,第二高度与第一高度的比例大于或等于约0.1且小于1。在一实施例中,此方法还包括在移除虚置栅极结构之前横向蚀刻多个第一半导体层,以及在横向蚀刻之后形成内间隔物于多个第一半导体层余留部分的侧壁上。在一实施例中,形成栅极间隔物的步骤还包括:形成栅极间隔物层于虚置栅极的侧壁之上,且覆盖保护层的顶表面,以及部分移除栅极间隔物层使得形成了栅极间隔物。在一实施例中,保护层的侧壁与栅极间隔物直接接触。在一实施例中,形成栅极间隔物的步骤还包括:形成栅极间隔物层于虚置栅极结构的侧壁之上,栅极间隔物层与多个第一半导体层的最顶层直接接触,以及部分移除栅极间隔物层使得形成了栅极间隔物。
前述内文概述了许多实施例的特征部件,使本技术领域中技术人员可以从各个方面更佳地了解本发明实施例。本技术领域中技术人员应可理解,且可轻易地以本发明实施例为基础来设计或修饰其他工艺及结构,并以此达到相同的目的及/或达到与在此介绍的实施例相同的优点。本技术领域中技术人员也应了解这些相等的结构并未背离本发明实施例的发明精神与范围。在不背离本发明实施例的发明精神与范围的前提下,可对本发明实施例进行各种改变、置换或修改,因此本发明的保护范围当视随附的权利要求所界定者为准。另外,虽然本发明已以数个较佳实施例公开如上,然其并非用以限定本发明,且并非所有优点都已于此详加说明。
Claims (1)
1.一种半导体装置结构,包括:
一鳍状结构,形成于一基板之上;
一硬掩模层,形成于该鳍状结构之上;
一栅极结构,形成围绕该硬掩模层及该鳍状结构,且该栅极结构的一部分介于该鳍状结构及该硬掩模层之间;以及
一源极/漏极结构,形成于邻近该栅极结构。
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