CN112420790A

CN112420790A - Display panel

Info

Publication number: CN112420790A
Application number: CN202011279377.7A
Authority: CN
Inventors: 李纪辉; 靳增建; 鲜于文旭
Original assignee: Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
Current assignee: Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority date: 2020-11-16
Filing date: 2020-11-16
Publication date: 2021-02-26

Abstract

The application provides a display panel, which comprises a main display area and an edge display area surrounding the main display area; wherein the display panel further comprises: the pixel circuit units are arranged in the main display area in an array manner; and a plurality of OLED devices arranged in the main display area and the edge display area in an array manner, wherein each OLED device is electrically connected to a pixel circuit unit. This application has good display effect at display panel, sets up OLED device in order to form display panel's marginal display area in display panel's frame region for display panel's frame region is further compressed, is favorable to realizing the display panel of super narrow frame, improves the screen and accounts for the ratio, increases the range of application of product, thereby promotes user experience.

Description

Display panel

Technical Field

The application relates to the technical field of display, in particular to a display panel.

Background

With the development of display technology and the progress of technology, the application range of display devices is gradually increasing, such as those used in various multimedia devices such as televisions, mobile phones, in-vehicle displays, computer monitors, and game consoles, and display screens used for generating picture images. The display device includes a display area on which an image is displayed and a non-display area on which no image is displayed when viewed from the front.

In order to improve user experience, narrow borders are always the technology pursued by various products. The display panel with the extremely narrow frame can enable the picture to have more impact feeling, and provides better technical support for seamless splicing. For example, on a television display and a vehicle-mounted display, large-size and random splicing combination can be realized more easily.

Disclosure of Invention

The invention aims to provide a display panel to solve the technical problem of how to realize seamless splicing of the display panel.

To achieve the above object, the present invention provides a display panel including a main display area and an edge display area surrounding the main display area; wherein the display panel further comprises: the pixel circuit units are arranged in the main display area in an array manner; and a plurality of OLED devices arranged in the main display area and the edge display area in an array manner, wherein each OLED device is electrically connected to a pixel circuit unit.

Further, the pixel circuit units are arranged into M rows and N columns; the OLED devices are also arranged in M rows and N columns, wherein M, N is a positive integer; the central position of the OLED device in the main display area and the central position of the pixel circuit unit in the main display area are mutually coincident.

Further, the distance between two adjacent pixel circuit units is smaller than the distance between two adjacent OLED devices.

Further, each pixel circuit unit includes a 7T1C circuit including seven thin film transistors and a capacitor for driving an OLED device.

Further, the display panel further includes: a thin film transistor layer; the external driving circuit layer is arranged on the same layer with the thin film transistor layer; and at least one OLED device is correspondingly arranged above the external driving circuit layer.

Further, the display panel further includes: a flexible substrate extending from the main display area to the edge display area; the buffer layer is arranged on the flexible substrate and extends from the main display area to the edge display area; the barrier layer is arranged on the buffer layer and extends from the main display area to the edge display area; the thin film transistor layer and the external driving circuit layer are arranged on the blocking layer.

Further, each thin film transistor includes: an active layer; a first gate insulating layer disposed on the active layer; the first grid electrode layer is arranged on the first grid electrode insulating layer and completely falls into the projection of the active layer on the barrier layer in the projection of the barrier layer; a second gate insulating layer disposed on the first gate layer and the first gate insulating layer; the projection of the second gate layer on the active layer is completely superposed with the projection of the first gate layer on the active layer; a dielectric layer disposed on the second gate layer and the second gate insulating layer; the first through hole penetrates through the dielectric layer to the upper surface of the active layer in sequence; and the source drain layer is filled in the first through hole, covers the upper surface of the dielectric layer and is connected to the active layer.

Further, the display panel further includes: the flat layer is arranged on the thin film transistor layer and the external driving circuit layer and extends from the main display area to the edge display area; the second through hole penetrates through the source drain layer and is positioned in the main display area; and the first electrode layer is provided with a plurality of first electrodes, each first electrode fills the second through hole and extends to the surface of the flat layer, and the first electrode at the junction of the main display area and the edge display area extends from the main display area to the edge display area.

Furthermore, the external driving circuit layer comprises a GOA circuit wire, a VDD wire, a VSS wire and a data wire; the GOA circuit wire, the VDD wire and the VSS wire are arranged in the same layer; the data wiring and the source drain layer are arranged on the same layer.

Further, the display panel further includes: and the pixel defining layer is arranged on the flat layer and the first electrode layer, wherein the pixel defining layer is provided with a plurality of pixel units, two adjacent pixel units and the first electrode form a groove, and the groove is used for placing an OLED device.

The display panel has the advantages that the OLED device is arranged in the frame area of the display panel to form the edge display area of the display panel while the display panel has a good display effect, so that the frame area of the display panel is further compressed, the display panel with an ultra-narrow frame is favorably realized, the screen occupation ratio is improved, the application range of a product is increased, and the user experience is improved.

Drawings

The technical solution and other advantages of the present application will become apparent from the detailed description of the embodiments of the present application with reference to the accompanying drawings.

Fig. 1 is a plan view of a display panel 100 according to an embodiment of the present application.

Fig. 2 is a partially enlarged view of a portion a in fig. 1.

Fig. 3 is a cross-sectional view of a display panel 100 according to an embodiment of the present application.

The components of the drawings are identified as follows:

100 a display panel;

101 a main display area; 102 an edge display area;

10 pixel circuit units; 20 an OLED device;

1 a flexible substrate; 2, a buffer layer;

3 a barrier layer; 4 a thin film transistor layer;

5 an external driving circuit layer; 6 a flat layer;

7a first electrode layer; an 8-pixel definition layer; 9 a support column;

401 an active layer; 402 a first gate insulation layer;

403 a first gate layer; 404 a second gate insulation layer;

405 a second gate layer; 406 a dielectric layer;

407a source drain layer; 407b data routing;

11 a first through-hole; 12 a second via hole; 13, grooves;

71 a first electrode; and 81 pixel units.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. In this application, unless expressly stated or limited otherwise, the first feature "on" or "under" the second feature may comprise direct contact of the first and second features, or may comprise contact of the first and second features not directly but through another feature in between. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.

As shown in fig. 1, fig. 1 is a plan view of a display panel 100 according to an embodiment of the present application. The present embodiment provides a display panel 100 including a main display area 101 and an edge display area 102 surrounding the main display area 101.

Specifically, the display panel 100 further includes a pixel circuit unit 10 and an OLED device 20. A plurality of pixel circuit units 10 are arranged in the main display area 101 in an array.

Each pixel circuit cell 10 includes a 7T1C circuit including seven thin film transistors and a capacitor for driving an OLED device 20. Regarding the 7T1C circuit, reference may be made to a circuit of which the conventional pixel circuit cell is 7T1C, and a detailed description thereof is omitted.

A plurality of OLED devices 20 are arranged in the main display area 101 and the edge display area 102, and each OLED device 20 is electrically connected to a pixel circuit unit 10.

As shown in fig. 2, fig. 2 is a partially enlarged view of a in fig. 1. The pixel circuit units 10 are arranged in M rows and N columns; OLED devices 20 are also arranged in M rows and N columns, where M, N is a positive integer. That is, the number of the pixel circuit units 10 arranged in the main display area 101 is equal to the sum of the number of the OLED devices 20 arranged in the main display area 101 and the edge display area 102, which results in that the array area of the OLED devices 20 is larger than that of the pixel circuit units 10. In the conventional display panel, the array area of the OLED device is equal to the array area of the pixel circuit unit, so that the OLED device 20 of the embodiment of the present application is uniformly distributed to the periphery, and the pixel circuit unit 10 and the OLED device 20 are connected by routing, so as to drive the OLED device 20 to light.

In the present embodiment, the OLED device 20 is overlapped with the pixel circuit unit 10 in the center of the main display area 101, so that the connection distance between each pixel circuit unit 10 and the OLED device 20 is as short as possible, and the wiring space is reduced. Therefore, when the display panel 100 has a good display effect, the display panel 100 with an ultra-narrow frame can be realized, the screen occupation ratio is improved, the application range of the product is increased, and the experience of a user is improved. In other embodiments, the central position of the OLED device 20 in the main display area 101 and the central position of the pixel circuit unit 10 in the main display area 101 may not coincide with each other, as long as the display panel 100 can achieve the effect of an ultra-narrow bezel.

The center position of the main display area 101 in this embodiment is a position where the midpoint of a straight line H extending in the first direction intersects with the center of a straight line V extending in the second direction.

In this embodiment, the distance between two adjacent pixel circuit units 10 is smaller than the distance between two adjacent OLED devices 20, so that the pixel circuit units 10 of the display panel 100 are all located in the main display area 101, and thus do not occupy the frame area of the display panel 100, and therefore, the OLED devices 20 are placed in the frame area to form the edge display area 102, which is beneficial to realizing the narrow frame design of the display panel 100, and increasing the display picture of the display panel 100, thereby improving the user experience. Particularly, when a plurality of display panels 100 are spliced to realize a large-size display screen or a plurality of display panels 100 are arbitrarily spliced and combined, two adjacent display panels 100 can be seamlessly spliced, and the experience effect of a user is greatly improved.

As shown in fig. 3, fig. 3 is a cross-sectional view of a display panel 100 according to an embodiment of the present application. The display panel 100 further includes a flexible substrate 1, a buffer layer 2, a barrier layer 3, a thin film transistor layer 4, an external driving circuit layer 5, a planarization layer 6, a first electrode layer 7, a pixel defining layer 8, and support posts 9.

Specifically, the flexible substrate 1 extends from the main display area 101 to the edge display area 102. The flexible substrate 1 may have a stacked structure of a double-layer PI substrate or a structure of a single-layer PI substrate. The preferred double-deck PI base plate of this embodiment, wherein be equipped with inorganic layer between the double-deck PI base plate, consequently, the laminated structure of double-deck PI base plate can be when promoting the flexible ability of buckling of display panel 100, and water oxygen can also effectual separation is favorable to promoting the life-span of display panel.

The buffer layer 2 is disposed on the flexible substrate 1 and extends from the main display region 101 to the edge display region 102. The buffer layer 2 is made of SiNx or SiO₂For example, the buffer layer 2 may extend the path of water and oxygen permeation, thereby improving the sealing effect of the display panel 100.

The barrier layer 3 is disposed on the buffer layer 2 and extends from the main display region 101 to the edge display region 102. The barrier layer 3 is a multilayer laminated structure made of SiNx or SiO₂And the like, as long as the water and oxygen barrier ability of the display panel 100 can be improved, and is not particularly limited.

Thin-film transistor layer 4 is divided into a plurality of pixel circuit units 10. In the present embodiment, each of the tfts includes an active layer 401, a first gate insulating layer 402, a first gate layer 403, a second gate insulating layer 404, a second gate layer 405, a dielectric layer 406, and a source/drain layer 407 a.

Specifically, the active layer 401 is disposed on the barrier layer 3. The material of the active layer 401 is a metal oxide, such as indium gallium zinc oxide, but not limited thereto, and may also be one or more of aluminum zinc oxide, indium zinc oxide, indium oxide, boron-doped zinc oxide, and magnesium-doped zinc oxide. In addition, the active layer 401 may also be a polysilicon material or other materials.

The first gate insulating layer 402 is disposed on the active layer 401 and the barrier layer 3. The material of the first gate insulating layer 402 may be silicon oxide, silicon nitride, or other insulating materials.

The first gate layer 403 is disposed on the first gate insulating layer 402, and a projection thereof on the barrier layer 3 completely falls within a projection of the active layer 401 on the barrier layer 3. The material of the first gate layer 403 may include, but is not limited to, molybdenum, aluminum, and copper, and may also be, but is not limited to, chromium, tungsten, titanium, tantalum, and alloys containing the same.

A second gate insulating layer 404 is provided on the first gate layer 403 and the first gate insulating layer 402. The material of the second gate insulating layer 404 may be silicon oxide, silicon nitride, or other insulating materials.

The second gate layer 405 is disposed on the second gate insulating layer 404, and a projection thereof on the active layer 401 is completely overlapped with a projection of the first gate layer 403 on the active layer 401. The material of the second gate layer 405 may include, but is not limited to, molybdenum, aluminum, and copper, and may also include, but is not limited to, chromium, tungsten, titanium, tantalum, and alloys containing the same.

A dielectric layer 406 is provided on the second gate layer 405 and the second gate insulating layer 404. The dielectric layer 406 may be an insulating material such as silicon oxide or silicon nitride.

A plurality of first vias 11 sequentially extend from the dielectric layer 406 to the upper surface of the active layer 401. The source/drain layer 407a fills the first via 11, covers the upper surface of the dielectric layer 406, and is connected to the active layer 401. The source drain layer 407a may be made of, but not limited to, mo, al, cu, cr, w, ti, ta, and alloys thereof, and patterned by an etching process to form a source and a drain. The source and drain electrodes are connected to the active layer 401 through the first via hole 11.

The external driving circuit layer 5 is disposed in the same layer as the thin-film transistor layer 4. In other words, the thin-film transistor layer 4 and the external driving circuit layer 5 are both disposed on the barrier layer 3. At least one OLED device 20 is correspondingly disposed above the external driving circuit layer 5, so that the OLED device 20 is expanded toward the frame area of the display panel 100, thereby increasing the display frame of the display panel 100 and improving the user experience. Especially, in the process of splicing a plurality of display panels 100, two adjacent display panels 100 are seamlessly spliced, so that the experience effect of a user is greatly improved.

The external driving circuit layer 5 includes a GOA circuit trace, a VDD trace, a VSS trace, and a data trace. In this embodiment, the GOA circuit trace, the VDD trace, and the VSS trace are disposed in the same layer, and the data trace 407b and the source drain layer 407a are disposed in the same layer. The data trace 407b and the source drain layer 407a are patterned in the same process step. In this embodiment, the width ranges of the GOA circuit traces, the VDD traces, and the VSS traces can be reduced, thereby facilitating the increase of the driving capability of the GOA.

Planar layer 6 is disposed on thin-film-transistor layer 4 and extends from main display area 101 to edge display area 102. The material of the planarization layer 6 may be an insulating material such as silicon oxide or silicon nitride.

The second through holes 12 penetrate through the source/drain layer 407a and are located in the main display region 101. The first electrode layer 7 has a plurality of first electrodes 71, each first electrode 71 fills the second through hole 12 and extends to the upper surface of the planarization layer 6, wherein the first electrode 71 at the boundary between the main display area 101 and the edge display area 102 extends from the main display area 101 to the edge display area 102.

The pixel defining layer 8 is disposed on the planarization layer 6 and the first electrode layer 7. The pixel defining layer 8 has a plurality of pixel units 81, two adjacent pixel units 81 and the first electrode 71 form a groove 13, and the groove 13 is used for accommodating an OLED device 20.

A plurality of support posts 9 are disposed on the upper surface of the pixel defining layer 8 at intervals. The display panel 100 includes an array substrate and a color filter substrate disposed opposite to the array substrate. The flexible substrate 1, the buffer layer 2, the barrier layer 3, the thin-film transistor layer 4, the external driving circuit layer 5, the planarization layer 6, the first electrode layer 7, the pixel definition layer 8, and the support posts 9 described above constitute an array substrate of the display panel 100. The supporting columns 9 are used for supporting the color film substrate.

This embodiment provides a display panel, when display panel has good display effect, sets up OLED device in display panel's frame region in order to form display panel's marginal display area for display panel's frame region is compressed further, is favorable to realizing the display panel of super narrow frame, improves the screen and accounts for the ratio, increases the range of application of product, thereby promotes user experience.

The display panel provided by the embodiment of the present application is described in detail above, and a specific example is applied to illustrate the principle and the implementation manner of the present application, and the description of the embodiment is only used to help understanding the technical solution and the core idea of the present application; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications or substitutions do not depart from the spirit and scope of the present disclosure as defined by the appended claims.

Claims

1. A display panel comprising a main display area and an edge display area surrounding the main display area;

wherein the display panel further comprises:

the pixel circuit units are arranged in the main display area in an array manner; and

the OLED devices are arranged in the main display area and the edge display area in an array mode, and each OLED device is electrically connected to one pixel circuit unit.

2. The display panel according to claim 1,

the pixel circuit units are arranged into M rows and N columns; the OLED devices are also arranged in M rows and N columns, wherein M, N is a positive integer;

the central position of the OLED device in the main display area and the central position of the pixel circuit unit in the main display area are mutually coincident.

3. The display panel according to claim 1,

the distance between two adjacent pixel circuit units is smaller than the distance between two adjacent OLED devices.

4. The display panel according to claim 1,

each pixel circuit unit comprises a 7T1C circuit, which comprises seven thin film transistors and a capacitor, and is used for driving an OLED device.

5. The display panel according to claim 1, further comprising:

a thin film transistor layer; and

the external driving circuit layer is arranged on the same layer with the thin film transistor layer;

and at least one OLED device is correspondingly arranged above the external driving circuit layer.

6. The display panel according to claim 5, further comprising:

a flexible substrate extending from the main display area to the edge display area;

the buffer layer is arranged on the flexible substrate and extends from the main display area to the edge display area; and

the barrier layer is arranged on the buffer layer and extends from the main display area to the edge display area;

the thin film transistor layer and the external driving circuit layer are arranged on the blocking layer.

7. The display panel according to claim 5, wherein each thin film transistor comprises:

an active layer;

a first gate insulating layer disposed on the active layer;

the first grid electrode layer is arranged on the first grid electrode insulating layer and completely falls into the projection of the active layer on the barrier layer in the projection of the barrier layer;

a second gate insulating layer disposed on the first gate layer and the first gate insulating layer;

the projection of the second gate layer on the active layer is completely superposed with the projection of the first gate layer on the active layer;

a dielectric layer disposed on the second gate layer and the second gate insulating layer;

the first through hole penetrates through the dielectric layer to the upper surface of the active layer in sequence; and

and the source drain layer is filled in the first through hole, covers the upper surface of the dielectric layer and is connected to the active layer.

8. The display panel according to claim 5, further comprising:

the flat layer is arranged on the thin film transistor layer and the external driving circuit layer and extends from the main display area to the edge display area;

the second through hole penetrates through the source drain layer and is positioned in the main display area;

and the first electrode layer is provided with a plurality of first electrodes, each first electrode fills the second through hole and extends to the surface of the flat layer, and the first electrode at the junction of the main display area and the edge display area extends from the main display area to the edge display area.

9. The display panel according to claim 7,

the external driving circuit layer comprises a GOA circuit wire, a VDD wire, a VSS wire and a data wire;

the GOA circuit wire, the VDD wire and the VSS wire are arranged in the same layer;

the data wiring and the source drain layer are arranged on the same layer.

10. The display panel according to claim 8, further comprising:

and the pixel defining layer is arranged on the flat layer and the first electrode layer, wherein the pixel defining layer is provided with a plurality of pixel units, two adjacent pixel units and the first electrode form a groove, and the groove is used for placing an OLED device.