CN112420594A - Method for improving lateral undercut generated by groove etching - Google Patents
Method for improving lateral undercut generated by groove etching Download PDFInfo
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- CN112420594A CN112420594A CN202011344307.5A CN202011344307A CN112420594A CN 112420594 A CN112420594 A CN 112420594A CN 202011344307 A CN202011344307 A CN 202011344307A CN 112420594 A CN112420594 A CN 112420594A
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- silicon substrate
- hard mask
- etching
- improving
- mask pattern
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- 238000005530 etching Methods 0.000 title claims abstract description 50
- 238000000034 method Methods 0.000 title claims abstract description 35
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 89
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 84
- 239000010703 silicon Substances 0.000 claims abstract description 84
- 239000000758 substrate Substances 0.000 claims abstract description 81
- 229920000642 polymer Polymers 0.000 claims abstract description 26
- 238000001312 dry etching Methods 0.000 claims description 5
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76237—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Drying Of Semiconductors (AREA)
Abstract
The invention provides a method for improving side undercut generated by groove etching, which comprises the steps of providing a silicon substrate, and forming a hard mask layer on the silicon substrate; etching the hard mask layer until the upper surface of the silicon substrate is exposed to form a hard mask pattern; polymer is accumulated on the upper surface of the silicon substrate, and a fillet structure is formed at the root of the hard mask graph; and etching the silicon substrate along the hard mask pattern to form a groove with a uniform side wall structure. According to the invention, the polymer is accumulated at the root of the hard mask pattern on the silicon substrate, so that the side wall structure of the groove formed by etching is uniform, and the phenomenon of side digging of the side wall of the groove is avoided.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a method for improving side undercut generated by groove etching.
Background
In the etching process of the Power MOS groove (trench), because the selective etching ratio of silicon (Si) to a hard mask (hard mask) is higher, if the side wall protection of the groove (trench) is insufficient, an undercut phenomenon is easy to generate. As shown in fig. 1, fig. 1 is a schematic view of an electron microscope for generating undercutting in a conventional trench etching process.
Therefore, it is necessary to propose a new method for solving the above problems.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a method for improving trench etching to generate undercut, which is used to solve the problem in the prior art that undercut is generated on the trench sidewall due to high selective etching ratio of silicon to hard mask.
To achieve the above and other related objects, the present invention provides a method for improving undercut generation in trench etching, the method at least comprising the following steps:
providing a silicon substrate, and forming a hard mask layer on the silicon substrate;
etching the hard mask layer until the upper surface of the silicon substrate is exposed to form a hard mask pattern;
thirdly, polymers are accumulated on the upper surface of the silicon substrate, and a fillet structure is formed at the root of the hard mask graph;
and fourthly, etching the silicon substrate along the hard mask pattern to form a silicon structure with a uniform side wall structure.
Preferably, CHF is passed in step three3And O2And accumulating polymer on the surface of the silicon substrate.
Preferably, the CHF in step three3And O2Middle O2In an amount less than CHF3The content of (a).
Preferably, the passing CH in step three3F and O2And accumulating polymer on the surface of the silicon substrate.
Preferably, the CH in step three3F and O2Middle O2Is less than CH3The content of F.
Preferably, CHF is passed in step three3And, CH3F and O2And accumulating polymer on the surface of the silicon substrate.
Preferably, the CHF in step three3And, CH3The sum of the contents of F is more than O2The content of (a).
Preferably, after the silicon substrate is etched in the fourth step, a remaining hard mask pattern is formed on the top of the silicon structure.
Preferably, in the fourth step, the silicon substrate is etched by using a dry etching method.
As described above, the method for improving the undercut generated by trench etching according to the present invention has the following beneficial effects: according to the invention, the polymer is accumulated at the root of the hard mask pattern on the silicon substrate, so that the side wall structure of the groove formed by etching is uniform, and the phenomenon of side digging of the side wall of the groove is avoided.
Drawings
FIG. 1 is a schematic diagram of a structure of a silicon substrate having a hard mask pattern formed thereon according to the present invention;
FIG. 2 is a schematic diagram of a polymer deposition on a silicon substrate to form a fillet structure according to the present invention;
FIG. 3 is a schematic structural view of a trench formed by etching a silicon substrate according to the present invention;
FIG. 4 is a flowchart of a method for improving the lateral undercut generated by trench etching according to the present invention.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1 to 4. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
Example one
The invention provides a method for improving side undercut generated by trench etching, as shown in fig. 4, fig. 4 shows a flow chart of the method for improving side undercut generated by trench etching, the method at least comprises the following steps:
providing a silicon substrate, and forming a hard mask layer on the silicon substrate; as shown in fig. 1, fig. 1 is a schematic structural view illustrating a hard mask pattern formed on a silicon substrate according to the present invention. Providing the silicon substrate 01, and then forming a hard mask layer on the silicon substrate, wherein the hard mask layer covers the upper surface of the silicon substrate.
Etching the hard mask layer until the upper surface of the silicon substrate is exposed to form a hard mask pattern; as shown in fig. 1, in the second step, a hard mask layer on the silicon substrate is etched until the upper surface of the silicon substrate 01 is exposed, so as to form the hard mask pattern 02, and the hard mask pattern 02 is used as a mask for forming a trench by subsequent etching.
Thirdly, polymers are accumulated on the upper surface of the silicon substrate, and a fillet structure is formed at the root of the hard mask graph; as shown in fig. 2, fig. 2 is a schematic structural view illustrating a polymer deposited on a silicon substrate to form a fillet structure according to the present invention. In this step three, the polymer 03 is deposited on the silicon substrate 01, and further, in this example, the passage of CHF is performed in step three3And O2And accumulating polymer on the surface of the silicon substrate. Still further, the CHF in step three of the present embodiment3And O2Middle O2In an amount less than CHF3The content refers to volume content.
And fourthly, etching the silicon substrate along the hard mask pattern to form a groove with a uniform side wall structure. As shown in fig. 3, fig. 3 is a schematic structural view illustrating a trench formed by etching a silicon substrate according to the present invention. Further, after the silicon substrate 01 is etched in the fourth step of this embodiment, a remaining hard mask pattern 02 is also formed on the top of the formed silicon structure 01. Still further, in the fourth step of this embodiment, the silicon substrate is etched by using a dry etching method.
Example two
The invention provides a method for improving side undercut generated by trench etching, as shown in fig. 4, fig. 4 shows a flow chart of the method for improving side undercut generated by trench etching, the method at least comprises the following steps:
providing a silicon substrate, and forming a hard mask layer on the silicon substrate; as shown in fig. 1, fig. 1 is a schematic structural view illustrating a hard mask pattern formed on a silicon substrate according to the present invention. Providing the silicon substrate 01, and then forming a hard mask layer on the silicon substrate, wherein the hard mask layer covers the upper surface of the silicon substrate.
Etching the hard mask layer until the upper surface of the silicon substrate is exposed to form a hard mask pattern; as shown in fig. 1, in the second step, a hard mask layer on the silicon substrate is etched until the upper surface of the silicon substrate 01 is exposed, so as to form the hard mask pattern 02, and the hard mask pattern 02 is used as a mask for forming a trench by subsequent etching.
Thirdly, polymers are accumulated on the upper surface of the silicon substrate, and a fillet structure is formed at the root of the hard mask graph; as shown in fig. 2, fig. 2 is a schematic structural view illustrating a polymer deposited on a silicon substrate to form a fillet structure according to the present invention. In this step III, the polymer 03 is deposited on the silicon substrate 01, and further, in this embodiment, the polymer is passed through CH in step III3F and O2And accumulating polymer on the surface of the silicon substrate. Still further, the CH in step three of this embodiment3F and O2Middle O2Is less than CH3F content, which is the volume content.
And fourthly, etching the silicon substrate along the hard mask pattern to form a groove with a uniform side wall structure. As shown in fig. 3, fig. 3 is a schematic structural view illustrating a trench formed by etching a silicon substrate according to the present invention. Further, after the silicon substrate 01 is etched in the fourth step of this embodiment, a remaining hard mask pattern 02 is also formed on the top of the formed silicon structure 01. Still further, in the fourth step of this embodiment, the silicon substrate is etched by using a dry etching method.
EXAMPLE III
The invention provides a method for improving side undercut generated by trench etching, as shown in fig. 4, fig. 4 shows a flow chart of the method for improving side undercut generated by trench etching, the method at least comprises the following steps:
providing a silicon substrate, and forming a hard mask layer on the silicon substrate; as shown in fig. 1, fig. 1 is a schematic structural view illustrating a hard mask pattern formed on a silicon substrate according to the present invention. Providing the silicon substrate 01, and then forming a hard mask layer on the silicon substrate, wherein the hard mask layer covers the upper surface of the silicon substrate.
Etching the hard mask layer until the upper surface of the silicon substrate is exposed to form a hard mask pattern; as shown in fig. 1, in the second step, a hard mask layer on the silicon substrate is etched until the upper surface of the silicon substrate 01 is exposed, so as to form the hard mask pattern 02, and the hard mask pattern 02 is used as a mask for forming a trench by subsequent etching.
Thirdly, polymers are accumulated on the upper surface of the silicon substrate, and a fillet structure is formed at the root of the hard mask graph; as shown in fig. 2, fig. 2 is a schematic structural view illustrating a polymer deposited on a silicon substrate to form a fillet structure according to the present invention. In this step three, the polymer 03 is deposited on the silicon substrate 01, and further, in this example, the passage of CHF is performed in step three3And, CH3F and O2And accumulating polymer on the surface of the silicon substrate. Still further, CHF described in step three of this embodiment3And, CH3The sum of the contents of F is more than O2The content refers to volume content.
And fourthly, etching the silicon substrate along the hard mask pattern to form a groove with a uniform side wall structure. As shown in fig. 3, fig. 3 is a schematic structural view illustrating a trench formed by etching a silicon substrate according to the present invention. Further, after the silicon substrate 01 is etched in the fourth step of this embodiment, a remaining hard mask pattern 02 is also formed on the top of the formed silicon structure 01. Still further, in the fourth step of this embodiment, the silicon substrate is etched by using a dry etching method.
In summary, the polymer is accumulated at the root of the hard mask pattern on the silicon substrate, so that the structure of the side wall of the trench formed by etching is uniform, and the phenomenon of side undercut of the side wall of the trench is avoided. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (9)
1. A method for improving side undercut generated by trench etching is characterized by at least comprising the following steps:
providing a silicon substrate, and forming a hard mask layer on the silicon substrate;
etching the hard mask layer until the upper surface of the silicon substrate is exposed to form a hard mask pattern;
thirdly, polymers are accumulated on the upper surface of the silicon substrate, and a fillet structure is formed at the root of the hard mask graph;
and fourthly, etching the silicon substrate along the hard mask pattern to form a groove with a uniform side wall structure.
2. The method for improving the undercut generation by trench etching as claimed in claim 1, wherein: CHF passage in step three3And O2And accumulating polymer on the surface of the silicon substrate.
3. The method for improving the undercut generation by trench etching as claimed in claim 2, wherein: the CHF in step three3And O2Middle O2In an amount less than CHF3The content of (a).
4. The method for improving the undercut generation by trench etching as claimed in claim 1, wherein: passing CH in step three3F and O2Is deposited on the surface of the silicon substrateA polymer.
5. The method for improving the undercut generation by trench etching as claimed in claim 4, wherein: the CH in step three3F and O2Middle O2Is less than CH3The content of F.
6. The method for improving the undercut generation by trench etching as claimed in claim 1, wherein: CHF passage in step three3And, CH3F and O2And accumulating polymer on the surface of the silicon substrate.
7. The method for improving the undercut generation by trench etching as claimed in claim 6, wherein: CHF described in step three3And, CH3The sum of the contents of F is more than O2The content of (a).
8. The method for improving the undercut generation by trench etching as claimed in claim 1, wherein: and step four, after the silicon substrate is etched, the top of the formed silicon structure is provided with a residual hard mask pattern.
9. The method for improving the undercut generation by trench etching as claimed in claim 1, wherein: and etching the silicon substrate by adopting a dry etching method in the fourth step.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011344307.5A CN112420594A (en) | 2020-11-26 | 2020-11-26 | Method for improving lateral undercut generated by groove etching |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011344307.5A CN112420594A (en) | 2020-11-26 | 2020-11-26 | Method for improving lateral undercut generated by groove etching |
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| CN112420594A true CN112420594A (en) | 2021-02-26 |
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| CN202011344307.5A Pending CN112420594A (en) | 2020-11-26 | 2020-11-26 | Method for improving lateral undercut generated by groove etching |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101752290A (en) * | 2008-12-03 | 2010-06-23 | 中芯国际集成电路制造(上海)有限公司 | Method for making shallow groove insolation structure |
| US20110201205A1 (en) * | 2009-09-25 | 2011-08-18 | Sirajuddin Khalid M | Method of forming a deep trench in a substrate |
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2020
- 2020-11-26 CN CN202011344307.5A patent/CN112420594A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101752290A (en) * | 2008-12-03 | 2010-06-23 | 中芯国际集成电路制造(上海)有限公司 | Method for making shallow groove insolation structure |
| US20110201205A1 (en) * | 2009-09-25 | 2011-08-18 | Sirajuddin Khalid M | Method of forming a deep trench in a substrate |
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Application publication date: 20210226 |
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