CN112397029A - Pixel driving circuit and LTPO display panel - Google Patents
Pixel driving circuit and LTPO display panel Download PDFInfo
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- CN112397029A CN112397029A CN202011284186.XA CN202011284186A CN112397029A CN 112397029 A CN112397029 A CN 112397029A CN 202011284186 A CN202011284186 A CN 202011284186A CN 112397029 A CN112397029 A CN 112397029A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
Abstract
The pixel driving circuit forms modulation grids of thin film transistors in a compensation unit and a reset unit which are connected with a control end of a driving unit through a modulation unit, leads out modulation leads from each modulation grid, leads in modulation voltage through the modulation leads, applies the modulation voltage to each modulation grid, and compensates threshold voltages of the thin film transistors in the compensation unit and the reset unit by adjusting the modulation voltage. When the thin film transistors in the compensation unit and the reset unit of the pixel circuit of the LTPO display panel adopt oxide thin film transistors, the pixel driving circuit can be used for compensating the threshold voltage of the thin film transistors in the compensation unit and the reset unit, reducing the leakage current of the thin film transistors in the compensation unit and the reset unit, improving the stability of the control end of the driving unit and further improving the display uniformity.
Description
Technical Field
The present application relates to the field of display technologies, and in particular, to a pixel driving circuit and an LTPO display panel.
Background
The low temperature poly-silicon oxide (LTPO) display technology combines two thin film transistors, i.e., low temperature poly-silicon (LTPS) and Indium Gallium Zinc Oxide (IGZO), so that the display panel has both strong driving capability and low power consumption, is suitable for both high frequency display and low frequency display, and has become more and more popular in the display panel.
In the LTPO display panel, the IGZO thin film transistor has lower mobility and smaller leakage current than the LTPS thin film transistor, so the IGZO thin film transistor is usually used as a thin film transistor at a position where leakage is likely to occur in the pixel driving circuit, for example, the thin film transistor connected to the gate of the driving thin film transistor, to prevent electric charges on the gate of the driving thin film transistor from leaking away during low-frequency driving, so that the pixel driving circuit is suitable for low-frequency driving, and power consumption of the display panel is reduced.
However, in the manufacturing process of the LTPO display panel, the IGZO thin film transistor is easily affected by the LTPS thin film transistor manufacturing process to cause threshold voltage drift, which increases leakage current and affects the stability of the driving thin film transistor; in addition, since the threshold voltage shifts of the tfts of different pixels in different LTPO display panels are different, it is difficult to solve the threshold voltage shifts in different degrees by using the same pixel driving circuit.
Therefore, it is necessary to provide a pixel driving circuit suitable for an LTPO display panel, which can modulate the IGZO thin film transistors according to the threshold voltage shift conditions of different levels of the thin film transistors of different pixels in the LTPO display panel, so as to reduce the leakage current of the IGZO thin film transistors and improve the uniformity of the display panel.
Disclosure of Invention
In order to be able to compensate for the threshold voltage drift of the IGZO thin film transistor in the LTPO display panel, the present application provides a pixel driving circuit including: the device comprises a driving unit, a data writing unit, a compensation unit, a reset unit, a modulation unit and a light-emitting device;
the control end of the driving unit is connected with a first node, the input end of the driving unit is connected with a constant-voltage high potential through a second node, and the output end of the driving unit is connected with a third node;
the control end of the data writing unit is connected with a first scanning signal line, the input end of the data writing unit is connected with a data signal line, and the output end of the data writing unit is connected with the second node;
the control end of the compensation unit is connected with a second scanning signal line, the input end of the compensation unit is connected with the first node, and the output end of the compensation unit is connected with the third node;
the control end of the reset unit is connected with a reset signal line, the input end of the reset unit is connected with the reset signal line, and the output end of the reset unit is connected with a reference signal line;
the anode of the light-emitting device is connected with the third node, and the cathode of the light-emitting device is connected with a constant voltage low potential;
the modulation unit is used for forming modulation grids of the thin film transistors in the compensation unit and the reset unit respectively, and a modulation lead is led out from each modulation grid respectively and used for leading modulation voltage to be applied to each modulation grid so as to compensate the threshold voltage of the thin film transistors in the reset unit and the compensation unit.
In some embodiments, the modulation lead is used for introducing a modulation signal line or connecting the reference signal line and introducing the modulation voltage through the modulation signal line or the reference signal line.
In some embodiments, the magnitude of the modulation voltage is proportional to the amount of drift of the threshold voltage.
In some embodiments, the pixel driving circuit further includes a first light emission control unit and a second light emission control unit; the control end of the first light-emitting control unit and the control end of the second light-emitting control unit are respectively connected with a light-emitting signal line, the input end of the first light-emitting control unit is connected with the constant-voltage high potential, the output end of the first light-emitting control unit is connected with the second node, the input end of the second light-emitting control unit is connected with the third node, and the output end of the second light-emitting control unit is connected with the anode of the light-emitting device.
In some embodiments, the pixel driving circuit further includes a reset unit, a control terminal of the reset unit is connected to the third scanning signal line, an input terminal of the reset unit is connected to the reference signal line, and an output terminal of the reset unit is connected to the anode of the light emitting device.
In some embodiments, the pixel driving circuit further includes an energy storage capacitor, a first end of the energy storage capacitor is connected to a constant-voltage high potential, and a second end of the energy storage capacitor is connected to the first node.
In some embodiments, the driving unit includes a first thin film transistor, a gate of the first thin film transistor is connected to the first node, a source of the first thin film transistor is connected to the second node, and a drain of the first thin film transistor is connected to a third node.
The data writing unit comprises a second thin film transistor, the source electrode of the second thin film transistor is connected with the first scanning signal line, the source electrode of the second thin film transistor is connected with the data signal line, and the drain electrode of the second thin film transistor is connected with the second node.
The compensation unit comprises a third thin film transistor, the grid electrode of the third thin film transistor is connected with the second scanning signal line, the modulation grid electrode of the third thin film transistor is connected with the modulation lead wire, the source electrode of the third thin film transistor is connected with the first node, and the drain electrode of the third thin film transistor is connected with the third node.
The reset unit comprises a fourth thin film transistor, the grid electrode of the fourth thin film transistor is connected with the reset signal line, the modulation grid electrode of the fourth thin film transistor is connected with the modulation lead wire, the source electrode of the fourth thin film transistor is connected with the reference signal line, and the drain electrode of the fourth thin film transistor is connected with the first node.
The first light emission control unit includes a fifth thin film transistor, the second light emission control unit includes a sixth thin film transistor, a gate of the fifth thin film transistor and a gate of the sixth thin film transistor are connected to the light emission signal line, a source of the fifth thin film transistor is connected to the constant voltage high potential, a drain of the fifth thin film transistor is connected to the second node, a source of the sixth thin film transistor is connected to the third node, and a drain of the sixth thin film transistor is connected to an anode of the light emitting device.
The reset unit comprises a seventh thin film transistor, the grid electrode of the seventh thin film transistor is connected with the third scanning signal line, the source electrode of the seventh thin film transistor is connected with the reference signal line, and the drain electrode of the seventh thin film transistor is connected with the anode of the light-emitting device.
In some embodiments, the third thin film transistor and the fourth thin film transistor are oxide thin film transistors, and the first thin film transistor, the second thin film transistor, the fifth thin film transistor, the sixth thin film transistor, and the seventh thin film transistor are low temperature polysilicon thin film transistors.
In some embodiments, the gate of the first thin film transistor, the gate of the second thin film transistor, the gate of the fifth thin film transistor, the gate of the sixth thin film transistor, the gate of the seventh thin film transistor, and the first electrode plate of the energy storage capacitor are located in a first layer, the second electrode plate of the energy storage capacitor, the modulation gate of the third thin film transistor, the modulation gate of the fourth thin film transistor, the modulation lead, and the modulation signal line are located in a second layer, the gate of the third thin film transistor and the gate of the fourth thin film transistor are located in a third layer, and the first layer, the second layer, and the third layer are sequentially disposed from bottom to top.
The gate of the third thin film transistor and the modulation gate of the third thin film transistor are oppositely arranged above and below the oxide semiconductor layer of the third thin film transistor, and the gate of the fourth thin film transistor and the modulation gate of the fourth thin film transistor are oppositely arranged above and below the oxide semiconductor layer of the fourth thin film transistor.
In some embodiments, the modulation lead and the reference signal line are arranged in different layers, and the modulation lead is connected with the reference signal line through a trace and a via.
In some embodiments, the first, second, fifth, sixth, and seventh thin film transistors are P-type thin film transistors, and the third and fourth thin film transistors are N-type thin film transistors.
In some embodiments, the first scan signal line, the second scan signal line, the third scan signal line, the reset signal line, and the light emitting signal line are commonly used in a reset phase, a compensation phase, and a light emitting phase of the pixel driving circuit.
In the reset phase, the first scan signal line, the reset signal line, and the light emitting signal line are at a high level, and the second scan signal line, the third scan signal line, and the data are at a low level.
In the compensation phase, the second scanning signal line, the third scanning signal line and the light emitting signal line are at a high level, and the first scanning signal line and the reset signal line are at a low level; the compensation stage is used for detecting the threshold voltage of the first thin film transistor, and the threshold voltage drift amount of the first thin film transistor, the threshold voltage drift amount of the third thin film transistor and the threshold voltage drift amount of the fourth thin film transistor are the same.
In the light emission phase, the first scanning signal line, the second scanning signal line, the third scanning signal line, and the reset signal line are at a low level, and the light emission signal line is at a high level.
In addition, the present application also provides an LTPO display panel including a source driver and the pixel driving circuit as described above, the source driver being connected to the modulation signal line or the reference signal line and introducing the modulation voltage to the modulation lead line through the modulation signal line or the reference signal line.
In some embodiments, the plurality of modulation signal lines or the plurality of reference signal lines are horizontally disposed on the display panel and are connected to the source driver after being converged at a side surface of the display panel by using a lead, and each modulation signal line or each reference signal line is used for modulating a corresponding row of pixels.
In some embodiments, the modulation voltage introduced into the modulation lead by the source driver through the modulation signal line is between 0 and-8V, and the modulation voltage introduced into the modulation lead by the source driver through the reference signal line is between-2V and-4V.
In the pixel driving circuit and the LTPO display panel provided by the application, the pixel driving circuit comprises a driving unit for driving the light-emitting device to emit light, and a compensation unit and a reset unit which are connected with a control end of the driving unit, in order to avoid the problem that the threshold voltage of the thin film transistors in the compensation unit and the reset unit drifts to increase the leakage current of the thin film transistors in the compensation unit and the reset unit, the pixel driving circuit further comprises a modulation unit, the modulation unit is used for forming the modulation grid electrodes of the thin film transistors in the compensation unit and the reset unit, leading out a modulation lead wire from the modulation grid electrodes, leading in a modulation voltage through the modulation lead wire to be applied to the modulation grid electrodes, and compensating the threshold voltage of the thin film transistors in the compensation unit and the reset unit by adjusting the magnitude of the modulation voltage. The pixel driving circuit is suitable for an LTPO display panel, when thin film transistors in a compensation unit and a reset unit of a pixel circuit of the LTPO display panel adopt oxide thin film transistors, and other units adopt low-temperature polycrystalline silicon thin film transistors, the pixel driving circuit can be used for compensating the threshold voltages of the thin film transistors in the compensation unit and the reset unit, reducing the leakage current of the thin film transistors in the compensation unit and the reset unit, improving the stability of a control end of the driving unit and further improving the display uniformity.
Drawings
The technical solution and other advantages of the present application will become apparent from the detailed description of the embodiments of the present application with reference to the accompanying drawings.
Fig. 1 is a schematic diagram of a first general structure of a pixel driving circuit according to an embodiment of the present disclosure.
Fig. 2 is a schematic diagram of a second general structure of a pixel driving circuit according to an embodiment of the present disclosure.
Fig. 3 is a schematic diagram of a first specific structure of a pixel driving circuit according to an embodiment of the present disclosure.
Fig. 4 is a schematic diagram of a second specific structure of a pixel driving circuit according to an embodiment of the present disclosure.
Fig. 5 is a timing diagram of a pixel driving circuit according to an embodiment of the present disclosure.
Fig. 6 is a schematic view of layout of a pixel driving circuit according to an embodiment of the present disclosure.
Fig. 7 is a schematic cross-sectional view of an LTPO display panel according to an embodiment of the present disclosure.
Fig. 8 is a schematic layout diagram of modulation signal lines or reference signal lines in an LTPO display panel according to an embodiment of the present disclosure.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In all embodiments of the present application, two electrodes of the thin film transistor except for the gate electrode are distinguished, one of the two electrodes is referred to as a source electrode, and the other electrode is referred to as a drain electrode. Since the source and drain electrodes of the thin film transistor are symmetrical, the source and drain electrodes thereof are interchangeable. The form in the drawing stipulates that the middle end of the thin film transistor is a grid electrode, a signal input end is a source electrode, and a signal output end is a drain electrode. In addition, the thin film transistors adopted in all the embodiments of the present application may include two types, i.e., P-type and/or N-type transistors, wherein the P-type thin film transistor is turned on when the gate is at a low potential and turned off when the gate is at a high potential; the N-type thin film transistor is turned on when the grid is at a high potential and turned off when the grid is at a low potential.
Fig. 1 is a schematic diagram of a first general structure of a pixel driving circuit according to an embodiment of the present disclosure, and as shown in fig. 1, the pixel driving circuit includes: a driving unit 100, a data writing unit 200, a compensation unit 300, a reset unit 400, a modulation unit 800, and a light emitting device OLED.
The control end of the driving unit 100 is connected to the first node a, the input end of the driving unit 100 is connected to the constant voltage high potential Vdd through the second node B, and the output end of the driving unit 100 is connected to the third node C.
The control terminal of the Data writing unit 200 is connected to the first Scan signal line Scan1, the input terminal of the Data writing unit 200 is connected to the Data signal line Data, and the output terminal of the Data writing unit 200 is connected to the second node B.
The control terminal of the compensation unit 300 is connected to the second Scan signal line Scan2, the input terminal of the compensation unit 300 is connected to the first node a, and the output terminal of the compensation unit 300 is connected to the third node C.
The control end of the Reset unit 400 is connected to the Reset signal line Reset, the input end of the Reset unit 400 is connected to the Reset signal line Reset, and the output end of the Reset unit 400 is connected to the reference signal line Vi.
The control terminal of the reset unit 700 is connected to the third Scan signal line Scan3, the input terminal of the reset unit 700 is connected to the reference signal line Vi, the output terminal of the reset unit 700 is connected to the anode of the light emitting device OLED and the third node C, and the cathode of the light emitting device OLED is connected to the constant voltage low potential Vss.
The modulation unit 800 is used for forming modulation gates 801 of the thin film transistors in the compensation unit 300 and in the reset unit 400 respectively and a modulation lead 802 led out from each modulation gate 801 respectively, and the modulation lead 802 is used for leading a modulation voltage to be applied to each modulation gate 801 so as to compensate the threshold voltage of the thin film transistors in the compensation unit 300 and in the reset unit 400.
In the pixel driving circuit provided in the embodiment of the present application, the modulation unit 800 adds the modulation gate 801 in the thin film transistor of the reset unit 400 and the thin film transistor of the compensation unit 300, and leads out the modulation lead 802 from each modulation gate 801, the modulation lead 802 leads in a modulation voltage from the outside and applies the modulation voltage to the modulation gate 801, and adjusts the voltage on the modulation gate 801 by adjusting the magnitude of the modulation voltage, so as to compensate for the threshold voltages of the thin film transistor of the reset unit 400 and the thin film transistor of the compensation unit 300, thereby preventing the leakage currents of the compensation unit 300 and the reset unit 400 from becoming large, causing the leakage of the charge at the control end of the driving unit 100 to make the luminances of the light emitting devices OLED in different pixels different, and affecting the stability of the control end of the driving unit 100, so as to affect the display uniformity.
The pixel driving circuit obtains the threshold voltage shift of the thin film transistors in the compensation unit 300 and the reset unit 400 connected to the control terminal of the driving unit 100 according to the threshold voltage shift of the thin film transistors in the driving unit 100 based on the fact that the shift of the thin film transistors in the pixels of the same display panel is basically the same.
Based on the foregoing embodiment, fig. 2 is a schematic diagram of a second general structure of a pixel driving circuit provided in the embodiment of the present application, and as shown in fig. 2, the pixel driving circuit further includes a first light-emitting control unit and a second light-emitting control unit; the control end of the first light-emitting control unit 500 and the control end of the second light-emitting control unit 600 are both connected to the light-emitting signal line EM, the input end of the first light-emitting control unit 500 is connected to the constant-voltage high-potential Vdd, the output end of the first light-emitting control unit 500 is connected to the second node B, the input end of the second light-emitting control unit 600 is connected to the third node C, and the output end of the second light-emitting control unit 600 is connected to the anode of the light-emitting device OLED.
Further, as shown in fig. 2, the pixel driving circuit further includes a reset unit 700, a control terminal of the reset unit 700 is connected to the third scanning signal line, an input terminal of the reset unit 700 is connected to the reference signal line Vi, and an output terminal of the reset unit 700 is connected to the anode of the light emitting device.
Further, as shown in fig. 2, the pixel driving circuit further includes an energy storage capacitor Cst, a first end of the energy storage capacitor Cst is connected to the constant voltage high potential Vdd, and a second end of the energy storage capacitor Cst is connected to the first node a. The storage capacitor Cst can be used to compensate for a threshold voltage of the thin film transistor in the driving unit, and a specific compensation process is described in the following description of the working process of the pixel driving circuit.
Based on the foregoing embodiment, fig. 3 is a schematic diagram of a first specific structure of a pixel driving circuit provided in the embodiment of the present application, fig. 4 is a schematic diagram of a second specific structure of the pixel driving circuit provided in the embodiment of the present application, fig. 3 is a schematic diagram of introducing a modulation signal line into a modulation lead 802, and fig. 4 is a schematic diagram of connecting the modulation lead 802 to a reference signal line, as shown in fig. 3 and fig. 4, the modulation lead 802 is used for introducing a modulation signal line Vsw or connecting the reference signal line Vi, and introducing a modulation voltage through the modulation signal line Vsw or the reference signal line Vi.
It can be understood that if the modulation lead 802 is used to introduce the modulation signal line Vsw, the modulation voltage introduced by the modulation signal line Vsw needs to be separately set, and if the modulation lead 802 is connected to the reference signal line Vi, the modulation voltage can be introduced directly via the reference signal line Vi without separately setting a special signal line, but since the reference signal line Vi also needs to provide the reference signal Vi for reset, the range of the modulation voltage that can be introduced by the modulation signal line Vsw is larger than that introduced by the reference signal line Vi, and a wider threshold voltage drift amount can be compensated.
In some embodiments, the driving unit 100 includes a first thin film transistor T1, a gate of the first thin film transistor T1 is connected to the first node a, a source of the first thin film transistor T1 is connected to the second node B, and a drain of the first thin film transistor T1 is connected to the third node C.
The Data writing unit 200 includes a second thin film transistor T2, a source of the second thin film transistor T2 is connected to the first Scan signal line Scan1, a source of the second thin film transistor T2 is connected to the Data signal line Data, and a drain of the second thin film transistor T2 is connected to the second node B.
The compensation unit 300 includes a third thin film transistor T3, a gate of the third thin film transistor T3 is connected to the second Scan signal line Scan2, a modulation gate 801 of the third thin film transistor T3 is connected to the modulation lead 802, a source of the third thin film transistor T3 is connected to the first node a, and a drain of the third thin film transistor T3 is connected to the third node C.
The Reset unit 400 includes a fourth thin film transistor T4, a gate of the fourth thin film transistor T4 connected to a Reset signal line Reset, a modulation gate 801 of the fourth thin film transistor T4 connected to a modulation lead 802, a source of the fourth thin film transistor T4 connected to a reference signal line Vi, and a drain of the fourth thin film transistor T4 connected to the first node a.
The first light emission control unit 500 includes a fifth thin film transistor T5, the second light emission control unit 600 includes a sixth thin film transistor T6, a gate of the fifth thin film transistor T5 and a gate of the sixth thin film transistor T6 are connected to the light emission signal line EM, a source of the fifth thin film transistor T5 is connected to the constant voltage high potential Vdd, a drain of the fifth thin film transistor T5 is connected to the second node B, a source of the sixth thin film transistor T6 is connected to the third node C, and a drain of the sixth thin film transistor T6 is connected to an anode of the light emitting device OLED.
The reset unit 700 includes a seventh thin film transistor T7, a gate of the seventh thin film transistor T7 is connected to the third Scan signal line Scan3, a source of the seventh thin film transistor T7 is connected to the reference signal line Vi, and a drain of the seventh thin film transistor T7 is connected to the anode of the light emitting device OLED.
The pixel driving circuit provided in the embodiment of the application obtains the threshold voltage shift conditions of the third thin film transistor T3 and the fourth thin film transistor T4 connected to the gate of the first thin film transistor T1 according to the threshold voltage shift conditions of the first thin film transistor T1 based on that the shift conditions of the thin film transistors in the pixels of the same display panel are substantially the same, introduces a modulation voltage to the modulation gate 801 of the third thin film transistor T3 and the modulation gate 801 of the fourth thin film transistor T4 through the modulation lead 802 of the modulation unit 800, and adjusts the voltage of the modulation gate 801 by adjusting the magnitude of the modulation voltage, so as to compensate the threshold voltages of the third thin film transistor T3 and the fourth thin film transistor T4, so as to prevent the leakage currents of the third thin film transistor T3 and the fourth thin film transistor T4 from becoming large and causing the charge leakage of the first thin film transistor T1, therefore, the brightness of the light emitting devices OLED in different pixels is different, and the brightness of the display panel is different.
The magnitude of the modulation voltage is proportional to the amount of drift of the threshold voltage. Specifically, since the thin film transistor in the pixel is in an off state for a long time, the gate voltage is generally in a negative bias state, and the threshold voltage is generally in a negative drift state. When the threshold voltages of the third thin film transistor T3 and the fourth thin film transistor T4 drift in the negative direction, in order to compensate for the threshold voltages of the third thin film transistor T3 and the fourth thin film transistor T4, the voltage of the modulation gate 801 of the third thin film transistor T3 and the fourth thin film transistor T4 needs to be lowered, that is, a negative modulation voltage is applied to the modulation lead 802 to achieve a positive recovery of the threshold voltages of the third thin film transistor T3 and the fourth thin film transistor T4, so that the leakage currents of the third thin film transistor T3 and the fourth thin film transistor T4 are reduced to improve the display uniformity, that is, in an ideal state, the modulation voltage applied to the modulation gate 801 of the third thin film transistor T3 and the fourth thin film transistor T4 is proportional to the drift amount of the threshold voltages.
Based on the above embodiments, if the pixel driving circuit is applied to the LTPO display panel, the portion of the pixel driving circuit that is easy to leak current is made of oxide (IGZO) thin film transistors, and the rest of the pixel driving circuit is still made of Low Temperature Polysilicon (LTPS) thin film transistors to maintain strong driving capability, for example, the third thin film transistor T3 and the fourth thin film transistor T4 are made of oxide thin film transistors, and the first thin film transistor T1, the second thin film transistor T2, the fifth thin film transistor T5, the sixth thin film transistor T6, and the seventh thin film transistor T7 are made of low temperature polysilicon thin film transistors.
Fig. 6 is a layout diagram of a pixel driving circuit according to an embodiment of the present disclosure, and as shown in fig. 6, a modulation lead 802 and a modulation signal line Vsw are laid below the third thin film transistor and the fourth thin film transistor and led out from the modulation gates of the third thin film transistor and the fourth thin film transistor; fig. 7 is a schematic cross-sectional view of an LTPO display panel according to an embodiment of the present invention, as shown in fig. 7, with LTPS tfts on the left and IGZO tfts on the right.
Specifically, in the pixel driving circuit, the gate of the first thin film transistor T1, the gate of the second thin film transistor T2, the gate of the fifth thin film transistor T5, the gate of the sixth thin film transistor T6, the gate of the seventh thin film transistor T7, and the first plate of the storage capacitor Cst are located in a first layer (GE1 layer), the second plate of the storage capacitor Cst, the modulation gate 801 of the third thin film transistor T3, the modulation gate 801 of the fourth thin film transistor T4, the modulation lead 802, and the modulation signal line Vsw are located in a second layer (GE2 layer), the gate of the third thin film transistor T3, and the gate of the fourth thin film transistor T4 are located in a third layer (GE3 layer), and the first layer, the second layer, and the third layer are sequentially disposed from bottom to top.
The gate electrode of the third thin film transistor T3 and the modulation gate electrode 801 of the third thin film transistor T3 are disposed above and below the oxide semiconductor layer (IGZO layer) of the third thin film transistor T3 with respect to each other, and the gate electrode of the fourth thin film transistor T4 and the modulation gate electrode 801 of the fourth thin film transistor T4 are disposed above and below the oxide semiconductor layer (IGZO layer) of the fourth thin film transistor T4 with respect to each other.
In the film structure of the pixel driving circuit provided in the embodiment of the application, a threshold voltage modulation layer (a GE2 portion below the IGZO layer) is provided on the GE2 layer below the IGZO layer of the third thin film transistor T3 and the fourth thin film transistor T4, and the threshold voltage modulation layer includes the modulation gate 801 of the third thin film transistor T3, the modulation gate 801 of the fourth thin film transistor T4, the modulation lead 802, and the modulation signal line Vsw (the GE2 portion above the GE1 is a second plate of the storage capacitor Cst). The third thin film transistor T3 and the fourth thin film transistor T4 have their own gate as a top gate and their own modulation gate as a bottom gate, so that the third thin film transistor T3 and the fourth thin film transistor T4 form a dual-gate thin film transistor, and according to the characteristic that the top gate and the top gate of the dual-gate thin film transistor can be controlled individually, the top gate is connected to the gate of the driving thin film transistor, i.e., the first thin film transistor T1, and the bottom gate is connected to the modulation lead, and a modulation voltage is introduced to the bottom gate through the modulation lead to adjust the voltage of the bottom gate, thereby compensating the drift of the threshold voltage.
In fact, the third thin film transistor T3 and the fourth thin film transistor T4 may also directly adopt a double-gate transistor, so as to omit the manufacturing process of the modulation gate in the modulation unit, that is, the modulation unit does not need to form the bottom gates of the third thin film transistor T3 and the fourth thin film transistor T4, and only needs to draw out the modulation lead from the bottom gates of the third thin film transistor T3 and the fourth thin film transistor T4.
In some embodiments, the modulation lead 802 and the reference signal line Vi are arranged in different layers, and the modulation lead 802 is connected with the reference signal line Vi through a trace and a via.
Based on the foregoing embodiments, fig. 5 is a timing diagram of the pixel driving circuit provided in the embodiments of the present application, and as shown in fig. 5, taking the first thin film transistor T1, the second thin film transistor T2, the fifth thin film transistor T5, the sixth thin film transistor T6, and the seventh thin film transistor T7 as P-type thin film transistors, and taking the third thin film transistor T3 and the fourth thin film transistor T4 as N-type thin film transistors as examples, the first Scan signal line Scan1, the second Scan signal line Scan2, the third Scan signal line Scan3, the Reset signal line Reset, and the light-emitting signal line EM are commonly applied to the Reset stage T1, the compensation stage T2, and the light-emitting stage T3 of the pixel driving circuit, and the operation process of the pixel driving circuit is explained in detail as follows:
in the Reset period T1, the first Scan signal line Scan1, the Reset signal line Reset, and the light emitting signal line EM are at a high level, the second Scan signal line Scan2, the third Scan signal line Scan3, and the data are at a low level, at this time, the second thin film transistor T2, the third thin film transistor T3, the fifth thin film transistor T5, and the sixth thin film transistor T6 are turned off, the fourth thin film transistor T4, and the seventh thin film transistor T7 are turned on, and the reference voltage line applies the reference voltage Vi to the first node a.
In the compensation period t2, the second Scan signal line Scan2, the third Scan signal line Scan3 and the light emitting signal line EM are at a high level, the first Scan signal line Scan1 and the Reset signal line Reset are at a low level, and at this time, the fourth thin film transistor T4, the fifth thin film transistor T5, the sixth thin film transistor T6, and the seventh thin film transistor T7 are turned off, the first thin film transistor T1, the second thin film transistor T2, and the third thin film transistor T3 are turned on, the Data signal line Data charges the first node a through the second thin film transistor T2, the first thin film transistor T1, and the third thin film transistor T3 until the charging is completed when the voltage of the first node a is Vdata + Vth, thereby completing the extraction of the threshold voltage Vth of the first thin film transistor T1 and the writing of the data voltage Vdata, where the voltage value on the storage capacitor is Vdata + Vth-Vdd, i.e. the threshold voltage Vth of the first thin film transistor T1 is stored in the storage capacitor.
It is understood that the compensation phase T2 is for detecting the threshold voltage of the first thin film transistor T1, so that the threshold voltage shift amount of the first thin film transistor T1 can be acquired according to the variation of the threshold voltage of the first thin film transistor T1. Based on that the drift conditions of the tfts in the pixels of the same display panel are substantially the same, the threshold voltage drift amount of the third tft T3 and the threshold voltage drift amount of the fourth tft T4 can be known from the threshold voltage drift amount of the first tft T1.
In the light emitting period t3, the first Scan signal line Scan1, the second Scan signal line Scan2, the third Scan signal line Scan3, and the Reset signal line Reset are at a low level, and the light emitting signal line EM is at a high level. At this time, the second thin film transistor T2, the third thin film transistor T3, the fourth thin film transistor T4 and the seventh thin film transistor T7 are turned off, the first thin film transistor T1, the fifth thin film transistor T5 and the sixth thin film transistor T6 are turned on, and the gate-source voltage difference of the first thin film transistor T1 is: vgs is Vdata + Vth-Vdd, and a current I flowing through the light emitting device OLED is K (Vgs-Vth)2＝K(Vdata+Vth-Vdd-Vth)＝K(Vdata-Vdd)2And K is an intrinsic factor of the thin film transistor. It can be seen that the current I flowing through the light emitting device OLED is independent of the threshold voltage Vth of the first thin film transistor T1, and the pixel driving circuit achieves compensation for the threshold voltage Vth of the first thin film transistor T1.
It should be noted that, in the reset phase T1, the compensation phase T2 and the light emitting phase T3 of the pixel driving circuit, the modulation lead 802 continuously introduces a modulation voltage from the modulation signal line Vsw or the reference signal line Vi to the modulation gate 801, thereby adjusting the voltage of the modulation gate 801 to compensate the threshold voltage drift amount of the third thin film transistor T3 and the fourth thin film transistor T4.
Based on the above embodiments, the present embodiment also provides an LTPO display panel including the pixel driving circuit and the source driver (D-IC) as above, the source driver being connected to the modulation signal line Vsw or the reference signal line Vi, and applying a modulation voltage to the modulation gate 801 through the modulation signal line Vsw or the reference signal line Vi by introducing the modulation voltage through the modulation lead 802.
Specifically, fig. 8 is a schematic layout diagram of modulation signal lines or reference signal lines in the LTPO display panel provided in the embodiment of the present application, as shown in fig. 8, a plurality of modulation signal lines 2 or a plurality of reference signal lines 2 are horizontally disposed on the LTPO display panel 1 and are converged by a single lead 3 at a side of the LTPO display panel 1 and then connected to the source driver 4, and each modulation signal line 2 or each reference signal line 2 is used for modulating a row of pixels corresponding to the modulation signal line 2.
It should be noted that the modulation signal line Vsw may also be disposed in a vertical direction or an oblique direction on the LTPO display panel, and the horizontal disposition is only one of the preferred directions to reduce the influence on other signal lines on the LTPO display panel.
Based on the above embodiment, the modulation voltage introduced into the modulation lead 802 by the source driver through the modulation signal line Vsw is 0V to-8V, and the modulation voltage introduced into the modulation lead 802 by the source driver through the reference signal line Vi is-2V to-4V. Table 1 shows an actual relationship between the modulation voltage and the threshold voltage shift amount obtained through experiments, and as shown in table 1, it can be understood that, due to a certain error, the actual relationship between the modulation voltage and the threshold voltage shift amount does not show a strict proportional relationship, but an adjustment trend of the modulation voltage is consistent with a variation trend of the threshold voltage shift amount, and an appropriate modulation voltage can be applied to the modulation gate 801 through the modulation lead 802 according to the threshold voltage shift amount to compensate the threshold voltage shift amount.
TABLE 1
| Threshold voltage drift amount (V) | Modulating voltage (V) |
| -1 | 0 |
| -2 | -2.5 |
| -3 | -4.2 |
| -4 | -5.8 |
| -5 | -6.5 |
The LTPO display panel provided by the embodiment of the application can apply the pixel driving circuit to the LTPO display panel, and when the thin film transistors in the compensation unit 300 and the reset unit 400 of the pixel circuit of the LTPO display panel adopt oxide thin film transistors and other units adopt low temperature polysilicon thin film transistors, the pixel driving circuit can be used for compensating the threshold voltages of the thin film transistors in the compensation unit 300 and the reset unit 400, so as to prevent the leakage currents of the thin film transistors in the compensation unit 300 and the reset unit 400 from becoming large and affecting the display uniformity. And, according to the threshold voltage drift condition of each LTPO display panel, each LTPO display panel can be independently modulated, thereby improving the display quality.
Based on the above embodiments, as shown in fig. 7, when the pixel driving circuit is applied to an LTPO display panel, the manufacturing process of the LTPO display panel is as follows:
providing a glass substrate Base, and sequentially depositing PI1, Buffer1, PI2, Buffer2 and 3layer on the glass substrate Base.
Continuing to deposit poly-si on the substrate
The semiconductor layer pattern is formed through a photolithography process.
And continuing to deposit GI1 and a Gate1 layer on the substrate, and then performing a photoetching process to form a GE1 pattern.
And continuing to deposit GI2 and a Gate2 layer on the substrate, and then performing a photolithography process to form a GE2 pattern and a threshold voltage modulation layer.
A layer of ILD1 continues to be deposited on the substrate. The ILD1 holes are formed using photolithography and dry etching.
The IGZO semiconductor layer is successively deposited on the above substrate, and a semiconductor pattern is formed by photolithography.
Deposition of a GI 3layer, deposition of a Gate 3layer thereon, and patterning of GE3 by photolithography was continued on the above substrate.
Continuing to deposit a layer of ILD2 on the substrate, an ILD2 hole is formed using photolithography and dry etching.
And continuously depositing an SD1 layer on the substrate, and forming a data pattern by utilizing photoetching and wet etching.
A PV layer is deposited thereon and a PV aperture is formed by photolithography and dry etching.
Continuing to deposit a layer of PLN1 on the substrate, photolithography was used to form PLN1 holes.
Continuing to deposit a layer of SD2 on the substrate, a pattern of SD2 was formed using photolithography and wet etching.
Continuing to deposit a layer of PLN2 on the substrate, photolithography was used to form PLN2 holes.
The ITO/Ag/ITO anode layer was deposited on the substrate.
The pixel definition layer PDL and the PS layer continue to be produced on the above substrate.
In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
The above description of the embodiments is only for assisting understanding of the technical solutions and the core ideas thereof; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications or substitutions do not depart from the spirit and scope of the present disclosure as defined by the appended claims.
Claims (15)
1. A pixel driving circuit is characterized by comprising a driving unit, a data writing unit, a compensation unit, a reset unit, a modulation unit and a light-emitting device;
the control end of the driving unit is connected with a first node, the input end of the driving unit is connected with a constant-voltage high potential through a second node, and the output end of the driving unit is connected with a third node;
the control end of the data writing unit is connected with a first scanning signal line, the input end of the data writing unit is connected with a data signal line, and the output end of the data writing unit is connected with the second node;
the control end of the compensation unit is connected with a second scanning signal line, the input end of the compensation unit is connected with the first node, and the output end of the compensation unit is connected with the third node;
the control end of the reset unit is connected with a reset signal line, the input end of the reset unit is connected with the reset signal line, and the output end of the reset unit is connected with a reference signal line;
the anode of the light-emitting device is connected with the third node, and the cathode of the light-emitting device is connected with a constant voltage low potential;
the modulation unit is used for forming modulation grids of the thin film transistors in the compensation unit and the reset unit respectively, and a modulation lead is led out from each modulation grid respectively and used for leading modulation voltage to be applied to each modulation grid so as to compensate the threshold voltage of the thin film transistors in the reset unit and the compensation unit.
2. The pixel driving circuit according to claim 1, wherein the modulation lead is used to introduce a modulation signal line or connect to the reference signal line and introduce the modulation voltage through the modulation signal line or the reference signal line.
3. The pixel driving circuit according to claim 1, wherein the magnitude of the modulation voltage is proportional to the amount of drift of the threshold voltage.
4. The pixel driving circuit according to claim 1, wherein the pixel driving circuit further comprises a first light emission control unit and a second light emission control unit;
the control end of the first light-emitting control unit and the control end of the second light-emitting control unit are respectively connected with a light-emitting signal line, the input end of the first light-emitting control unit is connected with the constant-voltage high potential, the output end of the first light-emitting control unit is connected with the second node, the input end of the second light-emitting control unit is connected with the third node, and the output end of the second light-emitting control unit is connected with the anode of the light-emitting device.
5. The pixel driving circuit according to claim 4, further comprising a reset unit, wherein a control terminal of the reset unit is connected to a third scan signal line, an input terminal of the reset unit is connected to the reference signal line, and an output terminal of the reset unit is connected to an anode of the light emitting device.
6. The pixel driving circuit according to claim 5, further comprising an energy storage capacitor, wherein a first terminal of the energy storage capacitor is connected to a high constant voltage potential, and a second terminal of the energy storage capacitor is connected to the first node.
7. The pixel driving circuit according to claim 6, wherein the driving unit comprises a first thin film transistor, a gate of the first thin film transistor is connected to the first node, a source of the first thin film transistor is connected to the second node, and a drain of the first thin film transistor is connected to a third node;
the data writing unit comprises a second thin film transistor, the source electrode of the second thin film transistor is connected with the first scanning signal line, the source electrode of the second thin film transistor is connected with the data signal line, and the drain electrode of the second thin film transistor is connected with the second node;
the compensation unit comprises a third thin film transistor, the grid electrode of the third thin film transistor is connected with the second scanning signal line, the modulation grid electrode of the third thin film transistor is connected with the modulation lead wire, the source electrode of the third thin film transistor is connected with the first node, and the drain electrode of the third thin film transistor is connected with the third node;
the reset unit comprises a fourth thin film transistor, the grid electrode of the fourth thin film transistor is connected with the reset signal line, the modulation grid electrode of the fourth thin film transistor is connected with the modulation lead wire, the source electrode of the fourth thin film transistor is connected with the reference signal line, and the drain electrode of the fourth thin film transistor is connected with the first node;
the first light emission control unit includes a fifth thin film transistor, the second light emission control unit includes a sixth thin film transistor, a gate of the fifth thin film transistor and a gate of the sixth thin film transistor are connected to the light emission signal line, a source of the fifth thin film transistor is connected to the constant voltage high potential, a drain of the fifth thin film transistor is connected to the second node, a source of the sixth thin film transistor is connected to the third node, and a drain of the sixth thin film transistor is connected to an anode of the light emitting device;
the reset unit comprises a seventh thin film transistor, the grid electrode of the seventh thin film transistor is connected with the third scanning signal line, the source electrode of the seventh thin film transistor is connected with the reference signal line, and the drain electrode of the seventh thin film transistor is connected with the anode of the light-emitting device.
8. The pixel driving circuit according to claim 7, wherein the third thin film transistor and the fourth thin film transistor are each an oxide thin film transistor, and wherein the first thin film transistor, the second thin film transistor, the fifth thin film transistor, the sixth thin film transistor, and the seventh thin film transistor are each a low temperature polysilicon thin film transistor.
9. The pixel driving circuit according to claim 8, wherein a gate of the first thin film transistor, a gate of the second thin film transistor, a gate of the fifth thin film transistor, a gate of the sixth thin film transistor, a gate of the seventh thin film transistor, and a first plate of the energy storage capacitor are in a first layer, a second plate of the energy storage capacitor, a modulation gate of the third thin film transistor, a modulation gate of the fourth thin film transistor, the modulation lead, and the modulation signal line are in a second layer, a gate of the third thin film transistor and a gate of the fourth thin film transistor are in a third layer, and the first layer, the second layer, and the third layer are sequentially arranged from bottom to top;
the gate of the third thin film transistor and the modulation gate of the third thin film transistor are oppositely arranged above and below the oxide semiconductor layer of the third thin film transistor, and the gate of the fourth thin film transistor and the modulation gate of the fourth thin film transistor are oppositely arranged above and below the oxide semiconductor layer of the fourth thin film transistor.
10. The pixel driving circuit according to claim 7, wherein the modulation lead and the reference signal line are disposed in different layers, and the modulation lead is connected to the reference signal line through a trace and a via.
11. The pixel driving circuit according to claim 7, wherein the first thin film transistor, the second thin film transistor, the fifth thin film transistor, the sixth thin film transistor, and the seventh thin film transistor are P-type thin film transistors, and the third thin film transistor and the fourth thin film transistor are N-type thin film transistors.
12. The pixel driving circuit according to claim 11, wherein the first scan signal line, the second scan signal line, the third scan signal line, the reset signal line, and the light emitting signal line function in common in a reset phase, a compensation phase, and a light emitting phase of the pixel driving circuit;
in the reset phase, the first scanning signal line, the reset signal line, and the light emitting signal line are at a high level, and the second scanning signal line, the third scanning signal line, and the data are at a low level;
in the compensation phase, the second scanning signal line, the third scanning signal line and the light emitting signal line are at a high level, and the first scanning signal line and the reset signal line are at a low level; the compensation stage is used for detecting the threshold voltage of the first thin film transistor, and the threshold voltage drift amount of the first thin film transistor, the threshold voltage drift amount of the third thin film transistor and the threshold voltage drift amount of the fourth thin film transistor are the same;
in the light emission phase, the first scanning signal line, the second scanning signal line, the third scanning signal line, and the reset signal line are at a low level, and the light emission signal line is at a high level.
13. An LTPO display panel comprising a source driver and the pixel driving circuit according to any one of claims 1 to 12, wherein the source driver is connected to the modulation signal line or the reference signal line and introduces the modulation voltage to the modulation lead line through the modulation signal line or the reference signal line.
14. The LTPO display panel of claim 13, wherein a plurality of the modulation signal lines or a plurality of the reference signal lines are horizontally disposed on the display panel and connected to the source driver after being converged at a side of the display panel by a lead, and each of the modulation signal lines or each of the reference signal lines is used for modulating a corresponding row of pixels.
15. The LTPO display panel of claim 13, wherein the modulation voltage introduced into the modulation lead by the source driver through the modulation signal line is 0 to-8V, and the modulation voltage introduced into the modulation lead by the source driver through the reference signal line is-2V to-4V.
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