WO2021142871A1

WO2021142871A1 - Pixel compensation circuit and display panel

Info

Publication number: WO2021142871A1
Application number: PCT/CN2020/075250
Authority: WO
Inventors: 张晓东
Original assignee: 深圳市华星光电半导体显示技术有限公司
Priority date: 2020-01-13
Filing date: 2020-02-14
Publication date: 2021-07-22
Also published as: CN111179850A

Abstract

Disclosed are a pixel compensation circuit and a display panel. The use of a double-gate structure transistor as a driving transistor enables a channel to be separately adjusted by a top gate and a bottom gate, so as to achieve dynamic adjustment of a threshold voltage of the driving transistor. The threshold voltage can be detected by means of diode connection by controlling the driving transistor, so as to achieve real-time compensation for the threshold voltage and compensation for the threshold voltage in the case of positive and negative drift, thereby effectively improving the uniformity of image display with the same grayscale.

Description

Pixel compensation circuit and display panel

Technical field

This application relates to the field of display technology, and in particular to a pixel compensation circuit and a display panel.

Background technique

Active Matrix Organic Light Emitting Diode (Active-Matrix Organic Light Emitting Diode (AMOLED for short) display device is a display device that uses current to drive OLED devices to emit light to form a picture. As a new generation of display technology, compared to traditional liquid crystal display (Liquid Crystal Display, LCD), AMOLED has higher contrast, faster response speed and wider viewing angle, so it is widely used in the field of smart phones. After continuous development, it has expanded to the field of smart TVs and wearable devices.

In terms of driving mode, unlike traditional voltage-driven LCDs, AMOLED is a current-driven device. Film Transistor (TFT for short) is more sensitive to electrical variation, and the drift of the threshold voltage (Vth) of the TFT will affect the uniformity and accuracy of the screen display. At present, small and medium-sized low-temperature polysilicon based (Low Temperature Poly-Silicon, referred to as LTPS) panels, generally use 7T1C internal compensation circuit to compensate for threshold voltage drift, so as to improve the picture display.

technical problem

Please refer to Fig. 1, a circuit diagram of the existing 7T1C internal compensation circuit. In the existing 7T1C internal compensation circuit, all 7 TFT tubes adopt P-type TFTs, and the TFT tube M2 adopts a diode-connect method to capture the threshold voltage to realize the internal compensation of the threshold voltage. Among them, VDD is the driving voltage, VI is the initialization voltage, VSS is the common voltage, Data(m) is the mth data line, Scan(n) is the scan signal corresponding to the nth first scan line, Scan(n- 1) is the scan signal corresponding to the n-1th first scan line, EM(n) is the light-emitting control signal corresponding to the n-th light-emitting control line, and Xscan(n) is the n-th second scan line. Scan signal. However, the TFT tube uses a diode-connected internal compensation circuit, the threshold voltage compensation range is small, and the threshold voltage cannot be compensated for the positive value, and the compensation effect is different under different gray scales.

Technical solutions

The embodiments of the present application provide a pixel compensation circuit and a display panel, which can compensate the threshold voltage under the same gray scale, improve the uniformity of the panel display, and can realize the compensation ability when the threshold voltage is a positive value.

The embodiment of the application provides a pixel compensation circuit, the circuit includes a driving transistor and a light emitting device; the circuit further includes: an initialization unit, a data writing unit, a compensation unit, and a light emission control unit; The driving transistor adopts a P-type thin film transistor with a double-gate structure. Its bottom gate is electrically connected to a first node, its top gate is electrically connected to a second node, its first electrode is used to receive a driving voltage, and its second electrode Is electrically connected to a third node; the initialization unit is electrically connected to the first node, and is used for transmitting an initialization voltage to the first node during the initialization phase, so as to modulate the threshold voltage of the driving transistor to a positive value The data writing unit is electrically connected to the second node for transmitting a reference voltage to the second node during the compensation phase, and transmitting a data voltage to the second node during the data writing phase; The compensation unit includes: a fourth transistor, a first capacitor, and a second capacitor; the gate of the fourth transistor is used to receive a third scan signal, and the first electrode of the fourth transistor is electrically connected to the first node, The second electrode is electrically connected to the third node; the first capacitor is electrically connected to the first electrode of the driving transistor and the first node; the second capacitor is electrically connected to the first electrode of the driving transistor. Electrode and the second node; the compensation unit is used to control the driving transistor to form a diode connection mode during the compensation phase, so as to compensate the threshold voltage of the driving transistor to a value according to the reference voltage and the driving voltage A preset value; the light-emitting control unit is electrically connected to the third node and the light-emitting device, and is used for controlling the light-emitting device to emit light under the driving of the driving transistor during the light-emitting stage.

The embodiment of the application provides a pixel compensation circuit, the circuit includes a driving transistor and a light emitting device; the circuit further includes: an initialization unit, a data writing unit, a compensation unit, and a light emission control unit; The driving transistor adopts a double gate structure, its bottom gate is electrically connected to a first node, its top gate is electrically connected to a second node, its first electrode is used to receive a driving voltage, and its second electrode is connected to a third node Electrically connected; the initialization unit is electrically connected to the first node, and is used for transmitting an initialization voltage to the first node during the initialization phase to modulate the threshold voltage of the driving transistor to a positive value; the data writing The input unit is electrically connected to the second node, and is used for transmitting a reference voltage to the second node during the compensation phase, and transmitting a data voltage to the second node during the data writing phase; the compensation units are respectively The first node, the second node, the third node, and the first electrode of the driving transistor are electrically connected, and are used to control the driving transistor to form a diode connection mode in the compensation phase, so as to be based on the reference The voltage and the driving voltage compensate the threshold voltage of the driving transistor to a preset value; the light-emitting control unit is electrically connected to the third node and the light-emitting device, and is used to control all the light-emitting devices during the light-emitting phase. The light emitting device emits light under the driving of the driving transistor.

An embodiment of the present application also provides a display panel, the display panel array substrate, the array substrate includes a pixel compensation circuit, the circuit includes a driving transistor and a light emitting device; wherein, the circuit further includes: an initialization Unit, a data writing unit, a compensation unit, and a light-emitting control unit; the driving transistor adopts a double-gate structure, the bottom gate of which is electrically connected to a first node, the top gate of which is electrically connected to a second node, and the first An electrode is used to receive a driving voltage, and the second electrode is electrically connected to a third node; the initialization unit is electrically connected to the first node, and is used to transmit an initialization voltage to the first node in the initialization phase, In order to modulate the threshold voltage of the driving transistor to a positive value; the data writing unit is electrically connected to the second node for transmitting a reference voltage to the second node during the compensation phase, and during data writing In the stage, a data voltage is transmitted to the second node; the compensation unit is electrically connected to the first node, the second node, the third node, and the first electrode of the driving transistor, respectively, for In the compensation stage, the driving transistor is controlled to form a diode connection mode to compensate the threshold voltage of the driving transistor to a preset value according to the reference voltage and the driving voltage; the light emitting control unit is electrically connected to the The third node and the light-emitting device are used for controlling the light-emitting device to emit light under the driving of the driving transistor during the light-emitting stage.

Beneficial effect

The pixel compensation circuit of the present application adopts a double-gate structure transistor as the driving transistor, and the top gate and the bottom gate can adjust the channel separately to realize the dynamic adjustment of the threshold voltage of the driving transistor; the threshold voltage can be detected by controlling the driving transistor to realize the diode connection mode. Realize the real-time compensation of the threshold voltage, and can realize the compensation under the positive and negative drift of the threshold voltage, effectively broaden the scope of the threshold voltage compensation, and realize the threshold voltage compensation under the condition of different threshold voltage drifts under the same gray scale, thereby effectively improving the same gray scale. The uniformity of the screen display in grayscale improves the life of the panel display. In addition, the pixel compensation circuit of the present application has a simple circuit structure and requires fewer TFTs, which facilitates in-plane integration.

Description of the drawings

In order to more clearly describe the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings that need to be used in the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained from these drawings without creative work.

Figure 1 is a circuit diagram of an existing 7T1C internal compensation circuit;

Fig. 2 is a structural diagram of a pixel compensation circuit of this application;

Figure 3 is a gate modulation IV curve of a double-gate structure transistor;

Fig. 4 is a modulation relationship curve between the threshold voltage and the bottom gate voltage of the double-gate structure transistor;

FIG. 5 is a schematic diagram of the compensation principle of the dual-gate structure transistor in the case of different threshold voltage drifts;

FIG. 6 is a schematic diagram of the film structure of the driving transistor of the present application;

FIG. 7 is a circuit diagram of an embodiment of a pixel compensation circuit of this application;

FIG. 8 is a driving timing diagram of the pixel compensation circuit shown in FIG. 7;

FIG. 9 is a schematic diagram of the structure of the display panel of this application.

Embodiments of the present invention

The embodiments of the present application are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals indicate the same or similar components or components with the same or similar functions. The terms "first", "second", "third", etc. (if any) in the description and claims of this application and the drawings are used to distinguish similar objects, and not necessarily used to describe a specific order or sequence. . It should be understood that the objects described in this way can be interchanged under appropriate circumstances. In the description of the present application, "multiple" means two or more than two, unless otherwise specifically defined. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. The terms of direction mentioned in this application, for example: up, down, left, right, front, back, inner, outer, side, etc., are only directions with reference to the drawings.

In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installation", "connection" and "connection" should be understood in a broad sense. For example, it can be a fixed connection or a detachable connection. Or integrally connected; it can be mechanically connected, or it can be electrically connected or can communicate with each other; it can be directly connected, or indirectly connected through an intermediate medium, it can be the internal communication of two components or the interaction relationship between two components. For those of ordinary skill in the art, the specific meanings of the above-mentioned terms in this application can be understood according to specific circumstances.

This application proposes a new type of 5T2C pixel compensation circuit, which uses Double-Gate transistors as driving transistors. The two gates of the dual-gate device are controlled, the top gate (TG) and the bottom gate (BG) can adjust the channel separately to realize the dynamic adjustment of the threshold voltage (Vth) of the driving transistor; by introducing an electrical connection between the bottom gate and the bottom gate of the driving transistor The transistor between the drains allows the driving transistor to realize a diode-connect mode; by introducing a capacitance electrically connected between the bottom gate and the source of the driving transistor, the storage between the bottom gate and the source of the driving transistor The potential. This application combines the principle of gate regulation of double-gate devices and the principle of detecting the threshold voltage of the transistor using a diode connection method, which can realize real-time compensation of the threshold voltage, and can realize compensation under the condition of positive and negative drift of the threshold voltage, which effectively broadens the scope of threshold voltage compensation , Realize the threshold voltage compensation under the condition of different threshold voltage drifts under the same gray scale, thereby effectively improving the uniformity of the screen display under the same gray scale and increasing the life of the panel display. Among them, the TFTs in the 5T2C pixel compensation circuit can all be PTFTs, and the TFT structure and circuit implementation methods are universal.

Please also refer to Figures 2 to 5, where Figure 2 is a structural diagram of the pixel compensation circuit of this application, Figure 3 is a gate modulation IV curve of a double-gate transistor, and Figure 4 is a threshold voltage and a bottom of the double-gate transistor. For the modulation relationship curve between the gate terminal voltages, FIG. 5 is a schematic diagram of the compensation principle of the dual-gate structure transistor in the case of different threshold voltage drifts.

As shown in FIG. 2, the pixel compensation circuit of the present application includes a driving transistor T1 and a light-emitting device 21; it also includes an initialization unit 22, a data writing unit 23, a compensation unit 24 and a light-emitting control unit 25.

The driving transistor T1 adopts a double-gate structure (Double-Gate), its bottom gate (BG) is electrically connected to a first node P1, its top gate (TG) is electrically connected to a second node P2, and its first electrode is used for After receiving a driving voltage VDD, its second electrode is electrically connected to a third node P3. Specifically, the driving transistor T1 adopts a PTFT with a double gate structure. The gate modulation IV curve of the double-gate structure transistor is shown in Fig. 3, where the ordinate is the top-gate terminal voltage V _TG of the double-gate structure transistor in units of volts (V), and the abscissa is the current I _D of the double-gate structure transistor. The unit is ampere (A). The modulation relationship curve between the threshold voltage Vth and the bottom gate terminal voltage V _{BG of the} double-gate structure transistor is shown in FIG. 4.

The initialization unit 22 is electrically connected to the first node P1, and is used for transmitting an initialization voltage Vini to the first node P1 during the initialization phase to modulate the threshold voltage (Vth) of the driving transistor T1 to a positive value . In the initialization phase, the first node P1 writes the initialization voltage Vini, which can refresh the previous frame signal; at this time, since the bottom gate voltage of the driving transistor T1 is negative compared to the driving voltage VDD, its threshold voltage will be modulated Into a positive value.

The data writing unit 23 is electrically connected to the second node P2, and is used for transmitting a reference voltage Vref to the second node P2 during the compensation phase, and transmitting a data voltage Vdata to the second node P2 during the data writing phase. The second node P2. Specifically, in the compensation stage, the data writing unit 23 writes the reference voltage Vref into the driving transistor T1; in the data writing stage, the data writing unit 23 writes the data voltage Vdata into the drive transistor T1. The driving transistor T1.

The compensation unit 24 is electrically connected to the first node P1, the second node P2, the third node P3, and the first electrode of the driving transistor T1, respectively, for controlling the driving transistor during the compensation phase T1 forms a diode-connect mode to compensate the threshold voltage of the driving transistor T1 to a preset value according to the reference voltage Vref and the driving voltage VDD. Specifically, in the compensation phase, the data writing unit 23 writes the reference voltage Vref into the driving transistor T1; the driving transistor T1 forms a diode connection, so that the potential of the first node P1 continuously rises, so The threshold voltage of the driving transistor T1 gradually decreases until the driving transistor T1 is turned off; at this time, the threshold voltage of the driving transistor T1 is maintained at a preset value (Vref-VDD), which plays a role of threshold voltage compensation. Moreover, when the driving transistor T1 is turned off, the threshold voltages of all transistors are modulated to the preset value, that is, the threshold voltages of all transistors are written to the same value, so as to achieve threshold voltage compensation under the same gray scale, And it can compensate for the case where the initial value of the threshold voltage is positive.

The light-emitting control unit 25 is electrically connected to the third node P3 and the light-emitting device 21 respectively, and is used for controlling the light-emitting device 21 to emit light under the driving of the driving transistor T1 during the light-emitting stage.

As shown in FIG. 5, the ordinate is the threshold voltage Vth of the double-gate structure transistor (driving transistor T1), and the abscissa is the threshold voltage compensation value ΔV. Assume that Vth1 to Vth3 are different initial values of the threshold voltage Vth of the driving transistor T1. In the initialization phase, the bottom gate (BG) end of the driving transistor T1 is written with the initialization voltage Vini, and the threshold voltage Vth of the driving transistor T1 is raised respectively through the gate regulation mechanism of the bottom gate of the double-gate device (to the corresponding vertical coordinate Vth1' ~Vth3', the corresponding abscissa is Vini-VDD); in the compensation phase, the top gate (TG) terminal of the driving transistor T1 is written with the reference potential Vref, at this time the driving transistor T1 forms a diode connection, and the bottom gate potential rises, making the driving transistor T1 When the threshold voltage Vth of all TFTs are modulated to Vref-VDD (corresponding to the ordinate Vth_com, the corresponding abscissas are respectively Vp3, Vp2, Vp1), the driving transistor T1 is turned off, thus turning off the threshold of all TFTs The voltage Vth is written to the same value, so as to realize the compensation of the threshold voltage Vth under the same gray scale, and can compensate the case where the initial value of the threshold voltage Vth is positive.

Please refer to FIG. 6, which is a schematic diagram of the film structure of the driving transistor of the present application. Specifically, the film structure of the driving transistor 60 includes a bottom gate (BG) 601, a first gate dielectric layer (BGI) 602, a semiconductor layer 603, a second gate dielectric layer (TGI) 604, which are stacked in sequence. Top gate (TG) 605. The bottom gate 601 and the top gate 605 can respectively adjust the channel of the semiconductor layer 603 to achieve dynamic adjustment of the threshold voltage of the transistor.

In a further embodiment, the driving transistor 60 is a P-type thin film transistor, and the semiconductor layer 603 includes an n-type channel region and P-type doped regions formed on both sides of the channel region.

In a further embodiment, the first gate dielectric layer 602 is a bottom gate dielectric layer, and a silicon oxide/silicon nitride laminated structure (SiOx+SiNx) may be used. The second gate dielectric layer 604 is a top gate dielectric layer, and may adopt a silicon oxide single layer structure (SiOx).

Please refer to FIGS. 2 and 7-8 together. FIG. 7 is a circuit diagram of an embodiment of the pixel compensation circuit of the present application, and FIG. 8 is a driving timing diagram of the pixel compensation circuit shown in FIG. 7.

As shown in Figure 7, the pixel compensation circuit uses a 5T2C pixel compensation circuit, and the TFTs in the circuit all use P-type thin film transistors (PTFT). The source of the PTFT is the first electrode of the corresponding transistor, and the drain of the PTFT is the second electrode of the corresponding transistor. electrode. The TFT structure and circuit implementation of the 5T2C pixel compensation circuit are universal. The driving transistor T1 adopts a PTFT with a double gate structure, and the light emitting device 21 adopts a photodiode D1.

Specifically, the initialization unit 22 includes: a second transistor T2, the gate of the second transistor T2 is used to receive a first scan signal Xscan(n), and the first electrode of the second transistor T2 is used to receive the initialization voltage Vini , The second electrode is electrically connected to the first node P1. That is, the second transistor T2 is used to turn on in response to the first scan signal Xscan(n) to transmit the initialization voltage Vini to the first node P1.

Specifically, the data writing unit 23 includes: a third transistor T3, the gate of the third transistor T3 is used to receive a second scan signal scan(n), and the first electrode of the third transistor T3 is used to receive The reference voltage Vref and the data voltage Vdata are received during the data writing phase, and the second electrode of the reference voltage Vref is electrically connected to the second node P2. That is, the third transistor T3 is used to turn on in response to the second scan signal scan(n) to write the reference voltage Vref into the driving transistor T1 during the compensation phase, and to write the reference voltage Vref into the driving transistor T1 during the data writing phase. The data voltage Vdata is written into the driving transistor T1.

Specifically, the compensation unit unit 24 includes: a fourth transistor T4, a first capacitor C1, and a second capacitor C2. The gate of the fourth transistor T4 is used to receive a third scan signal Xscan(n+1), and its first electrode is electrically connected to the first node P1, and its second electrode is electrically connected to the third node P3. That is, the fourth transistor T4 is used to turn on in response to the third scan signal Xscan(n+1), so that the driving transistor T1 is connected in the form of a diode, thereby pulling up the first transistor according to the reference voltage Vref. The potential of a node P1. The first capacitor C1 is electrically connected to the first electrode of the driving transistor T1 and the first node P1; the first capacitor C1 is used to store the voltage of the first node P1, that is, to store the voltage of the driving transistor T1 Bottom gate potential. The second capacitor C2 is electrically connected to the first electrode of the driving transistor T1 and the second node P2; the second capacitor C2 is used to store the voltage of the second node P2, that is, to store the voltage of the driving transistor T1 Top gate potential. Wherein, the third scan signal Xscan(n+1) is a scan signal of the next frame related to the first scan signal Xscan(n).

Specifically, the light emission control unit 25 includes: a fifth transistor T5, the gate of the fifth transistor T5 is used to receive a light emission control signal EM(n), and the first electrode of the fifth transistor T5 is electrically connected to the third node P3 , The second electrode is electrically connected to the anode of the photodiode D1, and the upper cathode of the photodiode D1 is connected to the common voltage VSS. That is, the fifth transistor T5 is used to turn on in response to the light emission control signal EM(n), so that the driving transistor T1 drives the photodiode D1 to emit light. In a further embodiment, the photodiode D1 is an organic light emitting diode (OLED).

The working principle of the pixel compensation circuit of the present application will be further explained below with reference to FIGS. 7-8. The specific working principle is as follows:

Initial stage A1: the light emission control signal EM(n) is high, the fifth transistor T5 is turned off to prevent the photodiode D1 from emitting light; the second scan signal scan(n), the third scan signal Xscan( n+1) are both high level, the third transistor T3 and the fourth transistor T4 are also in the off state; the first scan signal Xscan(n) is low, the first transistor T1 is turned on, The node P1 writes the initialization voltage Vini signal to refresh the signal of the previous frame. At this time, since the bottom gate voltage of the driving transistor T1 is negative compared to the driving voltage VDD, the threshold voltage of the driving transistor T1 will be modulated to a positive value.

Compensation stage A2: the first scan signal Xscan(n) jumps to high level, the first transistor T1 is turned off; the second scan signal scan(n) jumps to low level, and the third transistor T3 is turned on , The second node P2 writes the reference voltage Vref signal, the second capacitor C2 stores the corresponding potential of the first and second nodes P2; the third scan signal Xscan(n+1) also jumps to a low level, and the fourth transistor T4 is also turned on On, the driving transistor T1 forms a diode, the potential of the first node P1 continues to rise, and the threshold voltage of the driving transistor T1 gradually decreases until it is turned off; at this time, the threshold voltage of the driving transistor T1 remains at a preset value (Vref-VDD), starting To the effect of threshold voltage compensation, the first capacitor C1 stores the corresponding potential of the first node P1.

Data writing (Writing) stage A3: the third scan signal Xscan(n+1) jumps to a high level, the fourth transistor T4 is turned off; the second scan signal scan(n) maintains a low level, and the third transistor T3 Maintaining conduction, the second node P2 writes the data voltage Vdata signal.

Emission stage A4: the second scan signal scan(n) jumps to a high level, the third transistor T3 is turned off; the emission control signal EM(n) jumps to a low level, and the fifth transistor T5 is turned on, The photodiode D1 emits light.

Based on the same inventive concept, the present application also provides a display panel.

Please refer to FIG. 9, which is a schematic diagram of the display panel structure of the present application. The display panel 90 includes an array substrate 91, and the array substrate 91 includes a pixel compensation circuit 911. The pixel compensation circuit 911 adopts the pixel compensation circuit described in FIGS. 2 and 7 of the present application. The connection mode and working principle of the circuit components of the pixel compensation circuit 911 have been described in detail above, and will not be repeated here.

The display panel adopting the pixel compensation circuit of the present application can realize the dynamic adjustment of the threshold voltage of the driving transistor, realize the real-time compensation of the threshold voltage, and realize the compensation under the positive and negative drift of the threshold voltage, which effectively broadens the range of threshold voltage compensation , Realize the threshold voltage compensation under the condition of different threshold voltage drifts under the same gray scale, thereby effectively improving the uniformity of the screen display under the same gray scale and increasing the life of the panel display. In addition, the pixel compensation circuit of the present application has a simple circuit structure and requires fewer TFTs, which facilitates in-plane integration.

It can be understood that for those of ordinary skill in the art, equivalent replacements or changes can be made according to the technical solutions of the present application and its inventive concept, and all these changes or replacements shall fall within the protection scope of the appended claims of the present application.

Claims

A pixel compensation circuit, the circuit includes a driving transistor and a light emitting device; wherein, the circuit further includes: an initialization unit, a data writing unit, a compensation unit, and a light emission control unit;

The driving transistor adopts a P-type thin film transistor with a double-gate structure. Its bottom gate is electrically connected to a first node, its top gate is electrically connected to a second node, its first electrode is used to receive a driving voltage, and its second The electrode is electrically connected to a third node;

The initialization unit is electrically connected to the first node, and is configured to transmit an initialization voltage to the first node during the initialization phase, so as to modulate the threshold voltage of the driving transistor to a positive value;

The data writing unit is electrically connected to the second node, and is used for transmitting a reference voltage to the second node during the compensation phase, and transmitting a data voltage to the second node during the data writing phase;

The compensation unit includes: a fourth transistor, a first capacitor, and a second capacitor; the gate of the fourth transistor is used to receive a third scan signal, and the first electrode of the fourth transistor is electrically connected to the first node, The second electrode is electrically connected to the third node; the first capacitor is electrically connected to the first electrode of the driving transistor and the first node; the second capacitor is electrically connected to the first electrode of the driving transistor. Electrode and the second node; the compensation unit is used to control the driving transistor to form a diode connection mode during the compensation phase, so as to compensate the threshold voltage of the driving transistor to a value according to the reference voltage and the driving voltage A preset value;

The light-emitting control unit is electrically connected to the third node and the light-emitting device, and is used for controlling the light-emitting device to emit light under the driving of the driving transistor during the light-emitting stage.
8. The pixel compensation circuit according to claim 1, wherein the film structure of the driving transistor includes a bottom gate, a first gate dielectric layer, a semiconductor layer, a second gate dielectric layer, and a top gate stacked in sequence.
3. The pixel compensation circuit according to claim 2, wherein the semiconductor layer includes an n-type channel region and p-type doped regions formed on both sides of the channel region.
3. The pixel compensation circuit according to claim 2, wherein the first gate dielectric layer adopts a silicon oxide/silicon nitride laminated structure, and the second gate dielectric layer adopts a silicon oxide single layer structure.
The pixel compensation circuit of claim 1, wherein the fourth transistor is a P-type thin film transistor.
The pixel compensation circuit according to claim 1, wherein the light-emitting device is an organic light-emitting diode.
8. The pixel compensation circuit of claim 1, wherein the initialization unit comprises: a second transistor, a gate of the second transistor is used to receive a first scan signal, and a first electrode of the second transistor is used to receive the Initialize the voltage, and its second electrode is electrically connected to the first node.
8. The pixel compensation circuit of claim 1, wherein the data writing unit comprises: a third transistor, the gate of the third transistor is used to receive a second scan signal, and the first electrode of the third transistor is used to The reference voltage is received in the compensation phase, and the data voltage is received in the data writing phase, the second electrode of which is electrically connected to the second node.
5. The pixel compensation circuit of claim 1, wherein the light emission control unit comprises: a fifth transistor, a gate of the fifth transistor is used to receive a light emission control signal, and a first electrode of the fifth transistor is electrically connected to the first transistor. Three nodes, the second electrode of which is electrically connected to the light emitting device.
A pixel compensation circuit, the circuit includes a driving transistor and a light emitting device; wherein, the circuit further includes: an initialization unit, a data writing unit, a compensation unit, and a light emission control unit;

The driving transistor adopts a double-gate structure, its bottom gate is electrically connected to a first node, its top gate is electrically connected to a second node, its first electrode is used to receive a driving voltage, and its second electrode is electrically connected to a third node. Node electrical connection;

The initialization unit is electrically connected to the first node, and is configured to transmit an initialization voltage to the first node during the initialization phase, so as to modulate the threshold voltage of the driving transistor to a positive value;

The data writing unit is electrically connected to the second node, and is used for transmitting a reference voltage to the second node during the compensation phase, and transmitting a data voltage to the second node during the data writing phase;

The compensation unit is electrically connected to the first node, the second node, the third node, and the first electrode of the driving transistor, respectively, for controlling the driving transistor to form a diode connection mode during the compensation phase, To compensate the threshold voltage of the driving transistor to a preset value according to the reference voltage and the driving voltage;

The light-emitting control unit is electrically connected to the third node and the light-emitting device, and is used for controlling the light-emitting device to emit light under the driving of the driving transistor during the light-emitting stage.
9. The pixel compensation circuit according to claim 10, wherein the driving transistor is a P-type thin film transistor with a double gate structure.
10. The pixel compensation circuit of claim 10, wherein the light-emitting device is an organic light-emitting diode.
9. The pixel compensation circuit according to claim 10, wherein the film structure of the driving transistor comprises a bottom gate, a first gate dielectric layer, a semiconductor layer, a second gate dielectric layer, and a top gate stacked in sequence.
15. The pixel compensation circuit of claim 13, wherein the semiconductor layer includes an n-type channel region and P-type doped regions formed on both sides of the channel region.
15. The pixel compensation circuit according to claim 13, wherein the first gate dielectric layer adopts a silicon oxide/silicon nitride laminated structure, and the second gate dielectric layer adopts a silicon oxide single layer structure.
9. The pixel compensation circuit of claim 10, wherein the initialization unit comprises: a second transistor, a gate of the second transistor is used to receive a first scan signal, and a first electrode of the second transistor is used to receive the Initialize the voltage, and its second electrode is electrically connected to the first node.
9. The pixel compensation circuit of claim 10, wherein the data writing unit comprises: a third transistor, the gate of the third transistor is used to receive a second scan signal, and the first electrode of the third transistor is used to The reference voltage is received in the compensation phase, and the data voltage is received in the data writing phase, the second electrode of which is electrically connected to the second node.
10. The pixel compensation circuit of claim 10, wherein the compensation unit unit comprises: a fourth transistor, a first capacitor, and a second capacitor;

The gate of the fourth transistor is used to receive a third scan signal, the first electrode of the fourth transistor is electrically connected to the first node, and the second electrode of the fourth transistor is electrically connected to the third node;

The first capacitor is electrically connected to the first electrode of the driving transistor and the first node;

The second capacitor is electrically connected to the first electrode of the driving transistor and the second node, respectively.
9. The pixel compensation circuit of claim 10, wherein the light emission control unit comprises: a fifth transistor, a gate of the fifth transistor is used to receive a light emission control signal, and a first electrode of the fifth transistor is electrically connected to the Three nodes, the second electrode of which is electrically connected to the light emitting device.
A display panel, the display panel includes an array substrate, the array substrate includes a pixel compensation circuit, the circuit includes a driving transistor and a light emitting device; wherein, the circuit further includes: an initialization unit, a data writing Unit, a compensation unit, and a light-emitting control unit;

The driving transistor adopts a double-gate structure, its bottom gate is electrically connected to a first node, its top gate is electrically connected to a second node, its first electrode is used to receive a driving voltage, and its second electrode is electrically connected to a third node. Node electrical connection;

The initialization unit is electrically connected to the first node, and is configured to transmit an initialization voltage to the first node during the initialization phase, so as to modulate the threshold voltage of the driving transistor to a positive value;

The data writing unit is electrically connected to the second node, and is used for transmitting a reference voltage to the second node in the compensation phase, and transmitting a data voltage to the second node in the data writing phase;

The compensation unit is electrically connected to the first node, the second node, the third node, and the first electrode of the driving transistor, respectively, for controlling the driving transistor to form a diode connection mode during the compensation phase, To compensate the threshold voltage of the driving transistor to a preset value according to the reference voltage and the driving voltage;

The light-emitting control unit is electrically connected to the third node and the light-emitting device, and is used for controlling the light-emitting device to emit light under the driving of the driving transistor during the light-emitting stage.