CN111179850A - Pixel compensation circuit, array substrate and display panel - Google Patents
Pixel compensation circuit, array substrate and display panel Download PDFInfo
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- CN111179850A CN111179850A CN202010029803.5A CN202010029803A CN111179850A CN 111179850 A CN111179850 A CN 111179850A CN 202010029803 A CN202010029803 A CN 202010029803A CN 111179850 A CN111179850 A CN 111179850A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0233—Improving the luminance or brightness uniformity across the screen
Abstract
The application discloses pixel compensation circuit, array substrate and display panel. By adopting a double-gate structure transistor as a driving transistor, a top gate and a bottom gate can respectively regulate and control channels, and the dynamic regulation of the threshold voltage of the driving transistor is realized; the detection of the threshold voltage in a diode connection mode is realized by controlling the driving transistor, so that the real-time compensation of the threshold voltage can be realized, the compensation under the condition of positive and negative drift of the threshold voltage can be realized, and the uniformity of picture display under the same gray scale is effectively improved.
Description
Technical Field
The application relates to the technical field of display, in particular to a pixel compensation circuit, an array substrate and a display panel.
Background
An Active-Matrix Organic Light Emitting Diode (AMOLED) display device is a display device that uses current to drive an OLED device to emit Light to form a picture. As a new generation of Display technology, compared with a conventional Liquid Crystal Display (LCD), the AMOLED has higher contrast, faster response speed and wider viewing angle, and thus is widely applied to the field of smart phones and is continuously developed and expanded to the field of smart televisions and wearable devices.
In terms of driving mode, unlike a conventional voltage-driven LCD, the AMOLED belongs to a current-driven device, and is sensitive to electrical variation of a Thin Film Transistor (TFT), and the shift of the threshold voltage (Vth) of the TFT affects uniformity and accuracy of image display. At present, a small-sized low temperature Poly-Silicon (LTPS) process-based panel generally adopts a 7T1C internal compensation circuit to compensate for threshold voltage drift, thereby improving image display.
Referring to fig. 1, a circuit diagram of an internal compensation circuit of the prior art 7T1C is shown. In the existing 7T1C internal compensation circuit, 7 TFT transistors all adopt P-type TFTs, wherein the TFT transistor M2 adopts a diode-connected (diode-connected) mode to capture a threshold voltage, thereby implementing internal compensation of the threshold voltage. VDD is driving voltage, VI is initialization voltage, VSS is common voltage, Data (m) is mth Data line, Scan (n) is scanning signal transmitted corresponding to nth first scanning line, Scan (n-1) is scanning signal transmitted corresponding to nth first scanning line, EM (n) is light-emitting control signal transmitted corresponding to nth light-emitting control line, and Xscan (n) is scanning signal transmitted corresponding to nth second scanning line. However, the TFT employs an internal compensation circuit in a diode connection manner, so that the threshold voltage compensation range is relatively small, the situation that the threshold voltage is a positive value cannot be compensated, and compensation effects are different in different gray scales.
Disclosure of Invention
The embodiment of the application provides a pixel compensation circuit, an array substrate and a display panel, which can realize the compensation of threshold voltage under the same gray scale, improve the uniformity of panel display and realize the compensation capability under the condition that the threshold voltage is a positive value.
The embodiment of the application provides a pixel compensation circuit, which comprises a driving transistor and a light-emitting device; the circuit further comprises: an initialization unit, a data write-in unit, a compensation unit and a lighting control unit; the driving transistor adopts a double-gate structure, the bottom gate of the driving transistor is electrically connected with a first node, the top gate of the driving transistor is electrically connected with a second node, the first electrode of the driving transistor is used for receiving a driving voltage, and the second electrode of the driving transistor is electrically connected with a third node; the initialization unit is electrically connected with the first node and used for transmitting an initialization voltage to the first node in an initialization stage so as to modulate the threshold voltage of the driving transistor into a positive value; the data writing unit is electrically connected with the second node and used for transmitting a reference voltage to the second node in a compensation stage and transmitting a data voltage to the second node in a data writing stage; the compensation unit is respectively electrically connected with the first node, the second node, the third node and the first electrode of the driving transistor, and is used for controlling the driving transistor to form a diode connection mode in a compensation stage so as to compensate the threshold voltage of the driving transistor to a preset value according to the reference voltage and the driving voltage; and the light-emitting control unit is respectively electrically connected with the third node and the light-emitting device and is used for controlling the light-emitting device to emit light under the driving of the driving transistor in a light-emitting stage.
The embodiment of the application also provides an array substrate, and the array substrate comprises the pixel compensation electrode.
The embodiment of the application also provides a display panel, which comprises the array substrate.
The application has the advantages that: according to the pixel compensation circuit, the double-grid structure transistor is used as the driving transistor, and the top grid and the bottom grid can respectively regulate and control channels, so that the dynamic regulation of the threshold voltage of the driving transistor is realized; the detection of the threshold voltage in a diode connection mode is realized by controlling the driving transistor, the real-time compensation of the threshold voltage can be realized, the compensation under the condition of positive and negative drift of the threshold voltage can be realized, the compensation range of the threshold voltage is effectively widened, the compensation of the threshold voltage under the condition of different threshold voltage drifts under the same gray scale is realized, the uniformity of picture display under the same gray scale is effectively improved, and the service life of panel display is prolonged. And the pixel compensation circuit has simple structure and less required TFT, and is beneficial to in-plane integration.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a circuit diagram of an internal compensation circuit of a conventional 7T 1C;
FIG. 2 is a block diagram of a pixel compensation circuit according to the present application;
FIG. 3 is a gate modulation IV curve for a dual gate structure transistor;
FIG. 4 is a graph of the modulation relationship between the threshold voltage and the bottom gate voltage of a dual gate structure transistor;
FIG. 5 is a schematic diagram of compensation principles of a double-gate structure transistor under different threshold voltage drift conditions;
FIG. 6 is a schematic diagram of a film structure of a driving transistor according to the present application;
FIG. 7 is a circuit diagram of an embodiment of a pixel compensation circuit of the present application;
FIG. 8 is a driving timing diagram of the pixel compensation circuit shown in FIG. 7;
fig. 9 is a schematic diagram of a display panel structure according to the present application.
Detailed Description
Reference will now be made in detail to embodiments of the present application, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar components or components having the same or similar functions throughout. The terms "first," "second," "third," and the like in the description and in the claims of the present application, and in the drawings, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the objects so described are interchangeable under appropriate circumstances. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise. Furthermore, the terms "comprising" and "having," as well as any variations thereof, are intended to cover a non-exclusive inclusion. The directional phrases referred to in this application, for example: up, down, left, right, front, rear, inner, outer, lateral, etc., are simply directions with reference to the drawings.
Throughout the description of the present application, it is to be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; may be mechanically connected, may be electrically connected or may be in communication with each other; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.
The application provides a novel 5T2C pixel compensation circuit, which adopts a Double-Gate structure (Double-Gate) transistor as a driving transistor. The double-gate device is controlled by two gates, and a Top Gate (TG) and a Bottom Gate (BG) can respectively regulate and control channels to realize dynamic regulation of the threshold voltage (Vth) of the driving transistor; by introducing a transistor electrically connected between the bottom gate and the drain of the driving transistor, the driving transistor can realize a diode-connected (diode-connected) manner; by introducing a capacitance electrically connected between the bottom gate and the source of the drive transistor, the potential between the bottom gate and the source of the drive transistor can be stored. According to the method, the grid regulation principle of the double-grid device and the principle that the transistor detects the threshold voltage in the diode connection mode are combined, the real-time compensation of the threshold voltage can be realized, the compensation under the condition that the threshold voltage is positive and negative, the range of the threshold voltage compensation is effectively widened, the threshold voltage compensation under the condition that different threshold voltages drift under the same gray scale is realized, the uniformity of picture display under the same gray scale is effectively improved, and the service life of panel display is prolonged. The TFTs in the 5T2C pixel compensation circuit may all adopt PTFTs, and the TFT structure and circuit implementation thereof have universality.
Fig. 2-5 are also shown, in which fig. 2 is a structural diagram of the pixel compensation circuit of the present application, fig. 3 is a gate modulation IV curve of the dual-gate transistor, fig. 4 is a modulation relationship curve between the threshold voltage and the bottom gate voltage of the dual-gate transistor, and fig. 5 is a schematic diagram of the compensation principle of the dual-gate transistor under different threshold voltage drift conditions.
As shown in fig. 2, the pixel compensation circuit of the present application includes a driving transistor T1 and a light emitting device 21; further comprising: an initialization unit 22, a data writing unit 23, a compensation unit 24, and a light emission control unit 25.
The driving transistor T1The Double-Gate structure (Double-Gate) is adopted, the Bottom Gate (BG) is electrically connected to a first node P1, the Top Gate (TG) is electrically connected to a second node P2, the first electrode is used for receiving a driving voltage VDD, and the second electrode is electrically connected to a third node P3. Specifically, the driving transistor T1 employs a PTFT of a double gate structure. The gate modulation IV curve of the double-gate structure transistor is shown in FIG. 3, wherein the ordinate is the voltage V at the top gate of the double-gate structure transistorTGUnit voltage (V) and abscissa is current I of the transistor with double gate structureDIn amperes (a). Threshold voltage Vth and bottom gate voltage V of double-gate structure transistorBGThe modulation relationship curve between them is shown in fig. 4.
The initialization unit 22 is electrically connected to the first node P1, and is configured to transmit an initialization voltage Vini to the first node P1 during an initialization phase, so as to modulate the threshold voltage (Vth) of the driving transistor T1 to a positive value. In the initialization phase, the first node P1 writes an initialization voltage Vini, and the last frame signal can be refreshed; at this time, the driving transistor T1 has its threshold voltage modulated to a positive value because the bottom gate voltage is negative compared to the driving voltage VDD.
The data writing unit 23 is electrically connected to the second node P2, and is configured to transmit a reference voltage Vref to the second node P2 during a compensation phase, and transmit a data voltage Vdata to the second node P2 during a data writing phase. Specifically, in the compensation phase, the data writing unit 23 writes the reference voltage Vref in the driving transistor T1; in a data writing phase, the data writing unit 23 writes the data voltage Vdata into the driving transistor T1.
The compensation unit 24 is electrically connected to the first node P1, the second node P2, the third node P3 and the first electrode of the driving transistor T1, respectively, and is configured to control the driving transistor T1 to form a diode-connected (diode-connected) manner during a compensation phase, so as to compensate the threshold voltage of the driving transistor T1 to a predetermined value according to the reference voltage Vref and the driving voltage VDD. Specifically, in the compensation phase, the data writing unit 23 writes the reference voltage Vref in the driving transistor T1; the driving transistor T1 is diode-connected such that the potential of the first node P1 continuously rises and the threshold voltage of the driving transistor T1 gradually decreases until the driving transistor T1 is turned off; at this time, the threshold voltage of the driving transistor T1 is maintained at a predetermined value (Vref-VDD), which acts as a threshold voltage compensation. When the driving transistor T1 is turned off, the threshold voltages of all the transistors are modulated to the preset value, that is, the threshold voltages of all the transistors are written to the same value, so that the threshold voltage compensation at the same gray level is realized, and the condition that the initial value of the threshold voltage is a positive value can be compensated.
The light emission control unit 25 is electrically connected to the third node P3 and the light emitting device 21, respectively, for controlling the light emitting device 21 to emit light under the driving of the driving transistor T1 during a light emission period.
as shown in fig. 5, the vertical axis is the threshold voltage Vth of the double-gate structure transistor (driving transistor T1), the horizontal axis is the threshold voltage compensation value △ v, it is assumed that Vth1 to Vth3 are different initial values of the threshold voltage Vth of the driving transistor T1, in the initialization phase, the Bottom Gate (BG) end of the driving transistor T1 writes the initialization voltage Vini, the threshold voltage Vth of the driving transistor T1 is raised respectively (to Vth1 'to Vth 3' corresponding to the vertical axis and Vini-VDD corresponding to the horizontal axis) by the gate control mechanism of the bottom gate of the double-gate device, in the compensation phase, the Top Gate (TG) end of the driving transistor T1 writes the reference potential Vref, when the driving transistor T1 forms a diode connection, the bottom gate potential is raised, so that the threshold voltage Vth of the driving transistor T1 is reduced, when the threshold voltages of all the TFTs are modulated to Vref-VDD (to Vp _ com corresponding to Vp3, Vp 733, Vp 3873742 corresponding to the horizontal axis), so that the threshold voltages of the driving transistor T68584 are reduced and all the threshold voltages can be compensated to the same gray scale, thereby realizing the threshold voltage compensation under the same threshold voltage compensation condition.
According to the pixel compensation circuit, the double-grid structure transistor is used as the driving transistor, and the top grid and the bottom grid can respectively regulate and control channels, so that the dynamic regulation of the threshold voltage of the driving transistor is realized; the detection of the threshold voltage in a diode connection mode is realized by controlling the driving transistor, the real-time compensation of the threshold voltage can be realized, the compensation under the condition of positive and negative drift of the threshold voltage can be realized, the compensation range of the threshold voltage is effectively widened, the compensation of the threshold voltage under the condition of different threshold voltage drifts under the same gray scale is realized, the uniformity of picture display under the same gray scale is effectively improved, and the service life of panel display is prolonged. And the pixel compensation circuit has simple structure and less required TFT, and is beneficial to in-plane integration.
Referring to fig. 6, a film structure of a driving transistor according to the present application is shown. Specifically, the film structure of the driving transistor 60 includes sequentially stacked: a Bottom Gate (BG)601, a first gate dielectric layer (BGI)602, a semiconductor layer 603, a second gate dielectric layer (TGI)604, and a Top Gate (TG) 605. The bottom gate 601 and the top gate 605 can respectively regulate and control the channel of the semiconductor layer 603, so as to realize dynamic regulation of the threshold voltage of the transistor.
In a further embodiment, the driving transistor 60 is a P-type thin film transistor (PTFT), and the semiconductor layer 603 includes an n-type channel region and P-type doped regions formed on both sides of the channel region.
In a further embodiment, the first gate dielectric layer 602 is a bottom gate dielectric layer, and may adopt a silicon oxide/silicon nitride stack structure (SiOx + SiNx). The second gate dielectric layer 604 is a top gate dielectric layer, and may be a silicon oxide single layer structure (SiOx).
Referring to fig. 2 and fig. 7-8 together, fig. 7 is a circuit diagram of an embodiment of a pixel compensation circuit of the present application, and fig. 8 is a driving timing diagram of the pixel compensation circuit shown in fig. 7.
As shown in fig. 7, the pixel compensation circuit adopts a 5T2C pixel compensation circuit, the TFTs in the circuit all adopt P-type thin film transistors (PTFTs), the source of the PTFT is the first electrode of the corresponding transistor, and the drain of the PTFT is the second electrode of the corresponding transistor. The TFT structure and the circuit implementation mode of the 5T2C pixel compensation circuit have universality. The driving transistor T1 employs a PTFT of a double gate structure, and the light emitting device 21 employs a photodiode D1.
Specifically, the initialization unit 22 includes: a second transistor T2, a gate of the second transistor T2 is configured to receive a first scan signal Xscan (n), a first electrode thereof is configured to receive the initialization voltage Vini, and a second electrode thereof is electrically connected to the first node P1. That is, the second transistor T2 is to be turned on in response to the first scan signal Xscan (n) to transfer the initialization voltage Vini to the first node P1.
Specifically, the data writing unit 23 includes: a third transistor T3, the gate of the third transistor T3 is used for receiving a second scan signal scan (n), the first electrode of the third transistor T3 is used for receiving the reference voltage Vref during the compensation phase, and the data voltage Vdata during the data writing phase, and the second electrode of the third transistor T3 is electrically connected to the second node P2. That is, the third transistor T3 is turned on in response to the second scan signal scan (n) to write the reference voltage Vref to the driving transistor T1 during a compensation phase and write the data voltage Vdata to the driving transistor T1 during a data write phase.
Specifically, the compensation unit 24 includes: a fourth transistor T4, a first capacitor C1, and a second capacitor C2. The gate of the fourth transistor T4 is for receiving a third scan signal Xscan (n +1), the first electrode of which is electrically connected to the first node P1, and the second electrode of which is electrically connected to the third node P3. That is, the fourth transistor T4 is configured to be turned on in response to the third scan signal Xscan (n +1) to connect the driving transistor T1 in a diode form, thereby pulling up the potential of the first node P1 according to the reference voltage Vref. The first capacitor C1 is electrically connected to the first electrode of the driving transistor T1 and the first node P1, respectively; the first capacitor C1 is used for storing the voltage of the first node P1, i.e., the bottom gate potential of the driving transistor T1. The second capacitor C2 is electrically connected to the first electrode of the driving transistor T1 and the second node P2, respectively; the second capacitor C2 is used for storing the voltage of the second node P2, i.e. the top gate potential of the driving transistor T1. Wherein the third scan signal Xscan (n +1) is a scan signal of a next frame related to the first scan signal Xscan (n).
Specifically, the light emission control unit 25 includes: a fifth transistor T5, the gate of the fifth transistor T5 is used for receiving a light emission control signal EM (n), the first electrode thereof is electrically connected to the third node P3, the second electrode thereof is electrically connected to the anode of the photodiode D1, and the upper cathode of the photodiode D1 is connected to the common voltage VSS. That is, the fifth transistor T5 is turned on in response to the light emission control signal EM (n) so that the driving transistor T1 drives the photodiode D1 to emit light. In a further embodiment, the photodiode D1 is an Organic Light Emitting Diode (OLED).
The working principle of the pixel compensation circuit of the present application is further explained with reference to fig. 7-8.
The specific working principle is as follows:
initialization (initial) phase a 1: the emission control signal EM (n) is at a High level (High), and the fifth transistor T5 is turned off to prevent the photodiode D1 from emitting light; the second scan signal scan (n) and the third scan signal Xscan (n +1) are both at a high level, and the third transistor T3 and the fourth transistor T4 are also in an off state; the first scan signal Xscan (n) is Low (Low), the first transistor T1 is turned on, the initialization voltage Vini is written into the first node P1, and the previous frame signal is refreshed. At this time, the driving transistor T1 has a negative bottom gate voltage compared to the driving voltage VDD, and the threshold voltage of the driving transistor T1 is modulated to a positive value.
Compensation (Compensation) stage a 2: the first scan signal Xscan (n) transitions to a high level, and the first transistor T1 is turned off; the second scan signal scan (n) jumps to a low level, the third transistor T3 is turned on, the reference voltage Vref signal is written into the second node P2, and the second capacitor C2 stores the corresponding potential of the first two nodes P2; the third scan signal Xscan (n +1) also jumps to a low level, the fourth transistor T4 is also turned on, the driving transistor T1 forms a diode, the potential of the first node P1 continuously rises, and the threshold voltage of the driving transistor T1 gradually decreases until it is turned off; at this time, the threshold voltage of the driving transistor T1 is maintained at a predetermined value (Vref-VDD), which acts as threshold voltage compensation, and the first capacitor C1 stores the corresponding potential of the first node P1.
Data write (Writing) phase a 3: the third scan signal Xscan (n +1) jumps to a high level, and the fourth transistor T4 is turned off; the second scan signal scan (n) maintains a low level, the third transistor T3 maintains on, and the second node P2 writes the data voltage Vdata signal.
Emission (Emission) phase a 4: the second scan signal scan (n) transitions to a high level, and the third transistor T3 is turned off; the emission control signal EM (n) jumps to a low level, the fifth transistor T5 is turned on, and the photodiode D1 emits light.
Based on the same inventive concept, the application also provides a display panel.
Referring to fig. 9, a schematic diagram of a panel structure is shown in the present application. The display panel 90 includes an array substrate 91, and the array substrate 91 includes a pixel compensation circuit 911. The pixel compensation circuit 911 adopts the pixel compensation circuit described in fig. 2 and 7 of the present application. The connection and operation of the pixel compensation circuit 911 are described in detail above, and thus are not repeated herein.
By adopting the display panel of the pixel compensation circuit, the dynamic adjustment of the threshold voltage of the driving transistor can be realized, the real-time compensation of the threshold voltage can be realized, the compensation under the condition of positive and negative drift of the threshold voltage can be realized, the compensation range of the threshold voltage is effectively expanded, the compensation of the threshold voltage under the condition of different threshold voltage drifts under the same gray scale is realized, the uniformity of picture display under the same gray scale is effectively improved, and the service life of panel display is prolonged. And the pixel compensation circuit has simple structure and less required TFT, and is beneficial to in-plane integration.
The above description of the embodiments is only for assisting understanding of the technical solutions and the core ideas thereof; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications or substitutions do not depart from the spirit and scope of the present disclosure as defined by the appended claims.
Claims (10)
1. A pixel compensation circuit, the circuit includes a driving transistor and a light emitting device; characterized in that the circuit further comprises: an initialization unit, a data write-in unit, a compensation unit and a lighting control unit;
the driving transistor adopts a double-gate structure, the bottom gate of the driving transistor is electrically connected with a first node, the top gate of the driving transistor is electrically connected with a second node, the first electrode of the driving transistor is used for receiving a driving voltage, and the second electrode of the driving transistor is electrically connected with a third node;
the initialization unit is electrically connected with the first node and used for transmitting an initialization voltage to the first node in an initialization stage so as to modulate the threshold voltage of the driving transistor into a positive value;
the data writing unit is electrically connected with the second node and used for transmitting a reference voltage to the second node in a compensation stage and transmitting a data voltage to the second node in a data writing stage;
the compensation unit is respectively electrically connected with the first node, the second node, the third node and the first electrode of the driving transistor, and is used for controlling the driving transistor to form a diode connection mode in a compensation stage so as to compensate the threshold voltage of the driving transistor to a preset value according to the reference voltage and the driving voltage;
and the light-emitting control unit is respectively electrically connected with the third node and the light-emitting device and is used for controlling the light-emitting device to emit light under the driving of the driving transistor in a light-emitting stage.
2. The pixel compensation circuit of claim 1, wherein the film structure of the driving transistor comprises, in sequential order, stacked: the semiconductor device comprises a bottom gate, a first gate dielectric layer, a semiconductor layer, a second gate dielectric layer and a top gate.
3. The pixel compensation circuit of claim 2, wherein the semiconductor layer includes an n-type channel region and P-type doped regions formed on both sides of the channel region.
4. The pixel compensation circuit of claim 2, wherein the first gate dielectric layer is a silicon oxide/silicon nitride stack structure and the second gate dielectric layer is a silicon oxide single layer structure.
5. The pixel compensation circuit of claim 1, wherein the initialization unit comprises: and a second transistor, wherein a gate of the second transistor is used for receiving a first scanning signal, a first electrode of the second transistor is used for receiving the initialization voltage, and a second electrode of the second transistor is electrically connected with the first node.
6. The pixel compensation circuit of claim 1, wherein the data writing unit comprises: a third transistor, a gate of which is used for receiving a second scan signal, a first electrode of which is used for receiving the reference voltage in a compensation phase and receiving the data voltage in a data writing phase, and a second electrode of which is electrically connected with the second node.
7. The pixel compensation circuit according to claim 1, wherein the compensation unit includes: a fourth transistor, a first capacitor and a second capacitor;
the grid electrode of the fourth transistor is used for receiving a third scanning signal, the first electrode of the fourth transistor is electrically connected with the first node, and the second electrode of the fourth transistor is electrically connected with the third node;
the first capacitor is electrically connected with the first electrode of the driving transistor and the first node respectively;
the second capacitor is electrically connected to the first electrode of the driving transistor and the second node, respectively.
8. The pixel compensation circuit according to claim 1, wherein the light emission control unit includes: and a fifth transistor, a gate of which is used for receiving a light emitting control signal, a first electrode of which is electrically connected with the third node, and a second electrode of which is electrically connected with the light emitting device.
9. An array substrate comprising the pixel compensation circuit of any one of claims 1 to 8.
10. A display panel comprising the array substrate according to claim 9.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010029803.5A CN111179850A (en) | 2020-01-13 | 2020-01-13 | Pixel compensation circuit, array substrate and display panel |
| PCT/CN2020/075250 WO2021142871A1 (en) | 2020-01-13 | 2020-02-14 | Pixel compensation circuit and display panel |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202010029803.5A CN111179850A (en) | 2020-01-13 | 2020-01-13 | Pixel compensation circuit, array substrate and display panel |
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| CN111179850A true CN111179850A (en) | 2020-05-19 |
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| CN202010029803.5A Pending CN111179850A (en) | 2020-01-13 | 2020-01-13 | Pixel compensation circuit, array substrate and display panel |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112002281A (en) * | 2020-09-01 | 2020-11-27 | 云谷（固安）科技有限公司 | Pixel circuit driving method |
| CN112071268A (en) * | 2020-08-12 | 2020-12-11 | 武汉华星光电半导体显示技术有限公司 | Display panel and display device |
| CN114360448A (en) * | 2022-01-12 | 2022-04-15 | 深圳市华星光电半导体显示技术有限公司 | Light emitting circuit and display panel |
| CN114765007A (en) * | 2021-01-04 | 2022-07-19 | 京东方科技集团股份有限公司 | Display device, pixel circuit and driving method thereof |
| WO2023050774A1 (en) * | 2021-09-30 | 2023-04-06 | 昆山国显光电有限公司 | Pixel circuit and driving method therefor, and display panel |
| US11756480B2 (en) * | 2021-09-02 | 2023-09-12 | Samsung Display Co., Ltd. | Pixel of a display device, and display device |
| WO2023213214A1 (en) * | 2022-05-06 | 2023-11-09 | 京东方科技集团股份有限公司 | Pixel driving circuit and method, and display panel |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106504699A (en) * | 2016-10-14 | 2017-03-15 | 深圳市华星光电技术有限公司 | AMOLED pixel-driving circuits and driving method |
| CN107767814A (en) * | 2017-11-27 | 2018-03-06 | 合肥鑫晟光电科技有限公司 | Image element circuit, display device and double grid driving transistor |
| CN108597448A (en) * | 2017-03-14 | 2018-09-28 | 鸿富锦精密工业（深圳）有限公司 | Pixel-driving circuit and display device with pixel-driving circuit |
| CN108711398A (en) * | 2018-05-28 | 2018-10-26 | 京东方科技集团股份有限公司 | Pixel circuit and its driving method, array substrate, display panel |
| CN110021265A (en) * | 2019-04-26 | 2019-07-16 | 上海天马微电子有限公司 | A kind of pixel circuit and its driving method, display device and driving method |
| CN110189707A (en) * | 2019-05-30 | 2019-08-30 | 京东方科技集团股份有限公司 | A kind of pixel-driving circuit and its driving method, display device |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6897842B2 (en) * | 2001-09-19 | 2005-05-24 | Intel Corporation | Nonlinearly mapping video date to pixel intensity while compensating for non-uniformities and degradations in a display |
| KR100450761B1 (en) * | 2002-09-14 | 2004-10-01 | 한국전자통신연구원 | Active matrix organic light emission diode display panel circuit |
| KR102241704B1 (en) * | 2014-08-07 | 2021-04-20 | 삼성디스플레이 주식회사 | Pixel circuit and organic light emitting display device having the same |
| CN104485072B (en) * | 2014-12-22 | 2017-03-08 | 昆山国显光电有限公司 | Image element circuit and its driving method and active matrix/organic light emitting display |
| CN104464630B (en) * | 2014-12-23 | 2018-07-20 | 昆山国显光电有限公司 | Pixel circuit and its driving method and active matrix/organic light emitting display |
-
2020
- 2020-01-13 CN CN202010029803.5A patent/CN111179850A/en active Pending
- 2020-02-14 WO PCT/CN2020/075250 patent/WO2021142871A1/en active Application Filing
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106504699A (en) * | 2016-10-14 | 2017-03-15 | 深圳市华星光电技术有限公司 | AMOLED pixel-driving circuits and driving method |
| CN108597448A (en) * | 2017-03-14 | 2018-09-28 | 鸿富锦精密工业（深圳）有限公司 | Pixel-driving circuit and display device with pixel-driving circuit |
| CN107767814A (en) * | 2017-11-27 | 2018-03-06 | 合肥鑫晟光电科技有限公司 | Image element circuit, display device and double grid driving transistor |
| CN108711398A (en) * | 2018-05-28 | 2018-10-26 | 京东方科技集团股份有限公司 | Pixel circuit and its driving method, array substrate, display panel |
| CN110021265A (en) * | 2019-04-26 | 2019-07-16 | 上海天马微电子有限公司 | A kind of pixel circuit and its driving method, display device and driving method |
| CN110189707A (en) * | 2019-05-30 | 2019-08-30 | 京东方科技集团股份有限公司 | A kind of pixel-driving circuit and its driving method, display device |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112071268A (en) * | 2020-08-12 | 2020-12-11 | 武汉华星光电半导体显示技术有限公司 | Display panel and display device |
| CN112002281A (en) * | 2020-09-01 | 2020-11-27 | 云谷（固安）科技有限公司 | Pixel circuit driving method |
| WO2022048275A1 (en) * | 2020-09-01 | 2022-03-10 | 云谷（固安）科技有限公司 | Driving method for pixel circuit |
| CN112002281B (en) * | 2020-09-01 | 2022-08-09 | 云谷（固安）科技有限公司 | Pixel circuit driving method |
| US11854459B2 (en) | 2020-09-01 | 2023-12-26 | Yungu (Gu'an) Technology Co., Ltd. | Method for driving a pixel circuit |
| CN114765007A (en) * | 2021-01-04 | 2022-07-19 | 京东方科技集团股份有限公司 | Display device, pixel circuit and driving method thereof |
| US11587501B2 (en) | 2021-01-04 | 2023-02-21 | Boe Technology Group Co., Ltd. | Display apparatuses, pixel circuits and methods of driving pixel circuit |
| US11756480B2 (en) * | 2021-09-02 | 2023-09-12 | Samsung Display Co., Ltd. | Pixel of a display device, and display device |
| WO2023050774A1 (en) * | 2021-09-30 | 2023-04-06 | 昆山国显光电有限公司 | Pixel circuit and driving method therefor, and display panel |
| CN114360448A (en) * | 2022-01-12 | 2022-04-15 | 深圳市华星光电半导体显示技术有限公司 | Light emitting circuit and display panel |
| WO2023213214A1 (en) * | 2022-05-06 | 2023-11-09 | 京东方科技集团股份有限公司 | Pixel driving circuit and method, and display panel |
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