CN1123882C - Digital signal reproducing circuit - Google Patents
Digital signal reproducing circuit Download PDFInfo
- Publication number
- CN1123882C CN1123882C CN98108001A CN98108001A CN1123882C CN 1123882 C CN1123882 C CN 1123882C CN 98108001 A CN98108001 A CN 98108001A CN 98108001 A CN98108001 A CN 98108001A CN 1123882 C CN1123882 C CN 1123882C
- Authority
- CN
- China
- Prior art keywords
- phase
- signal
- circuit
- phase differential
- digital signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/10009—Improvement or modification of read or write signals
- G11B20/10305—Improvement or modification of read or write signals signal quality assessment
- G11B20/10398—Improvement or modification of read or write signals signal quality assessment jitter, timing deviations or phase and frequency errors
- G11B20/10407—Improvement or modification of read or write signals signal quality assessment jitter, timing deviations or phase and frequency errors by verifying the timing of signal transitions, e.g. rising or falling edges, or by analysing signal slopes
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/0805—Details of the phase-locked loop the loop being adapted to provide an additional control signal for use outside the loop
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/10009—Improvement or modification of read or write signals
- G11B20/10037—A/D conversion, D/A conversion, sampling, slicing and digital quantisation or adjusting parameters thereof
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/10009—Improvement or modification of read or write signals
- G11B20/10046—Improvement or modification of read or write signals filtering or equalising, e.g. setting the tap weights of an FIR filter
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/10009—Improvement or modification of read or write signals
- G11B20/10222—Improvement or modification of read or write signals clock-related aspects, e.g. phase or frequency adjustment or bit synchronisation
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/10009—Improvement or modification of read or write signals
- G11B20/10305—Improvement or modification of read or write signals signal quality assessment
- G11B20/10462—Improvement or modification of read or write signals signal quality assessment consistency with a reference waveform in a given time period, e.g. by calculating correlations or mean square errors
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/14—Digital recording or reproducing using self-clocking codes
- G11B20/1403—Digital recording or reproducing using self-clocking codes characterised by the use of two levels
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/0807—Details of the phase-locked loop concerning mainly a recovery circuit for the reference signal
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B2220/00—Record carriers by type
- G11B2220/20—Disc-shaped record carriers
- G11B2220/25—Disc-shaped record carriers characterised in that the disc is based on a specific recording technology
- G11B2220/2537—Optical discs
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B7/00—Recording or reproducing by optical means, e.g. recording using a thermal beam of optical radiation by modifying optical properties or the physical structure, reproducing using an optical beam at lower power by sensing optical properties; Record carriers therefor
- G11B7/004—Recording, reproducing or erasing methods; Read, write or erase circuits therefor
- G11B7/005—Reproducing
Abstract
A digital signal reproducing circuit which enables precise measurement of a phase difference and jitter components of reproduction signals while realizing miniaturization of the circuit is disclosed. The digital signal reproducing circuit has a phase comparator for detecting a phase difference by using sampled values before and after an edge portion of a reproduction signal from an optical disc outputted from an A/D converter, and a jitter measuring section for detecting a jitter detection signal on the basis of unevenness of the phase difference obtained by the phase comparator.
Description
Technical field
The present invention relates to be used for a kind of digital signal reproducing circuit of reproducing digital signals, refer more particularly to a kind of like this digital signal reproducing circuit, it can detect phase differential and the shake composition that is reproduced signal in reproducing signal.
Background technology
Digital signal reproducing circuit is applicable to reproducing digital signals from the simulating signal of input, and has a synchronous clock reconstructing portion, be used for producing one with import the synchronous clock of simulating signal, just PLL circuit.
The control function that the synchronous clock reconstructing portion is carried out is to produce a clock that is substantially equal to the input signal clock frequency, and produce a phase signal according to detected pulse width between clock that produces and input signal, thereby between the clock composition of clock that makes generation on the basis of phase signal and input signal, realize synchronously.
Be used for reappearing the digital signal reproducing circuit 202 that the disc repruducing apparatus that is recorded in the signal on the CD has comprised Fig. 1.
Disc repruducing apparatus 201 comprises an optical pickup apparatus 214, be used for a branch of rayed on CD 200, and the signal of reflected light playback record on CD 200 according to irradiates light, a waveform equalizer 203, be used for the reproducing signal of optical pickup apparatus 214 outputs is carried out wave shape equalization, and the signal of output waveform equilibrium, an asymmetric correcting circuit 204, be used for the signal of waveform equalizer 203 outputs is carried out asymmetric correction, and output is through the signal after the asymmetric correction, and a binary circuit 205, be used for the conversion of signals of asymmetric correcting circuit 204 outputs is become binary signal, so that export binary signal.Disc repruducing apparatus 201 also comprises: a phase compensator 207 is used for binary signal and a synchronous clock of binary circuit 205 outputs are compared, and exports thus obtained phase signal; Loop filter 208 usefulness simulated mode are come the phase differential of average phase comparer 207 outputs, export an average signal, and a voltage-controlled oscillator 209, be used for producing a synchronous clock, make the signal of loop filter 208 outputs become zero (0).In addition, disc repruducing apparatus 201 comprises a dithering measuring circuit 210, it is made of absolute value circuit 211 and low-pass filter 212, and be fit to measure the shake composition according to the phase signal of phase comparator 207 outputs, a servo circuit 215 is operated object lens by the twin shaft driver in the optical pickup apparatus 214, carries out focus servo and tracking servo; And a controller 213, be used for controlling servo circuit 215 and waveform equalizer 203.
In disc repruducing apparatus 201, be input to shake composition in the signal of disc repruducing apparatus 201 and be according to the phase signal of comparer 207 outputs of synchronous clock reconstructing portion 206 and measure, and the bias adjustment of tracking servo and focus servo is to carry out according to the shake detection signal that records thus.
For example, being used to measure the jitter measurement part 210 of shaking composition can adopt digital processing to calculate the shake detection signal.Like this, jitter measurement part 210 just can be measured the phase signal of input pulse by the high frequency sampling clock, and average its absolute value, therefrom calculates the shake detection signal.Controller 213 is carried out servo bias adjustment according to the shake detection signal that jitter measurement part 210 calculates.
Simultaneously, although in simulation process than the absolute value that is easier to typical pulse width, simulation process aspect deviation and performance accuracy less than digital processing.In addition, when calculating mean square, also have difficulties.Therefore, if measure the shake composition with simulation process, it is bad that deviation or performance accuracy will become.
Yet, handle for combine digital, the temporal resolution that must adopt corresponding required precision to phase differential pulse sample.That is to say, need the clock of a certain frequency, this frequency is the inverse of temporal resolution, or needs a high-precision delay circuit.
Therefore, in view of the problem that prior art faced, the purpose of this invention is to provide a kind of digital signal reproducing circuit, it can go out phase differential and shake composition with very high precision measure, can also realize the miniaturization of circuit simultaneously.
Summary of the invention
According to digital signal reproducing circuit provided by the present invention, comprising: mould/analog-to-digital conversion apparatus is used for input signal is carried out mould/number conversion, so that the output signal of the A/D conversion equipment with edge part to be provided; Phase comparison device, dispose described phase comparison device, with by calculating described edge part phase differential approaching in time, between first and second sampling values on the opposite side from an output signal of mould/analog-to-digital conversion apparatus, and the phase place of the phase place of comparator input signal and local clock; And jitter measuring apparatus, be used for by calculating from the unevenness acquisition jitter measurement amount of the phase differential of phase comparator acquisition, described unevenness is to be calculated by the phase differential that described phase comparator calculates by normalization, handle normalized phase differential, and the phase differential of handling is carried out integration in a period of time.
Description of drawings
Fig. 1 is a circuit diagram, has represented the structure of ordinary numbers signal reproduction circuit among the figure.
Fig. 2 represents the circuit structure diagram of a disc repruducing apparatus, has the digital signal reproducing circuit of one embodiment of the invention in this device.
Fig. 3 is the circuit structure diagram of the phase comparator in the digital signal reproducing circuit.
Fig. 4 is the circuit structure diagram of the jitter measurement part in the digital signal reproducing circuit.
Fig. 5 A to 5F is the curve map of reproducing signal, is used for representing to be input to the reproducing signal of digital signal reproducing circuit.
Fig. 6 is a process flow diagram, is used for illustrating the part operation of phase comparator.
Embodiment
The digital signal reproducing circuit of the embodiment that wants below that present invention will be described in detail with reference to the accompanying.
Digital signal reproducing circuit as the embodiment of the invention is used on the disc repruducing apparatus 1, as shown in Figure 2, in this device, the illumination that optical pickup apparatus 11 sends is mapped on the CD 100, the light redisplaying information signal that reflects on the signal recording surface according to CD 100.This digital signal reproducing circuit is used to shake the bias adjustment that becomes to assign to carry out focus servo and tracking servo according to detected from the information signal that reappears, and control waveform balanced device or the like device.
Be contained in the digital signal reproducing circuit 2 in the disc repruducing apparatus 1, comprise: a waveform equalizer 3, be used for the reproducing signal of optical pickup apparatus 11 output is carried out wave shape equalization, thereby to the signal of A/D converter 4 output waveform equilibriums; A/D converter 4, the signal that waveform equalizer 3 is exported carries out the A/D conversion; A phase comparator 5, the forward and backward sampled value in position, an edge of employing A/D converter 4 output signals calculates one and differs; A wave filter 6 is used for the phase differential that smooth phase comparer 5 is exported, and exports a signal that is converted into DC current; A variable oscillator 7 is used for reappearing a synchronous clock according to the output signal of wave filter 6; A jitter measurement part 9, the unevenness of the phase differential that obtains according to phase comparator 5 detects a shake detection signal, and a controller 10, as described below, it comes control waveform balanced device 3 and servo circuit 12 according to the shake detection signal of jitter measurement part 9 outputs.
In digital signal reproducing circuit 2, A/D converter 4, phase comparator 5, wave filter 6 and variable oscillator 7 have constituted a synchronous clock reconstructing portion 8, i.e. a PLL (phaselocked loop) circuit.Synchronous clock reconstructing portion 8 can reappear a synchronous clock according to the reproducing signal of variable oscillator 7, so that make this synchronous clock and reproducing signal synchronous.
Has digital signal reproducing circuit 2 in the disc repruducing apparatus 11, and comprise an outer optical pickup apparatus 11, be used for a laser beam irradiation to the signal recording surface of CD 100, and accept the light of its reflection, servo circuit 12 moves up focus direction and track side by a twin shaft driver and is contained in the object lens that do not have expression among the figure in the optical pickup apparatus 11.
Disc repruducing apparatus 1 can use the digital signal reproducing circuit 2 of said structure to come control waveform balanced device 3 and servo circuit 12, so that reduce from the signal of CD 100 reproductions and the shake composition between the synchronous clock.
The each several part circuit structure that constitutes digital signal reproducing circuit 2 below will be described.
3 pairs of reproducing signals that obtain from CD 100 of waveform equalizer are carried out wave shape equalization.The structure of waveform equalizer 3 is the filter circuits with predetermined transfering function, and this transport function is controlled by controller 10, so just can reduce the shake composition between reproducing signal and the synchronous clock.Reproducing signal through wave shape equalization in waveform equalizer 3 is provided for A/D converter 4.
A/D converter 4 will convert digital signal to as the wave shape equalization reproducing signal of simulating signal.The sampling clock of A/D converter 4 is exactly the synchronous clock of synchronous clock reconstructing portion 8.
For example, for digital video disk, data are that conversion interval according to 3T to 11T and 14T (T represents the cycle of synchronous clock) is recorded on the medium in accordance with regulations.Therefore, the sampling clock of A/D converter 4 adopts the frequency of synchronous clock, just can guarantee reappearance.The reproducing signal that is converted to numerical data by A/D converter 4 is provided for the phase comparator 5 of synchronous clock reconstructing portion 8.
The numerical data of reproducing signal is imported into phase comparator 5.Phase comparator 5 and shake test section 9 detect a phase differential and a shake detection signal respectively according to the numerical data of the reproducing signal of input.
Phase comparator 5 detects the phase differential between reproducing signal and the synchronous clock.As shown in Figure 3, phase comparator 5 comprises: the d type flip flop circuit 21 as a sampling delay device; A totalizer 22 is used for having postponed to import after the synchronous clock unit on the value in it being added in from a value of A/D converter 4 by d type flip flop circuit 21, and a multiplier 23, is used on duty with-1 with totalizer 22 outputs.Phase comparator 5, also comprise: a switch 24, when the binit position is 0 (+), totalizer 22 is connected to d type flip flop circuit 25, when the binit position is 1 (-), multiplier 23 is connected to d type flip flop circuit 25, as mentioned below, trigger d type flip flop circuit 25 with an EXOR (XOR) circuit 28 detected edge detection signals, and a subtracter 26, be used for from the output valve of d type flip flop circuit 21, deducting the output valve of A/D converter 4.Phase comparator 5 further comprises a d type flip flop 27 that is triggered by EXOR circuit 28 detected edge detection signals, and above-mentioned EXOR circuit 28, and it exports an edge detection signal when detecting the edge of reproducing signal.Hereinafter will describe in detail, EXOR circuit 28 is exported this edge detection signal when input signal strides across a threshold value.
The principle of work of phase difference detection below will be described with reference to Fig. 5 A to 5F and Fig. 6.
Phase comparator 5 passes through d type flip flop circuit 21, totalizer 22, and the forward and backward phase difference value in position, an edge that threshold values obtain is crossed in switch 24 and d type flip flop 25 outputs.Also by d type flip flop circuit 21, subtracter 26 and d type flip flop 27 circuit are exported the poor of this forward and backward numerical value in position, edge, just phase differential full scale value to phase comparator 5.In addition, when the position, edge strode across threshold value, phase comparator 5 was by edge detection signal of EXOR circuit 28 outputs.Be imported into jitter measurement part 9 from phase differential, phase differential full scale value and the edge detection signal of phase comparator 5 outputs.
As shown in Figure 4, shake test section 9 comprises: a normalization circuit 31 as divider, and it utilizes phase differential full scale value that phase differential is carried out normalization; A squaring circuit 32, to asking through normalization circuit 31 normalized phase differential square, an integrating circuit 33, the phase differential integration that squaring circuit 32 is calculated, and a counter 38 are used for edge detection signal counting to phase comparator 5 outputs.
Integrating circuit 33 comprises: a d type flip flop circuit 34 provides the phase differential of being asked square and be subjected to edge detection signal operation by squaring circuit 32 to it; A totalizer 37 is used for the output valve of d type flip flop circuit 34 is added on the output valve of following d type flip flop circuit 35; D type flip flop circuit 35 is from totalizer 37 output and be subjected to the signal of edge detection signal operation to be provided for this flip-flop circuit 35; Be provided for d type flip flop circuit 36 from the signal of d type flip flop circuit 35 outputs.In this integral part 33,, and when reaching predetermined value, exports by counter this integrated value to the value integration of squaring circuit 32 outputs.
Like this, jitter measurement part 9 just can detect the shake detection signal, it be one at phase differential be input on the basis of the phase differential full scale value in it by normalized square mean phase differential.
When counter 38 reaches predetermined value, from counter 38 to clear signal of d type flip flop circuit 35 inputs, and to storage signal of d type flip flop circuit 36 inputs.When the input clear signal, d type flip flop 35 is removed the value of storage.When the input storage signal, the output of d type flip flop 36 storages and output d type flip flop 35.Be imported into controller 10 from the signal of d type flip flop 36 outputs as the shake detection signal.
Can also constitute integral part 33 by the device that utilizes timer one class, thus the phase differential of output predetermined time cycle integrates, and the integration that replacement is carried out according to the edge count value.
For the output of average jitter measure portion 9, need with a divider the phase differential of integration divided by the quantity of importing data.If being set at 2 by the input data bulk of integral part 33 integrations
n(n is an integer) is by displacement or mobile integrated value that low-order bit just can on average be exported of a bit.
Jitter measurement part 9 can also replace squaring circuit 32 with an absolute value circuit.In this case, can reduce calculated amount.
Controller 10 control waveform balanced devices 3 descend the shake detected signal value of jitter measurement part 9 outputs.For example, can be by the transport function of controller 10 control waveform balanced devices 3, thus reduce shake composition between reproducing signal and the synchronous clock.
Like this, digital signal reproducing circuit 2 just can detect the numerical data of phase differential accurately, does not use the high frequency sampling clock not needing to resemble in the prior art.In addition, digital signal reproducing circuit 2 can detect phase differential and shake composition according to the numerical data of phase differential.Therefore, this digital signal reproducing circuit 2 can detect phase differential and shake composition accurately.
In addition, because the phase differential that calculates is by normalization, even fluctuation appears in the amplitude of reproducing signal, digital signal reproducing circuit 2 still can accurately be measured the shake composition.
Therefore, because digital signal reproducing circuit 2 can accurately be measured the shake composition, it can carry out the correction work of synchronous clock accurately.
Disc repruducing apparatus 1 with this digital signal reproducing circuit 2 can reappear the signal with slight damage.In addition, this disc repruducing apparatus 1 can also be carried out the bias adjustment of servo circuit 12 accurately according to the shake detection signal.
Phase difference detection mode in the digital signal reproducing circuit 2 below will be described.Fig. 5 A to 5F represents to be input to the reproducing signal of phase comparator 5.In this case, digital signal reproducing circuit 2 is poor according to the flow process detected phase shown in Fig. 6.
Although the reproducing signal of representing in the 5F at Fig. 5 A is continuous, these signals are actually samples according to the synchronous clock that is input to phase comparator 5.That is to say that the value of reproducing signal is sampled according to numerical data in such a way, change the value that departs from a threshold value V0 with A/D converter 4.
In 5F, threshold value V0 is voltage 0V at Fig. 5 A, and a sampled value d (i-1) of sampling reproducing signal is the value that was right after before striding across the position, edge of threshold value V.Signal d (i) is a sampled value that is right after after striding across the position, edge of threshold value V0.That is to say that the sampling interval between sampled value d (i-1) and the sampled value d (i) equals a unit gap of synchronous clock.
From the rising edge position of reproducing signal, if reproducing signal has been compared a phase delay with synchronous clock, as shown in Fig. 5 A, the point of crossing (hereinafter referred to as tr pt) between rising edge position and the threshold value V0 is positioned at after the intermediate point of sampling interval.In this case, the relation between sampled value d (i-1) and the sampled value d (i) is | d (i) |＜| d (i-1) |, and d (i)+d (i-1)＜0.
Equally, from the negative edge position of reproducing signal, if reproducing signal has been compared a phase delay with synchronous clock, as shown in Fig. 5 D, tr pt is positioned at after the intermediate point of sampling interval.In this case, the relation between sampled value d (i-1) and the sampled value d (i) is,
| d (i) |＜| d (i-1) |, and d (i)+d (i-1)＞0.
On the other hand, from the rising edge position of reproducing signal, if reproducing signal is compared with synchronous clock a leading phase place is arranged, shown in Fig. 5 C, tr pt is positioned at before the intermediate point of sampling interval.In this case, the relation between sampled value d (i-1) and the sampled value d (i) is
| d (i) |＞| d (i-1) |, and d (i)+d (i-1)＞0.
Equally, from the back decline position of reproducing signal, if reproducing signal is compared with synchronous clock a leading phase place is arranged, shown in Fig. 5 F, tr pt is positioned at before the intermediate point of sampling interval.In this case, the relation between sampled value d (i-1) and the sampled value d (i) is
| d (i) |＞| d (i-1) |, and d (i)+d (i-1)＜0.
Fig. 5 B represents reproducing signal and the synchronous situation of synchronous clock seen from the rising edge position of reproducing signal, and Fig. 5 E represents from the back reproducing signal of seeing along the position of reproducing signal and the synchronous situation of synchronous clock.In both cases, tr pt is positioned on the intermediate point of sampling interval.This moment can obtain | d (i) |=d (i-1) | relation.
On the basis of sampled value d (i-1) forward and backward and sampled value d (i) from the position, edge of the forward and backward acquisition of tr pt of reproducing signal, phase comparator 5 is derived a phase differential d (i)+d (i-1), and derives a phase differential full scale value d (i-1)-d (i).
The EXOR circuit 28 of phase comparator 5 is the binit position of sampled value d (i-1) and sampled value d (i) relatively, and exports an edge detection signal when differing from one another in the binit position.
Therefore, because d type flip flop circuit 25 and this edge detection signal of d type flip flop circuit 27 usefulness trigger, have only phase differential and the phase differential full scale value calculated according to the forward and backward sampled value in position, edge that strides across threshold value V0 to be output to jitter measurement part 9.As mentioned above, if the phase place of reproducing signal is more leading than synchronous clock, just can obtain at rising edge and negative edge position | d (i) |＞| d (i-1) |.Yet owing to the symbol about d (i)+d (i-1) is opposite, only under the situation at negative edge position, the switch 24 of phase comparator 5 just can pass through multiplier 23 to d type flip flop circuit 25 phase difference outputs from totalizer 22.
Can illustrate also that with reference to the process flow diagram of Fig. 6 phase comparator 5 is detected phase differences how.
At first, in step S1, read sampled value d (i-1) and sampled value d (i) continuously by d type flip flop circuit 21.Multiply by sampled value d (i-1) at step S2 with sampled value d (i) then, and judge whether its product is negative value.If this product is a negative value, sampled value d (i-1) that obtains and sampled value d (i) just adopt the forward and backward value in position, edge that strides across threshold value continuously.In phase comparator 5,, and carry out output to jitter measurement part 9 according to the result of comparison with EXOR circuit 28 relatively sampled value d (i) and sampled value d (i-1).
If this product is a negative value, program just enters step S3.If product be on the occasion of, that is to say, if reproducing signal does not stride across threshold value, program just enter the step S6.
Definite sampled value d's (i) is positive and negative in step S3.If sampled value d (i) is a negative value, sampled value d (i-1) and sampled value d (i) are exactly the value of negative edge part.Then the step calculate among the S4 phase differential ΔΦ (i)=-(d (i-1)+d (i)).
On the other hand, if sampled value d (i) be on the occasion of, sampled value d (i-1) and sampled value d (i) are exactly the value of rising edge part.In step S5, calculate one then and differ ΔΦ (i)=d (i-1)+d (i).
If the RF signal does not stride across threshold value, the phase differential among the step S6 is exactly previous phase differential ΔΦ (i)=ΔΦ (i-1).
Just can detect by jitter measurement part 9 normalized phase differential mean values according to the phase differential that calculates like this.
A numerical tabular shown in the use table 1 replaces according to phase differential and phase differential full scale value phase differential being carried out normalized normalization circuit 31.
Table 1
| PE | PA | POUT |
| -8 | -8 | 225 |
| -7 | -8 | 196 |
| -6 | -8 | 144 |
| -5 | -8 | 100 |
| -4 | -8 | 64 |
| -3 | -8 | 36 |
| -2 | -8 | 16 |
| -1 | -8 | 4 |
| 1 | -8 | 4 |
| 2 | -8 | 16 |
| 3 | -8 | 36 |
| 4 | -8 | 64 |
| 5 | -8 | 100 |
| 6 | -8 | 144 |
| 7 | -8 | 196 |
| -7 | -7 | 255 |
| -6 | -7 | 188 |
| -5 | -7 | 131 |
| -4 | -7 | 84 |
| -3 | -7 | 47 |
| -2 | -7 | 21 |
| -1 | -7 | 5 |
| 0 | -7 | 0 |
| 1 | -7 | 5 |
| 2 | -7 | 21 |
| 3 | -7 | 47 |
| 4 | -7 | 84 |
| PE | PA | POUT |
| 5 | -7 | 131 |
| 6 | -7 | 188 |
| 7 | -7 | 255 |
| -6 | -6 | 255 |
| -5 | -6 | 178 |
| -4 | -6 | 114 |
| -3 | -6 | 64 |
| -2 | -6 | 28 |
| -1 | -6 | 7 |
| 0 | -6 | 0 |
| 1 | -6 | 7 |
| 2 | -6 | 28 |
| 3 | -6 | 64 |
| 4 | -6 | 114 |
| 5 | -6 | 178 |
| 6 | -6 | 255 |
| -5 | -5 | 255 |
| -4 | -5 | 164 |
| -3 | -5 | 92 |
| -3 | -5 | 41 |
| -1 | -5 | 10 |
| 0 | -5 | 0 |
| 1 | -5 | 10 |
| 2 | -5 | 41 |
| 3 | -5 | 92 |
| 4 | -5 | 164 |
| 5 | -5 | 255 |
| -4 | -4 | 255 |
| -3 | -4 | 144 |
| PE | PA | POUT |
| -2 | -4 | 64 |
| -1 | -4 | 16 |
| 0 | -4 | 0 |
| 1 | -4 | 16 |
| 2 | -4 | 64 |
| 3 | -4 | 144 |
| 4 | -4 | 255 |
| -3 | -3 | 255 |
| -2 | -3 | 114 |
| -1 | -3 | 28 |
| 0 | -3 | 0 |
| 1 | -3 | 28 |
| 2 | -3 | 114 |
| 3 | -3 | 255 |
| -2 | -2 | 255 |
| -1 | -2 | 64 |
| 0 | -2 | 0 |
| 1 | -2 | 64 |
| 2 | -2 | 255 |
| -1 | -1 | 255 |
| 0 | -1 | 0 |
| 1 | -1 | 255 |
| -1 | 1 | 255 |
| 0 | 1 | 0 |
| 1 | 1 | 255 |
| -2 | 2 | 255 |
| -1 | 2 | 64 |
| 0 | 2 | 0 |
| 1 | 2 | 64 |
| PE | PA | POUT |
| 2 | 2 | 255 |
| -3 | 2 | 255 |
| -2 | 3 | 114 |
| -1 | 3 | 28 |
| 0 | 3 | 0 |
| 1 | 3 | 28 |
| 2 | 3 | 114 |
| 3 | 3 | 225 |
| -4 | 4 | 225 |
| -3 | 4 | 144 |
| -2 | 4 | 64 |
| -1 | 4 | 16 |
| 0 | 4 | 0 |
| 1 | 4 | 16 |
| 2 | 4 | 64 |
| 3 | 4 | 144 |
| 4 | 4 | 255 |
| -5 | 5 | 255 |
| -4 | 5 | 164 |
| -3 | 5 | 92 |
| -2 | 5 | 41 |
| -1 | 5 | 10 |
| 0 | 5 | 0 |
| 1 | 5 | 10 |
| 2 | 5 | 41 |
| 3 | 5 | 92 |
| 4 | 5 | 164 |
| 5 | 5 | 255 |
| -6 | 6 | 255 |
| PE | PA | POUT |
| -5 | 6 | 178 |
| -4 | 6 | 114 |
| -3 | 6 | 64 |
| -2 | 6 | 28 |
| -1 | 6 | 7 |
| 0 | 6 | 0 |
| 1 | 6 | 7 |
| 2 | 6 | 28 |
| 3 | 6 | 64 |
| 4 | 6 | 114 |
| 5 | 6 | 178 |
| 6 | 6 | 255 |
| -7 | 7 | 255 |
| -6 | 7 | 188 |
| -5 | 7 | 131 |
| -4 | 7 | 84 |
| -3 | 7 | 47 |
| -2 | 7 | 21 |
| -1 | 7 | 5 |
| 0 | 7 | 0 |
| 1 | 7 | 5 |
| 2 | 7 | 21 |
| 3 | 7 | 47 |
| 4 | 7 | 85 |
| 5 | 7 | 131 |
| 6 | 7 | 188 |
| 7 | 7 | 255 |
Numerical tabular shown in the table 1 is by phase differential (PE), and phase differential full scale value (PA) and normalized phase differential (POUT) constitute.
Normalized phase differential (POUT) is confirmed as POUT=(PE/PA) 2 * 256.In table 1, on the qualification basis of phase differential and phase differential full scale value, keep | PE|＞| the relation of PA|.
That is to say, when using this numerical tabular, do not need counting circuit.Therefore, can obtain normalized phase differential with small-scale circuit.
If imported the phase differential or the phase differential full scale value that do not have in the table, can be by exporting 0 or certain numerical value prevents maloperation.In addition, in order to dwindle circuit scale, also can adopt numerical value at random.
In addition, squaring circuit and absolute value circuit can use above-mentioned table to calculate the square value and the absolute value of phase differential respectively.In addition, by to normalization and the mean square value or the integration of absolute value mean value, when input value phase differential and phase differential full scale value, can detect normalized phase differential mean value.
Like this, because digital signal reproducing signal 2 comes measure phase difference and shake composition according to numerical data, it can make reproducing signal and synchronous clock synchronous accurately.
Have phase comparison device according to digital signal reproducing circuit of the present invention, be used for so just detecting phase differential as numerical data according to detecting a phase differential in the forward and backward sampled value in the position, edge of reproducing signal.In addition, have the jitter measurement part in the digital signal reproducing circuit, be used for calculating the shake composition of reproducing signal, so just can accurately measure the shake composition according to the phase differential that phase comparison device calculates as numerical data.
In addition, digital signal reproducing circuit also has phase differential is carried out normalized normalization device, therefore, even when fluctuation appears in the amplitude of reproducing signal, still can accurately measure the shake composition of reproducing signal.
Claims (5)
1. digital signal reproducing circuit comprises:
Mould/analog-to-digital conversion apparatus is used for input signal is carried out mould/number conversion, so that the output signal of the A/D conversion equipment with edge part to be provided;
Phase comparison device, dispose described phase comparison device, with by calculating described edge part phase differential approaching in time, between first and second sampling values on the opposite side from an output signal of mould/analog-to-digital conversion apparatus, and the phase place of the phase place of comparator input signal and local clock; And
Jitter measuring apparatus, be used for by calculating from the unevenness acquisition jitter measurement amount of the phase differential of phase comparator acquisition, described unevenness is to be calculated by the phase differential that described phase comparator calculates by normalization, handle normalized phase differential, and the phase differential of handling is carried out integration in a period of time.
2. according to the digital signal reproducing circuit of claim 1, wherein jitter measuring apparatus comprises the normalization device, be used for the phase differential that phase comparison device calculates is carried out normalization, and the square mean value calculation apparatus, be used for according to the mean value of calculating square value through the normalized phasometer of normalization device.
3. according to the digital signal reproducing circuit of claim 1, wherein shake pick-up unit and comprise the normalization device, be used for the phase differential that phase comparison device calculates is carried out normalization, and the absolute value average computing device, be used for according to calculating average absolute through the normalized phasometer of normalization device.
4. digital signal reproducing circuit as claimed in claim 1, wherein said phase comparison device also comprises the device that is used to obtain the full scale phase differential.
5. according to the digital signal reproducing circuit of claim 1, wherein further comprise the Waveform equalizing device of input signal being carried out wave shape equalization, so that to the signal of mould/analog-to-digital conversion apparatus output waveform equilibrium, this Waveform equalizing device is to control according to the output signal of jitter measuring apparatus.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP064820/97 | 1997-03-18 | ||
| JP064820/1997 | 1997-03-18 | ||
| JP06482097A JP3915163B2 (en) | 1997-03-18 | 1997-03-18 | Digital signal regeneration circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1199223A CN1199223A (en) | 1998-11-18 |
| CN1123882C true CN1123882C (en) | 2003-10-08 |
Family
ID=13269282
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN98108001A Expired - Fee Related CN1123882C (en) | 1997-03-18 | 1998-03-18 | Digital signal reproducing circuit |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US6100724A (en) |
| JP (1) | JP3915163B2 (en) |
| KR (1) | KR100623890B1 (en) |
| CN (1) | CN1123882C (en) |
| MY (1) | MY117953A (en) |
Families Citing this family (26)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100234849B1 (en) * | 1997-06-30 | 1999-12-15 | 김영환 | Phase difference detection circuit in lcd |
| SG65019A1 (en) * | 1997-09-13 | 1999-09-21 | Disk Ware Co Ltd | Jitter measuring method utilizing a/d conversion and device |
| JPH11317018A (en) * | 1998-04-30 | 1999-11-16 | Toshiba Corp | Disk reproducing device and rf amplifier control circuit |
| GB9809450D0 (en) * | 1998-05-01 | 1998-07-01 | Wandel & Goltermann Limited | Jitter measurement |
| JP3486119B2 (en) * | 1998-11-13 | 2004-01-13 | 松下電器産業株式会社 | Multi-rate clock generator and multi-rate digital data reproducing apparatus |
| US6724381B2 (en) * | 1999-03-26 | 2004-04-20 | Canon Kabushiki Kaisha | Signal processing apparatus for generating clocks phase-synchronized with input signal |
| KR100339478B1 (en) * | 1999-09-18 | 2002-05-31 | 구자홍 | An apparatus and method for recording the data on a optical disc using optimal writing condition |
| US6807134B2 (en) * | 1999-12-28 | 2004-10-19 | Matsushita Electric Industrial Co., Ltd. | Asymmetry detection apparatus, jitter detection apparatus, and recording/reproduction apparatus |
| US6680887B2 (en) * | 2000-05-15 | 2004-01-20 | Matsushita Electric Industrial Co., Ltd. | Optical disk apparatus and PLL circuit |
| JP3820856B2 (en) * | 2000-08-07 | 2006-09-13 | ヤマハ株式会社 | Optical disk recording device |
| JP3576137B2 (en) * | 2000-12-20 | 2004-10-13 | 株式会社ソニー・コンピュータエンタテインメント | Optical disc apparatus, servo adjustment method for optical disc apparatus, servo adjustment program for optical disc, and computer-readable recording medium recording servo adjustment program for optical disc |
| US6970403B2 (en) * | 2001-01-25 | 2005-11-29 | Dphi Acquisition, Inc. | Calibration of tracking error signal offset in a tracking servo system |
| US7522480B2 (en) | 2001-01-25 | 2009-04-21 | Dphi Acquisitions, Inc. | Digital tracking servo system with multi-track seek with an acceleration clamp |
| JP4206672B2 (en) * | 2002-03-01 | 2009-01-14 | 日本電気株式会社 | Receiver circuit |
| KR20040009799A (en) * | 2002-07-25 | 2004-01-31 | 삼성전자주식회사 | Method of adjusting tilt using jitter feedback and apparatus thereof |
| EP1388850A1 (en) * | 2002-08-06 | 2004-02-11 | Deutsche Thomson-Brandt GmbH | Method for detecting a wobble signal |
| US7206368B2 (en) * | 2002-10-30 | 2007-04-17 | Avago Tehnologies Fiber Ip (Singapore) Pte. Ltd. | Compensating jitter in differential data signals |
| US7133654B2 (en) * | 2003-08-07 | 2006-11-07 | International Business Machines Corporation | Method and apparatus for measuring communications link quality |
| TWI371970B (en) * | 2004-07-16 | 2012-09-01 | Thomson Licensing Sa | Preventing picture jitter in a digitized video signal |
| US7564897B2 (en) * | 2004-07-22 | 2009-07-21 | Advantest Corporation | Jitter measuring apparatus, jitter measuring method and PLL circuit |
| US20070047412A1 (en) * | 2005-08-31 | 2007-03-01 | Yuan-Chin Liu | Jitter measuring method and device thereof |
| JP4583347B2 (en) * | 2006-07-19 | 2010-11-17 | 三洋電機株式会社 | Optical disk signal processing device |
| JP2009099169A (en) * | 2007-10-15 | 2009-05-07 | Rohm Co Ltd | Jitter counter and optical disk apparatus using the same |
| JP4887267B2 (en) * | 2007-11-28 | 2012-02-29 | ルネサスエレクトロニクス株式会社 | Information playback device |
| US9618965B2 (en) * | 2015-05-15 | 2017-04-11 | Tektronix, Inc. | Dynamic calibration of data patterns |
| JP7139675B2 (en) * | 2018-04-27 | 2022-09-21 | セイコーエプソン株式会社 | Resampling circuit, physical quantity sensor unit, inertial measurement device and structure monitoring device |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60249496A (en) * | 1984-05-25 | 1985-12-10 | Teac Co | Jitter detector of reproduced video signal |
| JPH0750926B2 (en) * | 1991-07-08 | 1995-05-31 | 三星電子株式会社 | Jitter detection circuit |
| JPH0541877A (en) * | 1991-08-06 | 1993-02-19 | Sharp Corp | Jitter elimination device for magnetic recording and reproducing device |
| JPH08273182A (en) * | 1995-03-31 | 1996-10-18 | Seiko Epson Corp | Rotary recording device |
| JP3148590B2 (en) * | 1995-07-27 | 2001-03-19 | 株式会社ケンウッド | Automatic adjustment method of focus servo |
| KR0186138B1 (en) * | 1995-12-23 | 1999-04-15 | 구자홍 | Data reproducing device for a digital disc |
-
1997
- 1997-03-18 JP JP06482097A patent/JP3915163B2/en not_active Expired - Fee Related
-
1998
- 1998-03-10 US US09/037,333 patent/US6100724A/en not_active Expired - Lifetime
- 1998-03-18 CN CN98108001A patent/CN1123882C/en not_active Expired - Fee Related
- 1998-03-18 KR KR1019980009159A patent/KR100623890B1/en not_active IP Right Cessation
- 1998-03-18 MY MYPI98001177A patent/MY117953A/en unknown
Also Published As
| Publication number | Publication date |
|---|---|
| MY117953A (en) | 2004-08-30 |
| KR19980080386A (en) | 1998-11-25 |
| JP3915163B2 (en) | 2007-05-16 |
| CN1199223A (en) | 1998-11-18 |
| US6100724A (en) | 2000-08-08 |
| JPH10261269A (en) | 1998-09-29 |
| KR100623890B1 (en) | 2006-12-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN1123882C (en) | Digital signal reproducing circuit | |
| JP3698836B2 (en) | Digital signal reproduction device | |
| WO1998047136A9 (en) | Processing of disc-drive pickup signals | |
| WO1998047136A2 (en) | Processing of disc-drive pickup signals | |
| JP2002324360A (en) | Signal processing circuit and signal processing method | |
| CN1185634C (en) | Tracking error detector | |
| CN1096067C (en) | Optical disk reproducing apparatus | |
| KR920010214B1 (en) | Controlled oscillator circuit | |
| CN1208766C (en) | Device and method for determining differences between phase referrence signal and oscillation signals | |
| CN1253883C (en) | Clock signal generating system and data reproducing device using swinging signal | |
| NL1020242C2 (en) | Device and method for generating an RF signal and control signals in an optical disk system. | |
| JPH0556591B2 (en) | ||
| CN1229782C (en) | Reproducing method and device | |
| JP3485088B2 (en) | Signal processing circuit and signal processing method | |
| CN1354461A (en) | Clock drawing equipment for optical disk reproducing device | |
| JP2712195B2 (en) | Optical disc playback device | |
| CN1241189C (en) | Track error detection device having a function of removing a phase offset, and phase offset removing method thereof | |
| CN1300784C (en) | Information reproducing apparatus and method | |
| CN1220977C (en) | Aperture retion measuring device of optical recording medium with pre-pit | |
| CN101335042A (en) | Information recording system and an information recording method | |
| JP3339972B2 (en) | Optical disk drive device and information signal evaluation device | |
| JP3724411B2 (en) | Signal processing circuit and signal processing method | |
| CN1471088A (en) | Optical recording medium continuous gap detection apparatus and method | |
| JP3393421B2 (en) | Clock generation circuit and optical disk device | |
| JP4948450B2 (en) | Signal processing device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20031008 Termination date: 20150318 |
|
| EXPY | Termination of patent right or utility model |