JP3393421B2 - Clock generation circuit and optical disk device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock generation circuit and an optical disk device, and can be applied to a reproducing device such as a CD-ROM drive for generating a system clock.

[0002]

2. Description of the Related Art Conventionally, in a CD-ROM drive, after roughly adjusting the rotational speed of the spindle motor to a prescribed rotational speed, the rotational speed of the spindle motor is finely adjusted so that the reproduction signal is synchronized with the system clock. It is designed to be controlled.

That is, in the CD-ROM, after the data string to be recorded is converted into a prescribed data structure, the EFM (Ei
ght to Fourteen Modulation) By being recorded after being modulated, pits are sequentially formed and predetermined data is formed so that the signal level of the reproduction signal changes within a period of 3T to 11T with respect to the basic period T. It is designed to be recorded.

On the other hand, the conventional CD-ROM drive irradiates a laser beam from the optical pickup onto the CD-ROM while the CD-ROM is rotationally driven by a spindle motor, and the return light of the laser beam is picked up by the optical pickup. To receive light. As a result, the CD-ROM drive generates a reproduction signal whose signal level changes according to the amount of return light, and binarizes the reproduction signal to generate a binarized signal.

Further, the CD-ROM drive, as shown in FIG. 9, uses the edge of the binarized signal SU (FIG. 9 (A)) as a reference and the edge signal SE () by the system clock CK (FIG. 9 (C)). 9B) is generated, and the system clock CK is counted during the period in which the signal level of the binarized signal SU rises with reference to the edge signal SE.

In this case, when the system clock CK and the binarized signal SU are in phase synchronization with each other, the count value of 10 can be obtained for the reproduction signal of the period 11T, while the system clock CK and the binary signal SU can be obtained. When the frequency of the binarized signal SU is largely deviated, a count value other than the value 10 can be obtained. By the way, Fig. 9 (D) and (E)
Indicates a case where the frequency of the system clock CK is lower than that of the binarized signal SU, and in this case, a count value of 9 is obtained.

As a result, in the CD-ROM drive, the drive signal of the spindle motor is controlled by arithmetic processing so that the maximum count value becomes 10, and the rotation speed of the spindle motor is roughly set to the reference rotation speed. Set.

Further, when the rotation speed of the spindle motor is roughly set to the reference rotation speed in this way, the CD-ROM drive controls the rotation of the spindle motor as follows.
The spindle motor is rotated by forming a servo loop so that the reproduction signal is phase-synchronized with the system clock by switching to the rotation control based on the phase comparison result of the system clock and the binarized signal.

As a result, in the CD-ROM, the reproduction signal is rotationally driven so as to be synchronized with the system clock, and the laser beam irradiation position is maintained at a prescribed linear velocity, that is, under the condition that the linear velocity is constant. It is driven to rotate. Further, in the CD-ROM drive, a system clock which is phase-synchronized with the reproduction signal can be obtained, and the reproduction signal RF is processed using this system clock.

[0010]

By the way, this kind of CD
-The ROM drive is required to shorten the access time by being used by connecting it to a computer or the like. On the other hand, in the CD-ROM drive,
Since the CD-ROM is driven to rotate under the condition that the linear velocity is constant, it takes time to switch the rotation speed of the spindle motor, and there is a disadvantage that the time required for access becomes longer accordingly. In particular, when the CD-ROM is rotationally driven at a speed several times higher than the standard in order to increase the transfer speed of the reproduced data, it takes a lot of time to switch the speed of the spindle motor, and power is consumed. There is a drawback to consume.

As a method of solving this drawback, a method of driving a CD-ROM prepared under the condition of constant linear velocity under the condition of constant angular velocity can be considered.

That is, if the spindle motor is driven under the condition that the angular velocity is constant, the switching of the rotational speed can be omitted, and the inner and outer circumferences can be accessed only by seeking the optical pickup, and the time required for the access can be shortened. You can

However, in this way, the CD-ROM
In the drive, the linear velocity of the laser beam irradiation position changes greatly between the inner circumference side and the outer circumference side.
Contrary to the ROM drive, it is necessary to synchronize the system clock with the reproduced signal.

In this case, a method of varying the frequency of the system clock by the count value described above with reference to FIG. 9 can be considered, but in this case, even if the frequency of the system clock changes from the correct frequency by a maximum of 10%, the value can be changed. A count value of 10 is obtained. Therefore, in this case, the detection result includes an error of 10%, which makes it difficult to accurately detect the frequency error of the system clock with respect to the reproduction signal.

The present invention has been made in consideration of the above points, and proposes a clock generation circuit which can easily generate a clock frequency-synchronized with a reproduction signal and the like, and an optical disk device to which the clock generation circuit is applied. Is what you are trying to do.

[0016]

In order to solve such a problem, in the present invention, binarizing means for binarizing an input signal to generate a binarized signal, and the binarized signal as a reference, Reference signal generating means for generating a reference signal whose signal level rises or falls by the prescribed number of clock pulses of the clock, and first and second signal level detection results corresponding to the rising edge and the falling edge of the reference signal from the input signal. And a frequency error detection means for detecting an error in the frequency of the clock with respect to the fundamental frequency of the input signal based on the first and second signal level detection results, and the frequency error detection result. And a clock generating means for varying the frequency of the previous clock based on the above.

In particular, the signal level of the binarized signal is the period during which the signal level of the reference signal rises or falls when the basic frequency of the input signal and the frequency of the clock coincide with each other. It is set so that it coincides with the period with the highest appearance probability in the rising period and the falling period.

Alternatively, the above reference signal generating means generates a positive side reference signal and a negative side reference signal, and the signal level detecting means correspondingly generates the positive side reference signal. Corresponding positive side first and second signal level detection results,
The negative side first and second signal level detection results corresponding to the negative side reference signal are output, and the frequency error detection means outputs the positive side first and second signal level detection results and the negative side signal level detection result. A frequency error detection result is generated from the first and second signal level detection results.

Further, at this time, when the standard pulse number is equal to the basic frequency of the input signal and the frequency of the clock,
The period in which the signal level of the reference signal on the positive side rises or falls and the period in which the signal level of the reference signal on the negative side rises or falls include the period in which the signal level of the binarized signal rises and falls. It is set to match the period with the highest appearance probability.

Further, in the optical disk device, the binarizing means for binarizing the received light result to generate a binarized signal, and the signal level rises or rises by a prescribed number of clock pulses with reference to the binarized signal. Reference signal generating means for generating a falling reference signal, and a signal level of a light reception result at the rising and falling timings of the reference signal, and first and second signal levels corresponding to rising and falling of the reference signal. Based on the signal level detection means for outputting the detection result and the first and second signal level detection results, the frequency error for detecting the frequency error of the clock with respect to the fundamental frequency of the light reception result and outputting the frequency error detection result. A clock that generates the clock by varying the frequency of the previous clock based on the detection means and the frequency error detection result. So that and an adult means.

At this time, in particular, when the standard pulse number is the same as the basic frequency of the light reception result and the frequency of the clock, the period during which the signal level of the reference signal rises or falls is that of the binary signal. It is set so as to coincide with the period with the highest appearance probability in the period in which the signal level rises and the period in which it falls.

Alternatively, the reference signal generating means generates the positive side reference signal and the negative side reference signal, and the signal level detecting means correspondingly generates the positive side first and second signals. The level detection result and the negative side first and second signal level detection results are output, and the frequency error detecting means outputs the positive side first and second signal level detection results.
And the second signal level detection result, and the negative first and second signals
The frequency error detection result is generated based on the signal level detection result of the above.

Further, at this time, when the number of the above-mentioned regulation pulses is such that the signal level of the reference signal on the positive side rises or falls when the basic frequency of the light reception result and the frequency of the clock match, and the negative side The period during which the signal level of the reference signal rises or falls is set so as to coincide with the period with the highest appearance probability in the period during which the signal level of the binarized signal rises and falls.

Further, in these cases, the optical disk device is provided with a rough adjusting means for controlling the clock generating means so that the frequency of the clock roughly agrees with the fundamental frequency of the light receiving result.

[0025]

After the input signal is binarized, when the signal level of the binarized signal is switched, a reference signal whose signal level rises or falls by the specified number of pulses of the clock is generated. The reference signal corresponding to can be generated from the clock. Therefore, if the signal level of the input signal is detected at the rising and falling timings of this reference signal, in the specified cycle of the input signal,
It is possible to obtain the first and second signal level detection results corresponding to the rising side and the falling side of the input signal.
As a result, it is possible to detect the deviation of the clock cycle with respect to the specified cycle of the input signal based on the first and second signal level detection results, and detect the error of the clock frequency with respect to the basic frequency of the input signal. be able to.

Therefore, when the standard pulse number is equal to the basic frequency of the input signal and the frequency of the clock, the period during which the signal level of the reference signal rises or falls is the signal level of the binarized signal. If the period is set to coincide with the period with the highest appearance probability among the rising period and the falling period, the specified cycle of the input signal can be set to the cycle with the highest appearance probability.

Instead of this, a positive side reference signal and a negative side reference signal are generated, and correspondingly positive side first and second signal level detection results corresponding to the positive side reference signal. When,
If the negative first and second signal level detection results corresponding to the negative reference signal are obtained, the frequency of frequency error detection results can be further improved.

Also in this case, of course, when the standard number of pulses is equal to the basic frequency of the input signal and the frequency of the clock, the period during which the signal level of the reference signal rises or falls is binarized. The frequency of detection of the frequency error detection result can be further improved by setting the signal level so that it coincides with the period with the highest appearance probability during the period in which the signal level of the signal rises or falls.

Therefore, it is possible to apply these configurations to the optical disk device, process the light receiving result by the clock frequency-synchronized with the light receiving result, and reproduce the data recorded on the disk recording medium.

Further, in these cases, if the optical disk device is provided with a rough adjusting means for controlling the clock generating means so that the frequency of the clock roughly agrees with the basic frequency of the light receiving result, for example, access Thus, even if the fundamental frequency of the light reception result changes significantly, the clock can be quickly changed to follow the change of the fundamental frequency.

[0031]

Embodiments of the present invention will be described in detail below with reference to the drawings.

(1) First Embodiment FIG. 1 is a block diagram showing a CD-ROM drive according to an embodiment of the present invention. This CD-ROM drive 1
Is a CD-ROM created under the condition that the linear velocity is constant.
2 is reproduced under the condition that the angular velocity is constant.

That is, in the CD-ROM drive 1, the spindle motor 3 rotationally drives the CD-ROM 2 and outputs a rotation speed signal whose frequency changes following the rotation speed of the CD-ROM 2. Spindle servo circuit 4
Drives the spindle motor 3 based on the result of phase comparison between this rotation speed signal and the reference signal of the regulation so that the rotation speed of the CD-ROM 2 becomes the regulation rotation speed. This is the CD
In the -ROM drive 1, the CD-ROM 2 is rotationally driven under the condition that the angular velocity is constant.

The optical pickup 5 emits a laser beam from the built-in laser diode to the information recording surface of the CD-ROM 2 and receives the returned light through the prescribed optical system. Further, the optical pickup 5 performs current-voltage conversion on the reception result of the return light and then processes it by a built-in matrix circuit to change the signal level according to the tracking error amount and the tracking error signal and the focus error amount. A reproducing signal RF whose signal level changes in response to a changing focus error signal and a change in the amount of return light is generated. This allows CD-ROM drive 1
In the above, tracking control and focus control are performed based on the tracking error signal and the focus error signal.

The RF signal processing circuit 6 has an amplifier circuit having an automatic gain control circuit configuration, and the reproduced signal R is generated by this amplifier circuit.
Amplify F. As a result, the RF signal processing circuit 6 amplifies the reproduction signal RF with a predetermined gain and also reproduces the reproduction signal RF.
Correct the fluctuation of the signal level of. With this, CD-RO
In the M drive 1, the reproduction signal R is controlled by controlling the clock CK based on the signal level of the reproduction signal RF described later.
The deterioration of the control characteristics due to the fluctuation of the F signal level is effectively avoided.

Further, the RF signal processing circuit 6 controls the reproduction signal R
The asymmetry of F is corrected, and thus the signal level of the reproduction signal RF is corrected so that the signal level of the reproduction signal RF changes at equal time intervals on the positive side and the negative side with reference to the specified slice level SLV.

The binarization processing circuit 7 is formed of a comparison circuit, and as shown in FIGS. 2 and 3, a reproduction signal RF (FIGS. 2A and 3) output from the RF signal processing circuit 6.
By obtaining the comparison result between (A)) and the slice level SLV, the reproduction signal RF is binarized and the binarized signal SU (FIGS. 2B and 3B) is output. Note that FIG. 2 shows the clock CK with respect to the basic frequency of the reproduction signal RF.
3 shows the case where the frequencies of the clock CK and the frequency of the clock CK do not match the basic frequency of the reproduction signal RF.

The digital signal processing circuit 8 is a voltage controlled oscillator (VCO) 9.
Based on the system clock CK2 (FIG. 2 (C) and FIG. 3 (C)) output from the above, the binarized signal SU is converted into serial data, and then the serial data is decoded to perform error correction or the like. Execute the process. This makes the CD-R
The OM drive 1 reproduces the data recorded in the CD-ROM 2 and outputs the reproduced data in response to a request from an external device.

In this embodiment, the system clock CK2 is set to a frequency double that of the reproduction signal RF, and the voltage control type oscillation circuit 9 divides the system clock CK2 into 1/2 to generate the clock CK. (FIG. 2 (D) and FIG. 3 (D)) are generated. On the other hand, in the CD-ROM drive 1, this clock CK
Controls the voltage control type oscillation circuit 9 so that the signal is synchronized with the reproduction signal RF, and the system clock C is supplied to the reproduction signal RF.
Synchronize K2.

In outputting the data recorded on the CD-ROM 2 in this manner, the CD-ROM drive 1
For example, when the optical pickup 5 is sought in response to a command from an external device, the coarse adjustment circuit 10 roughly adjusts the frequency of the clock CK and then the reproduction signal RF.
The voltage control type oscillation circuit 9 is controlled by forming a servo loop based on the signal level of. This allows CD-ROM
The drive 1 synchronizes the phase of the system clock CK2 with the reproduction signal RF.

That is, when the optical pickup 5 seeks and the state of just tracking and the state of just focusing are almost formed, the rough adjusting circuit 10 starts the operation of the built-in counter and the rising edge of the binarized signal SU. And, the number of pulses of the clock CK is counted by this counter with reference to the falling edge.

As a result, the coarse adjustment circuit 10 causes the number of pulses of the clock CK to rise during the period when the signal level of the binarized signal SU rises and during the period when the signal level of the binarized signal SU falls. Are sequentially counted, and the maximum count result is detected. As a result, the coarse adjustment circuit 10 detects an error in the frequency of the clock CK with respect to the reproduction signal RF with reference to the pit and land having the longest period 11T with respect to the basic period T among the pits and lands of the CD-ROM 2. .

Further, the rough adjusting circuit 10 outputs a control voltage to the voltage control type oscillation circuit 9 based on the detected count value, so that the detected count value becomes a specified count value. It controls the frequency of CK (system clock CK2).

When the frequency of the clock CK is roughly adjusted in this way, in the CD-ROM drive 1, the clock CK is subsequently synchronized with the reproduction signal RF by the servo loop based on the signal level of the reproduction signal RF. Let In the coarse adjustment circuit 10, the clock C
By counting K to detect a frequency error, the error is large. Therefore, in the CD-ROM drive 1, when the seek distance is short, the coarse adjustment process is omitted and the signal level of the reproduction signal RF is used as a reference. The clock CK is synchronized with the reproduction signal RF by the servo loop.

Here, the 3T signal generating circuit 11 uses the rising edge of the binarized signal SU as a reference to generate the clock CK.
A 3T signal P3T corresponding to a reproduction signal RF having a cycle of 3T
(FIG. 2 (E) and FIG. 3 (E)) are generated.

That is, the 3T signal generation circuit 11 has a counter and starts the operation of this counter with reference to the rising edge of the binarized signal SU. When the counter rises to the operating state, it raises the signal level of the output signal in synchronization with the clock CK, then counts the clock CK for three cycles, and lowers the signal level of the output signal.

Thus, when the frequency of the clock CK matches the basic frequency of the reproduction signal RF, the 3T signal generation circuit 11 has a period equal to the period during which the reproduction signal RF having a period 3T rises across the slice level SLV. During this period, the 3T signal P3T whose signal level rises is generated, and thereby the reference signal corresponding to the reproduction signal RF having the cycle 3T is generated from the clock CK.

The sampling signal generating circuit 12 has three
The sampling signal S whose signal level rises at the rising edge and the falling edge of the T signal P3T, respectively.
Generate P.

The signal level detection circuit 13 samples the reproduction signal RF at the timing when the signal level of the sampling signal SP rises, and thereby the 3T signal P3T.
Sampling results P and Q subtraction corresponding to the rising edge and the falling edge of are detected. Further, the signal level detection circuit 13 subtracts the level difference from the SLV from the slice levels of the sampling results P and Q, outputs the subtraction result as a frequency error signal SΔf, and corresponds to the rising edge of the 3T signal P3T. A signal obtained by subtracting the slice level SLV from the sampling result P is output as the phase error signal SΔφ.

That is, when the 3T signal P3T corresponding to the reproduction signal RF of the cycle 3T is generated from the clock CK, when the frequency of the clock CK matches the basic frequency of the reproduction signal RF, the 3T signal P3T of the 3T signal P3T is generated. The period during which the signal level rises is equal to the period during which the signal level of the reproduction signal RF rises from 0 level in the reproduction signal RF of the cycle 3T.

Further, the 3T signal P3T rises at the rising timing of the clock CK after the signal level of the binarized signal SU rises, so that the rising edge and the falling edge of the 3T signal P3T become Phase error of clock CK 2
It will be delayed with respect to the binarized signal.

Therefore, assuming that the frequency of the clock CK matches the basic frequency of the reproduction signal RF, the sampling result P corresponding to the rising edge of the 3T signal P3T changes in signal level according to the phase error. Will be done.

In contrast, in FIG. 2, the symbols t1 and t
As shown by 2, in this case, in the reproduction signal RF of the cycle 3T, the period t1 from the 0 level of the reproduction signal RF to the rising edge of the 3T signal P3T and the reproduction signal RF of 0.
The period t2 from the level to the falling edge of the 3T signal P3T is held in the same period.

As a result, the sampling results P and Q obtained by sampling the reproduction signal RF having a period of 3T on the basis of the 3T signal P3T are obtained when the frequency of the clock CK matches the basic frequency of the reproduction signal RF. , Fig. 2
In (A), the level difference between the sampling results P and Q from the slice level SLV is detected with a value that is changed by equal signal levels on the positive and negative sides with the slice level SLV as the center, as indicated by symbols P1 and Q1. .

On the other hand, as shown in FIG. 3, when the frequency of the clock CK is deviated from the basic frequency of the reproduction signal RF, in the reproduction signal RF having a cycle of 3T, the 0T level of the reproduction signal RF is changed to the 3T signal. The period t1 from the 0 level of the reproduction signal RF to the falling edge of the 3T signal P3T with respect to the period t1 until the rising edge of P3T.
Will change by this frequency shift.

That is, the fundamental frequency of the reproduction signal RF is f
Let d be the frequency of clock CK and fs be

[Equation 1]

[Equation 2] The basic period td of the reproduction signal RF and the basic period ts of the clock CK can be expressed by the relational expression.

As a result, when the frequency of the clock CK is deviated from the reproduction signal RF, the following equation is given between the basic period td of the reproduction signal RF and the basic period ts of the clock CK.

[Equation 3] The time difference represented by the relational expression of is generated, and the time difference between the period t1 and the period t2 is 3 cycles of the basic cycle as the target cycle.
Since it is T,

[Equation 4] It can be expressed by the relational expression of.

As a result, when the frequency of the clock CK deviates from the basic frequency of the reproduction signal RF, the sampling timing of the reproduction signal RF changes relatively, and in the reproduction signal RF, the differential value is almost near the slice level SLV. By being held constant, the sampling results P1 and Q represented by the level difference from the slice level
It can be seen that 1 can be expressed by the following relational expression, where Δf is the error of this frequency. Note that k is a proportional constant.

[Equation 5]

Thus, in the CD-ROM drive 1,
The frequency error and the phase error are detected by utilizing these relationships, and the clock CK is synchronized with the reproduction signal RF.

By the way, in this way, when the 3T signal P3T is generated from the clock CK corresponding to the reproduction signal RF of the cycle 3T and the reproduction signal RF is sampled with reference to this 3T signal P3T, in FIG. 2 and FIG. As indicated by the symbols P2 and Q2, the reproduction signal RF may be sampled in cycles other than the cycle 3T, and in this case, it becomes difficult to detect a correct frequency error.

However, in this case, as shown in FIG.
The frequency error signal SΔf expressed by the equation (5) converges to near 0 level when the reproduction signal RF has a period of 3T, whereas the signal level rises when the reproduction signal RF has a period other than the period of 3T ( Or it will fall).

Further, this cycle 3T is the shortest cycle of the CD-ROM 2 and has the highest occurrence probability,
Based on the signal level, it is possible to easily select only the frequency error signal SΔf having a period of 3T.
It is possible to detect the frequency error with a frequency sufficient for practical use by selecting only the frequency error signal SΔf. Therefore, if the frequency error can be detected with sufficient frequency, the CD-
In the ROM drive 1, the clock CK can be controlled with high speed and high accuracy.

As a result, as shown in FIG. 5, the frequency error signal generation circuit 14 determines 0 from the frequency error signal SΔf.
The sampling result near the level is selectively sampled and held, whereby the frequency error signal SΔf is detected and the correct frequency error signal Sfe is generated.

On the other hand, in the phase error signal SΔφ, it is assumed that the frequency of the clock CK matches the fundamental frequency of the reproduction signal RF, and the phase error is detected in any of the sampling results P1 and P2. This means that the sampling is performed correctly and the sampling interval is the reproduction signal R.
It will change according to the cycle of F.

As a result, the phase error signal generation circuit 15
The phase error signal S output from the signal level detection circuit 13
Δφ is sequentially sampled and held to generate the phase error signal Sφ.

The control signal generation circuit 16 includes a coarse adjustment circuit 10
When a correct count value is obtained in (i.e., when the frequency of the clock CK is roughly adjusted with respect to the basic frequency of the reproduction signal RF), the operating state is started, and the frequency error signal Sfe becomes 0 level at first. Then, the voltage control type oscillation circuit 9 is controlled. With this, CD-RO
In the M drive 1, a servo loop based on the signal level of the reproduction signal RF is formed as a whole, and the reproduction signal RF is generated.
The frequency of the system clock CK2 is variably controlled so that the frequency of the clock CK matches the fundamental frequency of the.

Therefore, at the system clock CK2, even if the frequency of the reproduction signal RF obtained from the CD-ROM 2 is drastically changed by driving the CD-ROM 2 under the condition that the angular velocity is constant, the basic frequency of the reproduction signal RF is changed. The frequency is variably controlled so that the two coincide with each other with high accuracy.

Further, when the frequency error signal Sfe converges to almost 0 level, the control signal generation circuit 16 controls the voltage control type oscillation circuit 9 so that the signal level of the phase error signal Sφ subsequently becomes the prescribed signal level. To do. This gives C
Similarly, in the D-ROM drive 1, the reproduction signal R
The timing of the clock CK is controlled by the servo loop based on the signal level of F so as to be phase-synchronized with the reproduction signal RF.

As a result, in the CD-ROM drive 1,
Even when the frequency of the reproduction signal RF changes significantly, the system clock CK2 phase-locked with the reproduction signal RF
CD-RO can be generated under the condition that the angular velocity is constant.
Even when reproducing M2, the data recorded in the CD-ROM 2 can be reproduced correctly. Therefore, the access time can be shortened as compared with the conventional case where the CD-ROM is driven under the constant linear velocity condition.

In the above configuration, the CD-ROM 2 is
The spindle motor 3 rotationally drives under a condition of a constant angular velocity, the return light of the laser beam is received by the optical pickup 5 in this state, and a reproduction signal RF whose signal level changes according to the change in the amount of the return light is generated. To be done.

This reproduction signal RF is supplied to the RF signal processing circuit 6
, The asymmetry is corrected after the fluctuation of the signal level is corrected, and in the subsequent binarization processing circuit 7, it is binarized by the slice level SLV and binarized signal SU.
Is converted to.

The binarized signal SU is input to the coarse adjustment circuit 10, where the longest period 1 of the binarized signal SU is 1.
1T is detected by the number of pulses of the clock CK. As a result, in the CD-ROM drive 1, an error in the frequency of the clock CK with respect to the reproduction signal RF is roughly detected,
The voltage control type oscillation circuit 9 is controlled by this detection result,
The frequency of the system clock CK2 is roughly adjusted.

Further, the binarized signal SU is input to the 3T signal generation circuit 11, where the clock CK is counted with reference to the rising edge of the binarized signal SU to correspond to the reproduction signal RF having a period of 3T. As described above, the 3T signal P3T is generated from the clock CK.

The 3T signal P3T is input to the sampling signal generation circuit 12, a sampling signal SP whose signal level rises at the edge of the 3T signal P3T is generated, and the sampling signal SP is reproduced by the sampling signal SP in the signal level detection circuit 13. RF is sampled.

As a result, when the frequency of the clock CK is roughly adjusted in the CD-ROM drive 1, the signal level of the reproduction signal RF is detected at the timing of the clock CK corresponding to the cycle 3T of the reproduction signal RF. From the difference signal of the level differences P1 and Q1 from the slice level SLV of the results P and Q, the frequency error signal SΔf is
Further, the detection result P corresponding to the rising edge of the 3T signal P3T
The slice level SLV is subtracted from the phase error signal S
Δφ is generated.

Of the frequency error signal SΔf and the phase error signal SΔφ, the frequency error signal SΔf is detected by the frequency error signal generation circuit 14 by selectively sample-holding the detection result in the vicinity of 0 level and detecting the period 3T.
The frequency error signal SΔf based on the reproduction signal RF is selected and converted into the correct frequency error signal Sfe. Further, the phase error signal SΔφ is sampled and held in the phase error signal generation circuit 15 so that the phase error signal Sφ
Is converted to.

As a result, in the CD-ROM drive 1,
When the frequency of the clock CK is roughly adjusted, subsequently, the signal level of the reproduction signal RF is detected at the timing of the clock CK with reference to the reproduction signal RF having a period of 3T, and a frequency error signal with higher accuracy than this detection result. Sfe
And the phase error signal Sφ are generated, the frequency of the clock CK is finely controlled by the frequency error signal Sfe, and then the clock CK is generated by the phase error signal Sφ.
The phase of is adjusted.

As a result, in the CD-ROM drive 1,
With a simple configuration, a system clock CK2 that is phase-synchronized with the reproduction signal RF with high accuracy is generated, and the binarized signal SU is digitally processed in the digital signal processing circuit 8 with reference to the system clock CK2. The data recorded on the CD-ROM is reproduced.

In this way, when the clock CK is controlled with the signal level of the reproduction signal RF as a reference, the cycle of the reference reproduction signal RF is selected to be the cycle 3T which has the highest occurrence frequency and the shortest cycle. As a result, the clock CK can be controlled at high speed and with high accuracy.

Further, after the fluctuation of the signal level of the reproduction signal RF is corrected by the RF signal processing circuit 6, the signal level is detected by the signal level detection circuit 13, so that the control by the fluctuation of the signal level of the reproduction signal RF is performed. It is possible to effectively avoid deterioration of characteristics.

After the asymmetry of the reproduction signal RF is corrected by the RF signal processing circuit 6, the signal level is detected by the signal level detection circuit 13,
The clock CK can be controlled by correctly detecting the frequency error and the phase error.

According to the above configuration, a 3T signal corresponding to the reproduction signal RF having a period of 3T is generated from the clock CK with reference to the timing when the reproduction signal RF crosses the slice level, and the edge of this 3T signal is used as a reference. Playback signal R
By detecting the signal level of F and generating the frequency error signal from the signal level detection result, even if the frequency of the reproduction signal RF changes, the clock CK of the clock CK is tracked even if the frequency of the reproduction signal RF changes. System clock C whose frequency is switched and frequency-synchronized with the reproduction signal RF
K2 can be generated. Moreover, since the configuration can be simplified, the overall power consumption can also be reduced.

(2) Second Embodiment In the first embodiment described above, the binarized signal S is used.
Since the 3T signal P3T corresponding to the reproduction signal RF having the period 3T is generated from the clock CK with the rising edge of U as the reference, the system clock CK2 is controlled by using only the positive side of the reproduction signal RF. Become.

Therefore, it is considered that the control characteristic of the system clock CK2 can be further improved by controlling the system clock CK2 by also utilizing the negative side of the reproduction signal RF which is not used at all. That is, it is considered that the operating speed can be increased and the accuracy can be improved.

Therefore, in this embodiment, as shown in FIG. 6, in addition to the configuration of the first embodiment, a reproduction signal RF
Of the frequency error signal SΔfI and the phase error signal SΔφI corresponding to the negative side of the
Speed control and precision control. Note that among the configurations shown in FIG. 6, configurations common to those of the first embodiment described above with reference to FIG. 1 are denoted by the same reference numerals, and redundant description will be omitted.

That is, as shown in FIG. 7 and FIG.
The ROM drive 20 has a 3T signal generation circuit 21 in addition to the 3T signal generation circuit 11, and this 3T signal generation circuit 21 is generated from a reproduction signal RF (FIGS. 7A and 8A). Binary signal SU (FIG. 7 (B) and FIG. 8)
With reference to the falling edge of (B)), clock C
K (FIGS. 7C and 7D, 8C and 8D) is counted for three cycles.

As a result, in the CD-ROM drive 20, the 3T signal generation circuit 11 responds to the reproduction signal RF having the period 3T in which the signal level changes to the positive side.
The 3T signal P3T is generated from the clock CK, and the 3T signal generation circuit 21 generates the 3T signal P3TI from the clock CK so as to correspond to the reproduction signal RF having the period 3T in which the signal level changes to the negative side (see FIG. 7 ( E) and FIG.
(E)).

Corresponding to the sampling signal generating circuit 12, the sampling signal generating circuit 22 rises in signal level from the 3T signal P3TI output from the 3T signal generating circuit 21 at the rising edge and the falling edge of the 3T signal P3TI. A sampling signal SPI is generated.

The signal level detection circuit 23 corresponds to the signal level detection circuit 13 and the sampling signal generation circuit 22.
Based on the sampling signal SPI output from
The reproduction signal RF is sampled. Further, the signal level detection circuit 23 determines the slice level SLV from the sampling result P corresponding to the rising edge of the 3T signal P3TI.
Is subtracted, and the subtraction result is output as the negative-side phase error signal SΔφI. Further, the signal level detection circuit 23 generates a subtraction signal of the level differences P1 and Q1 from the slice level SLV between the sampling results P and Q corresponding to the rising edge and the falling edge of the 3T signal P3TI, and the subtraction signal is negative. It is output as the side frequency error signal SΔfI.

As a result, the frequency error signal generation circuit 14,
In the phase error signal generation circuit 15, the frequency error signals SΔf and SΔf are twice as frequently as those in the first embodiment.
I and the phase error signals SΔφ and SΔφI will be input. Therefore, in the CD-ROM drive 20,
It is possible to control the system clock CK2 while improving the operation speed and control accuracy as compared with the first embodiment.

According to the configuration shown in FIG. 6, the 3T signals P3T and P3TI are generated from the clock CK so as to correspond to the reproduction signal RF having the period 3T in which the signal level changes to the positive side and the negative side, respectively. Signals P3T and P3TI
By detecting the signal level of the reproduction signal RF with reference to, and generating the frequency error signal and the phase error signal, in addition to the effect of the first embodiment, the operating speed and the control accuracy can be further improved. .

(3) Other Embodiments In the above-described embodiments, the case where the phase error is corrected after the frequency error is corrected by switching the frequency error signal and the phase error signal has been described. The invention is not limited to this, and the voltage controlled oscillation circuit may be controlled by weighted addition of the frequency error signal and the phase error signal.

In the above embodiment, the case where the frequency error signal is generated by performing the subtraction processing between the first and second sampling results P and Q has been described, but the present invention is not limited to this. After subtracting the slice level SLV from each of P and Q, division processing may be performed to generate the frequency error signal.

Further, in the above-mentioned embodiments, the case where the frequency error is roughly detected and the coarse adjustment is performed by counting the clocks with the binarized signal as a reference has been described, but the present invention is not limited to this. , For example, when roughly changing the clock frequency based on the position information of the optical pickup and further on the seek target,
Various coarse adjustment means can be widely applied.

Further, in the above-described embodiments, the case where the clock is simply controlled by the signal level detection result detected by the signal level detection circuit 13 has been described, but the present invention is not limited to this, and the signal level detection result is used. It is also possible to monitor the cycle of the binarized signal SU and detect the defect together with the control of the clock.

Further, in the above-mentioned embodiment, the case where the present invention is applied to the CD-ROM drive for driving the CD-ROM under the condition of constant angular velocity is described, but the present invention is not limited to this, and the linear velocity is constant. CD-ROM depending on conditions
The present invention can be widely applied to a CD-ROM drive for driving a disk, a write-once type optical disk device, a magneto-optical disk device, and various signal processing devices that generate a clock from an input signal and process the input signal.

[0097]

As described above, according to the present invention, the reference signal corresponding to the predetermined cycle of the input signal is generated by the clock, and the signal level of the input signal is detected based on the reference signal to input the signal. By detecting the error in the frequency of the clock with respect to the fundamental frequency of the signal, the error in the frequency of the clock with respect to the input signal can be detected easily and with high accuracy even when the frequency of the input signal changes. As a result, the frequency of the clock can be varied based on the error detection result, and the frequency of the clock can be matched with the fundamental frequency of the input signal.

[Brief description of drawings]

FIG. 1 is a block diagram showing a CD-ROM drive according to an embodiment of the present invention.

FIG. 2 is a signal waveform diagram showing a state in which the clock frequency of the CD-ROM drive shown in FIG. 1 is substantially equal to the basic frequency of a reproduction signal.

3 is a signal waveform diagram showing a state where a clock frequency is deviated from a fundamental frequency of a reproduction signal in the CD-ROM drive shown in FIG.

FIG. 4 is a signal waveform diagram showing the detection result of the frequency error of FIG.

5 is a signal waveform diagram showing a processing result of the frequency error detection result of FIG.

FIG. 6 is a block diagram showing a CD-ROM drive according to a second embodiment.

FIG. 7 is a signal waveform diagram showing a state where the clock frequency substantially matches the fundamental frequency of a reproduction signal in the CD-ROM drive shown in FIG.

8 is a signal waveform diagram showing a state where a clock frequency is deviated from a fundamental frequency of a reproduction signal in the CD-ROM drive shown in FIG.

FIG. 9 is a signal waveform diagram for explaining a conventional method of detecting a frequency error.

[Explanation of symbols]

1,20 CD-ROM drive 2 CD-ROM 6 RF signal processing circuit 7 Binarization processing circuit 8 Digital signal processing circuit 9 Voltage controlled oscillator 10 Coarse adjustment circuit 11, 21 3T signal generation circuit 12, 22 Sampling signal generation circuit 13, 23 Signal level detection circuit 14 Frequency error signal generation circuit 15 Phase error signal generation circuit 16 Control signal generation circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H03L ^7/ 00-7/14 G11B 20/10-20/16

Claims (10)

(57) [Claims] 1. A clock generation circuit for generating a clock synchronized with an input signal, said binarizing means for binarizing said input signal with reference to a prescribed slice level to generate a binarized signal; When the signal level of the binarized signal is switched, a reference signal generating means for generating a reference signal whose signal level rises or falls by a prescribed number of pulses of the clock, and at the timing of the rising edge and the falling edge of the reference signal, Detecting the signal level of the input signal,
Signal level detecting means for outputting first and second signal level detection results corresponding to rising and falling edges of the reference signal; and the input signal based on the first and second signal level detection results. A frequency error detecting means for detecting an error in the frequency of the clock with respect to the fundamental frequency and outputting a frequency error detection result; and a clock for generating the clock by varying the frequency of the clock based on the frequency error detection result. A clock generation circuit comprising: a generation unit. 2. The regulation pulse number is the signal level of the binarized signal when the signal level of the reference signal rises or falls when the frequency of the clock matches the fundamental frequency of the input signal. 2. The clock generation circuit according to claim 1, wherein the clock generation circuit is set so as to coincide with a period having the highest appearance probability in a rising period and a falling period. 3. The reference signal generating means, when the signal level of the binarized signal rises, the positive side reference signal whose signal level rises or falls by a prescribed number of pulses of the clock, and the binarized signal. When the signal level of rises, the negative level reference signal whose signal level rises or falls by the specified number of pulses of the clock is generated, and the signal level detection means is a positive reference signal corresponding to the positive side reference signal. Side first and second
Signal level detection result of the negative side first and second negative side signals corresponding to the negative side reference signal
And the frequency error detection means based on the positive side first and second signal level detection results and the negative side first and second signal level detection results. The clock generation circuit according to claim 1, wherein the clock generation circuit generates the frequency error detection result. 4. The regulation pulse number is defined as a period during which the signal level of the reference signal on the positive side rises or falls, and a period on the negative side when the frequency of the clock matches the fundamental frequency of the input signal. The period during which the signal level of the reference signal rises or falls,
4. The clock generation circuit according to claim 3, wherein the clock generation circuit is set so as to coincide with a period having the highest appearance probability in a rising period and a falling period of the signal level of the binarized signal. 5. A disc-shaped recording medium is recorded by receiving return light obtained by irradiating a disc-shaped recording medium with a light beam and processing the reception result of the return light with reference to a prescribed clock. In the optical disc device for reproducing the recorded data, the binarizing means for binarizing the received light result based on the specified slice level to generate a binarized signal and the signal level of the binarized signal are switched. And a reference signal generating means for generating a reference signal whose signal level rises or falls by the specified number of pulses of the clock, and a signal level of the light reception result with reference to the timing of the rising edge and the falling edge of the reference signal. Is detected and the first and second signal level detection results corresponding to the rising edge and the falling edge of the reference signal are output. Signal level detection means, and frequency error detection means for detecting an error in the frequency of the clock with respect to the fundamental frequency of the light reception result based on the first and second signal level detection results and outputting the frequency error detection result. An optical disk device comprising: a clock generating unit that generates the clock by varying the frequency of the clock based on the frequency error detection result. 6. The threshold pulse number is a signal of the binarized signal when the signal level of the reference signal rises or falls when the frequency of the clock matches the fundamental frequency of the light reception result. The optical disk device according to claim 5, wherein the level is set so as to coincide with a period having the highest appearance probability in a period in which the level rises and a period in which the level falls. 7. The reference signal generating means, when the signal level of the binarized signal rises, the positive side reference signal whose signal level rises or falls by a prescribed number of pulses of the clock, and the binarized signal. When the signal level of rises, a negative side reference signal whose signal level rises or falls by a prescribed number of pulses of the clock is generated in synchronization with the clock, and the signal level detection means is a positive side reference signal. Positive side first and second sides corresponding to signals
Signal level detection result of the negative side first and second negative side signals corresponding to the negative side reference signal
And the frequency error detection means based on the positive side first and second signal level detection results and the negative side first and second signal level detection results. 6. The optical disk device according to claim 5, wherein the frequency error detection result is generated. 8. The regulation pulse number is defined as a period during which the signal level of the reference signal on the positive side rises or falls and a period on the negative side when the frequency of the clock matches the fundamental frequency of the light reception result. The period during which the signal level of the reference signal rises or falls,
8. The optical disk device according to claim 7, wherein the binarized signal is set so as to coincide with a period having the highest appearance probability in a rising period and a falling period of the signal level of the binarized signal. 9. The optical disk device comprises coarse adjustment means for controlling the clock generation means so that the frequency of the clock roughly matches the fundamental frequency of the light reception result. Item 6. The optical disk device according to item 6. 10. The optical disk device comprises coarse adjustment means for controlling the clock generation means so that the frequency of the clock roughly agrees with the fundamental frequency of the light reception result. Item 8. The optical disk device according to item 8.