CN112383418A - Design method for high-speed reliable transmission of Ethernet messages based on FPGA - Google Patents
Design method for high-speed reliable transmission of Ethernet messages based on FPGA Download PDFInfo
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- CN112383418A CN112383418A CN202011203869.8A CN202011203869A CN112383418A CN 112383418 A CN112383418 A CN 112383418A CN 202011203869 A CN202011203869 A CN 202011203869A CN 112383418 A CN112383418 A CN 112383418A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L41/00—Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks
- H04L41/08—Configuration management of networks or network elements
- H04L41/0803—Configuration setting
- H04L41/0823—Configuration setting characterised by the purposes of a change of settings, e.g. optimising configuration for enhancing reliability
- H04L41/0836—Configuration setting characterised by the purposes of a change of settings, e.g. optimising configuration for enhancing reliability to enhance reliability, e.g. reduce downtime
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
- G06F15/781—On-chip cache; Off-chip memory
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L47/00—Traffic control in data switching networks
- H04L47/50—Queue scheduling
- H04L47/62—Queue scheduling characterised by scheduling criteria
- H04L47/622—Queue service order
- H04L47/6225—Fixed service order, e.g. Round Robin
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/50—Reducing energy consumption in communication networks in wire-line communication networks, e.g. low power modes or reduced link rate
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Abstract
The invention relates to a design method for high-speed reliable transmission of Ethernet messages based on an FPGA (field programmable gate array), which comprises the following steps of: the method comprises the following steps of judging the number of a received message through the FPGA, and operating according to the result, including: s1, inquiring whether the terminal number of the first fragment message can be retrieved in the number index of the FPGA, if so, returning an error message, discarding the message, and if not, executing S2; s2, inquiring whether the message corresponding to the message number has a corresponding cache in the FPGA, if so, directly reading the cache content and sending the cache content to the terminal, and if not, executing S3; and S3, processing the received message, writing the message into a circular buffer area after the processing is finished, simultaneously writing a message buffer index, and simultaneously sending the processed message to a terminal needing to arrive. The invention realizes high-speed reliable transmission of the network.
Description
Technical Field
The invention relates to a network communication technology, in particular to a design method for high-speed reliable transmission of Ethernet messages based on an FPGA.
Background
In network communication, in order to ensure the security of network data transmission, it is generally necessary to process the network data to be transmitted. Due to the limitations and requirements of the performance of the data processing module, the network data packets input to the data processing module must be reliably transmitted. Due to the objective conditions of the unsound Ethernet transmission safety mechanism, the limited buffer resources in logic and the like, in the data transmission occasions with larger throughput and larger bandwidth, some messages are inevitably lost in the transmission process, which causes the disorder of data processing, and the processes of message retransmission, repeated message processing and the like are required to be carried out, thus causing the low message processing rate.
Disclosure of Invention
The invention aims to provide a design method for high-speed reliable transmission of Ethernet messages based on an FPGA (field programmable gate array), which is used for solving the problem of low message processing speed.
The invention relates to a design method for high-speed reliable transmission of Ethernet messages based on an FPGA (field programmable gate array), which comprises the following steps of: the method comprises the following steps of judging the number of a received message through the FPGA, and operating according to the result, including: s1, inquiring whether the terminal number of the first fragment message can be retrieved in the number index of the FPGA, if so, returning an error message, discarding the message, and if not, executing S2; s2, inquiring whether the message corresponding to the message number has a corresponding cache in the FPGA, if so, directly reading the cache content and sending the cache content to the terminal, and if not, executing S3; and S3, processing the received message, writing the message into a circular buffer area after the processing is finished, simultaneously writing a message buffer index, and simultaneously sending the processed message to a terminal needing to arrive.
According to an embodiment of the design method for the high-speed reliable transmission of the Ethernet message based on the FPGA, the method for numbering the message at the sending end comprises the following steps: numbering the terminals according to the triplets or quintuples of the sent messages; numbering the messages according to different messages of the sent multilinks; and numbering the fragmented messages according to the same message of the sending single link.
According to an embodiment of the design method for high-speed reliable transmission of ethernet messages based on the FPGA of the present invention, the receiving end message processing includes: carrying out repeated line inspection on the terminal number of the first fragment message of the received message; searching the processed message according to the number of the received message; the receiving end processes the message and caches the message.
According to an embodiment of the design method for high-speed reliable transmission of the Ethernet message based on the FPGA, a terminal sending end carries out terminal numbering according to a triplet or a quintuple of a sending message, carries out message numbering according to a multi-link concurrent message, and carries out fragment numbering on a single-link message.
According to an embodiment of the design method for high-speed reliable transmission of ethernet messages based on the FPGA of the present invention, if the terminal number of the message can be retrieved, S1 further reports the number repetition error type.
The technical scheme provided by the invention reduces the processing time of repeated messages by constructing three mechanisms of 'sending terminal message number', 'receiving terminal number repeatability check' and 'receiving terminal message number retrieval', and saving a plurality of processed message fields, thereby realizing high-speed reliable transmission of the network, and a designer can flexibly configure the mechanism by combining with actual conditions.
Drawings
FIG. 1 is a diagram illustrating a message numbering format;
FIG. 2 is a diagram illustrating the process of numbering received messages;
FIG. 3 is a schematic diagram of a message after FPGA cache processing;
Detailed Description
In order to make the objects, contents, and advantages of the present invention clearer, the following detailed description of the embodiments of the present invention will be made in conjunction with the accompanying drawings and examples.
Fig. 1 is a schematic diagram showing a message numbering of a sending terminal, and the message numbering method includes:
a1, terminal number: mapping from the triplet or quintuple to the terminal number, wherein the mapping method is customized by a user, and the mapped sequence number needs to meet the condition: the sequence numbers mapped by the other terminals and the sequence number mapped by the current terminal must be different.
A2, message numbering: according to different messages, different message numbers are set, and the conditions are met: the number of the message being transmitted cannot be repeated.
A3, fragment message numbering: the first fragment message starts from 0 or 1, and other fragment messages are sequentially numbered in an accumulated manner.
Fig. 2 is a schematic diagram of a message processing number of a receiving end, and the message number processing method includes:
b1, the terminal number of the first slicing message is checked repeatedly to ensure that the terminal number of the message being received can not be repeated, the message number and the slicing message number can be repeated, and B2 is executed.
B2, the buffer index of the message number, enquire whether the current received message has the buffer message which has been processed, if yes, the current message can be sent to the terminal directly without secondary processing; if not, B3 is executed.
B3, message processing: and processing the message according to the user, outputting the processed message to the sending terminal, updating the processed message to a local cache buffer, and writing the message cache index.
FIG. 3 shows a message buffer
C1, the processed message needs to be cached in a circular buffer, and the message number is synchronously cached in an index buffer, it should be noted that the content of the index buffer is an address pointer of the message buffer.
C2, message retrieval: searching an index buffer according to the number of the received message, and inquiring whether the received message is processed or not; if the processing is already carried out, directly reading the buffer, and outputting the processed message; if the message number is not searched, the message is sent to a message processing module for processing.
The invention relates to a design method for high-speed reliable transmission of Ethernet messages based on an FPGA (field programmable gate array), which comprises the following steps of: the method for numbering the messages at the sending end comprises the steps that the terminal sending end carries out terminal numbering according to a triplet or a quintuple of the sent messages, carries out message numbering according to a multi-link concurrent message and carries out fragment numbering on a single-link message; the FPGA judges the received message and executes the following judging steps: inquiring whether the terminal number of the first fragmentation message can be retrieved in the number index of the FPGA, if so, returning an error message, reporting a repeated error type of the number, indicating that the current number is applied, discarding the message, and if not, executing S2; s2, inquiring whether the message corresponding to the serial number has a corresponding cache in the FPGA, if so, directly reading the cache content and sending the cache content to the terminal, and if not, executing S3; and S3, receiving and processing the message, writing the message into a circular buffer cache area after the processing is finished, simultaneously writing a message cache index, and simultaneously sending the processed message to a terminal needing to arrive. The terminal sending end number comprises: a terminal sending end carries out terminal numbering according to the triplet or quintuple of the sent message, and ensures that the numbering of each terminal cannot be repeated so as to distinguish different terminals; a terminal sending end carries out message numbering according to different messages of multiple links to distinguish the messages of different links; and the terminal sending end carries out fragment message numbering according to the same message of the sending single link so as to distinguish different fragment messages of the same link message.
Compared with the prior art, the technical scheme provided by the invention has the advantages that three mechanisms of 'sending terminal message number', 'receiving terminal number repeatability check' and 'receiving terminal message number retrieval' are established, the processing time of repeated messages is reduced by storing a plurality of processed message sites, the high-speed reliable transmission of a network is realized, and a designer can flexibly configure by combining with actual conditions by adopting the mechanism, so the method has certain engineering practical value.
The above description is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, several modifications and variations can be made without departing from the technical principle of the present invention, and these modifications and variations should also be regarded as the protection scope of the present invention.
Claims (5)
1. A design method for high-speed reliable transmission of Ethernet messages based on FPGA is characterized by comprising the following steps:
the method comprises the following steps of judging the number of a received message through the FPGA, and operating according to the result, including:
s1, inquiring whether the terminal number of the first fragment message can be retrieved in the number index of the FPGA, if so, returning an error message, discarding the message, and if not, executing S2;
s2, inquiring whether the message corresponding to the message number has a corresponding cache in the FPGA, if so, directly reading the cache content and sending the cache content to the terminal, and if not, executing S3;
and S3, processing the received message, writing the message into a circular buffer area after the processing is finished, simultaneously writing a message buffer index, and simultaneously sending the processed message to a terminal needing to arrive.
2. The design method for high-speed reliable transmission of ethernet messages based on FPGA according to claim 1, wherein the method for numbering the messages at the transmitting end comprises:
numbering the terminals according to the triplets or quintuples of the sent messages;
numbering the messages according to different messages of the sent multilinks;
and numbering the fragmented messages according to the same message of the sending single link.
3. The design method for high-speed reliable transmission of ethernet messages based on FPGA according to claim 1, wherein the receiving-end message processing comprises:
carrying out repeated line inspection on the terminal number of the first fragment message of the received message;
searching the processed message according to the number of the received message;
the receiving end processes the message and caches the message.
4. The design method for high-speed reliable transmission of ethernet messages based on FPGA according to claim 1, wherein a terminal sending end performs terminal numbering according to a triplet or quintet of a sending message, performs message numbering according to a multilink concurrent message, and performs fragment numbering on a single-link message.
5. The design method for high-speed reliable transmission of ethernet messages based on FPGA of claim 1, wherein S1 further reports a number repetition error type if the terminal number of the message can be retrieved.
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Cited By (3)
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| CN113765721A (en) * | 2021-09-14 | 2021-12-07 | 北京左江科技股份有限公司 | Ethernet remote configuration device based on FPGA |
| CN114615343A (en) * | 2022-03-24 | 2022-06-10 | 北京左江科技股份有限公司 | Method for realizing reliable transmission of Ethernet message based on FPGA |
| CN116527406A (en) * | 2023-07-03 | 2023-08-01 | 北京左江科技股份有限公司 | Multi-host security system and communication method based on FPGA |
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Cited By (5)
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| CN116527406A (en) * | 2023-07-03 | 2023-08-01 | 北京左江科技股份有限公司 | Multi-host security system and communication method based on FPGA |
| CN116527406B (en) * | 2023-07-03 | 2023-09-12 | 北京左江科技股份有限公司 | Multi-host security system and communication method based on FPGA |
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