CN112382682A - Photoelectric detection substrate, preparation method thereof and display device - Google Patents
Photoelectric detection substrate, preparation method thereof and display device Download PDFInfo
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- H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
- H01L31/0352—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
- H01L31/035272—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions characterised by at least one potential jump barrier or surface barrier
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- H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
- H01L31/0256—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by the material
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- H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
- H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by potential barriers, e.g. phototransistors
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Abstract
The patent refers to the field of 'semiconductor devices and electric solid state devices'. The photodetection substrate includes: the photoelectric conversion layer comprises a first semiconductor layer, a second semiconductor layer and an intrinsic layer arranged between the first semiconductor layer and the second semiconductor layer, the second semiconductor layer is positioned on one side, far away from the substrate base plate, of the first semiconductor layer, and the band gap of one side, close to the second semiconductor layer, of the intrinsic layer is larger than that of one side, close to the first semiconductor layer, of the intrinsic layer. The band gap of one side, close to the second semiconductor layer, of the intrinsic layer is larger than the band gap of one side, close to the first semiconductor layer, of the intrinsic layer, the wide band gap of one side, close to the second semiconductor layer, of the intrinsic layer can reduce absorption of fingerprint reflection light, the narrow band gap of one side, close to the first semiconductor layer, of the intrinsic layer can increase absorption of the fingerprint reflection light, and detection sensitivity of the photoelectric detection substrate is improved.
Description
Technical Field
The application relates to the technical field of display, in particular to a photoelectric detection substrate, a preparation method of the photoelectric detection substrate and a display device.
Background
The amorphous silicon PIN photodiode has the advantages of simple process, low cost, convenience for large-area deposition and the like. The amorphous silicon PIN back plate can be widely applied to the field of photoelectric detection, such as fingerprint identification or spectrum identification, due to the high signal-to-noise ratio.
In fingerprint identification applications, fingerprint identification is performed by the difference of photocurrent at different positions of a fingerprint. At present, the photoelectric current of a photodiode adopting an amorphous silicon PIN technology is small, so that the signal-to-noise ratio of the photodiode is low, and the sensitivity of fingerprint identification is influenced.
Disclosure of Invention
The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.
The embodiment of the invention provides a photoelectric detection substrate, a preparation method thereof and a display device, which can improve the sensitivity of fingerprint identification.
The photoelectric detection substrate provided by the embodiment of the invention comprises: the photoelectric conversion layer comprises a first semiconductor layer, a second semiconductor layer and an intrinsic layer arranged between the first semiconductor layer and the second semiconductor layer, the second semiconductor layer is positioned on one side, far away from the substrate base plate, of the first semiconductor layer, and the band gap of one side, close to the second semiconductor layer, of the intrinsic layer is larger than that of one side, close to the first semiconductor layer, of the intrinsic layer.
In some exemplary embodiments, the band gap of the intrinsic layer is arranged in a gradient in a direction away from the first semiconductor layer.
In some exemplary embodiments, the intrinsic layer includes a plurality of sub-intrinsic layers whose band gaps sequentially increase in a direction away from the first semiconductor layer.
In some exemplary embodiments, the band gap difference of adjacent sub intrinsic layers is between 0.15ev and 0.3 ev.
In some exemplary embodiments, the plurality of sub intrinsic layers includes a first sub intrinsic layer, a second sub intrinsic layer, and a third sub intrinsic layer stacked, the first sub intrinsic layer is adjacent to the first semiconductor layer, the third sub intrinsic layer is adjacent to the second semiconductor layer, a band gap of the first sub intrinsic layer is between 1.5ev and 1.7ev, a band gap of the second sub intrinsic layer is between 1.75ev and 1.9ev, and a band gap of the third sub intrinsic layer is between 1.95ev and 2.1 ev.
In some exemplary embodiments, a band gap ratio of the first semiconductor layer to the first sub intrinsic layer is between 0.9 and 1.2, and a band gap ratio of the second semiconductor layer to the third sub intrinsic layer is between 0.9 and 1.2.
In some exemplary embodiments, the bandgap of the intrinsic layer is between 1.4ev and 2.4 ev.
In some exemplary embodiments, the first semiconductor layer is an n-type semiconductor layer, and the second semiconductor layer is a p-type semiconductor layer.
In some exemplary embodiments, the photodiode further includes a first electrode disposed on a side of the first semiconductor layer facing the substrate base plate, and a second electrode disposed on a side of the second semiconductor layer away from the substrate base plate, the substrate base plate includes a base plate and a thin film transistor disposed on the base plate, the thin film transistor includes a gate electrode, an active layer, a first pole and a second pole, and the first electrode and the second pole are connected.
In some exemplary embodiments, the substrate includes a first insulating layer disposed on the gate electrode and a second insulating layer covering the first and second electrodes, the photodetection substrate further includes a third insulating layer and a fourth insulating layer disposed on a side of the second insulating layer away from the substrate and wrapping the photodiode, a planarization layer disposed on a side of the fourth insulating layer away from the substrate, a fifth insulating layer disposed on a side of the planarization layer away from the substrate, and a lead-out wire disposed on a side of the fifth insulating layer away from the substrate, the planarization layer is provided with a first via hole exposing the second electrode, the fifth insulating layer includes a second via hole exposing the second electrode, the fifth insulating layer covers an inner wall of the first via hole, and the lead-out wire is connected to the second electrode through the second via hole.
In some exemplary embodiments, the orthographic projection of the lead-out lines on the substrate covers the orthographic projection of the active layer on the substrate.
The display device provided by the embodiment of the invention comprises the photoelectric detection substrate provided by the embodiment.
The preparation method provided by the embodiment of the invention comprises the following steps:
the method comprises the steps of forming a photodiode on a substrate, wherein the photodiode comprises a photoelectric conversion layer, the photoelectric conversion layer comprises a first semiconductor layer, a second semiconductor layer and an intrinsic layer arranged between the first semiconductor layer and the second semiconductor layer, the second semiconductor layer is located on one side, far away from the substrate, of the first semiconductor layer, and the band gap of one side, close to the second semiconductor layer, of the intrinsic layer is larger than that of one side, close to the first semiconductor layer, of the intrinsic layer.
In some exemplary embodiments, forming a photodiode on a substrate includes:
depositing a first semiconductor film, a first intrinsic film, a second intrinsic film, a third intrinsic film and a second semiconductor film in sequence, and patterning the second semiconductor film through a patterning process to form a first semiconductor layer, a first sub intrinsic layer, a second sub intrinsic layer, a third sub intrinsic layer and a second semiconductor layer, wherein the first sub intrinsic layer, the second sub intrinsic layer and the third sub intrinsic layer form an intrinsic layer, and the band gaps of the first sub intrinsic layer, the second sub intrinsic layer and the third sub intrinsic layer are increased in sequence.
In some exemplary embodiments, the deposition conditions of the first intrinsic thin film include: the deposition pressure is 1000Pa to 1200Pa, the second intrinsic thin film deposition condition includes a deposition pressure of 1250Pa to 1350Pa, and the second intrinsic thin film deposition condition includes a deposition pressure of 1450Pa to 1550 Pa.
The embodiment of the invention provides a photoelectric detection substrate, a preparation method thereof and a display device, wherein the band gap of one side of an intrinsic layer, which is adjacent to a second semiconductor layer, is set to be larger than the band gap of one side of the intrinsic layer, which is adjacent to a first semiconductor layer, the wide band gap of one side of the intrinsic layer, which is adjacent to the second semiconductor layer, can reduce the absorption of fingerprint reflected light and improve the transmission rate of the fingerprint reflected light, the narrow band gap of one side of the intrinsic layer, which is adjacent to the first semiconductor layer, can increase the absorption of the fingerprint reflected light, the migration distance of a photon-generated carrier is shortened, the magnitude of photocurrent is improved, the high signal-to-noise ratio of a photodiode is.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
Other aspects will be apparent upon reading and understanding the attached drawings and detailed description.
Drawings
The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the example serve to explain the principles of the invention and not to limit the invention.
FIG. 1 is a block diagram of an amorphous silicon photodiode;
fig. 2 is a structural view of a photodetecting substrate according to an exemplary embodiment of the present invention;
fig. 3 is a diagram illustrating simulation results of photocurrent and voltage of a photodetection substrate according to an exemplary embodiment of the present invention;
FIG. 4 is a diagram illustrating simulation results of dark current and voltage of a photodetection substrate according to an exemplary embodiment of the present invention;
FIG. 5 is a schematic view of a substrate after formation of a substrate base plate in accordance with an exemplary embodiment of the present invention;
FIG. 6 is a schematic structural view after a first electrode is formed in accordance with an exemplary embodiment of the present invention;
fig. 7 is a schematic structural view after a second semiconductor layer is formed according to an exemplary embodiment of the present invention;
FIG. 8 is a schematic structural view after forming a second electrode according to an exemplary embodiment of the present invention;
FIG. 9 is a schematic structural diagram after a first via is formed in accordance with an exemplary embodiment of the present invention;
FIG. 10 is a schematic structural view after forming a second via hole in accordance with an exemplary embodiment of the present invention;
fig. 11 is a schematic structural diagram after forming the lead-out lines according to the exemplary embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that the embodiments and features of the embodiments in the present application may be arbitrarily combined with each other without conflict.
Fig. 1 is a structural diagram of an amorphous silicon photodiode. As shown in fig. 1, the main structure of the amorphous silicon PIN photodiode includes a first electrode 11, a second electrode 12 and a photoelectric conversion layer 13 disposed between the first electrode 11 and the second electrode 12, the photoelectric conversion layer 13 includes a first semiconductor layer 131, a second semiconductor layer 132 and an intrinsic layer 133 disposed between the first semiconductor layer 131 and the second semiconductor layer 132, the second electrode 12 may be a transparent electrode, light reflected by a fingerprint may be incident to the photoelectric conversion layer 13 through the second electrode 12 to generate a photocurrent, and fingerprint identification is performed through a difference of photocurrents at different positions of the fingerprint. At present, the photoelectric current of a photodiode adopting an amorphous silicon PIN technology is small, so that the signal-to-noise ratio of the photodiode is low, and the sensitivity of fingerprint identification is influenced. The research of the inventor of the application finds that the main reason for causing the small photocurrent of the amorphous silicon PIN photodiode is as follows: the photogenerated carriers of the amorphous silicon PIN are mainly generated in the intrinsic layer 133, the photogenerated carriers mainly do drift motion under the action of an internal electric field due to the small diffusion length, and light reflected by the fingerprint is mainly absorbed at one side of the intrinsic layer 133 close to the second electrode 12, so that most of the photogenerated carriers cannot drift to the first electrode 11 to be led out.
The embodiment of the invention provides a photoelectric detection substrate which comprises a substrate base plate and a photodiode arranged on the substrate base plate, wherein the photodiode comprises a photoelectric conversion layer, the photoelectric conversion layer comprises a first semiconductor layer, a second semiconductor layer and an intrinsic layer arranged between the first semiconductor layer and the second semiconductor layer, the second semiconductor layer is positioned on one side, far away from the substrate base plate, of the first semiconductor layer, and the band gap of one side, close to the second semiconductor layer, of the intrinsic layer is larger than that of one side, close to the first semiconductor layer, of the intrinsic layer.
According to the embodiment of the invention, the band gap of the intrinsic layer adjacent to the second semiconductor layer is set to be larger than the band gap of the intrinsic layer adjacent to the first semiconductor layer, the wide band gap of the intrinsic layer adjacent to the second semiconductor layer can reduce the absorption of fingerprint reflected light, the fingerprint reflected light transmittance is improved, the narrow band gap of the intrinsic layer adjacent to the first semiconductor layer can increase the absorption of fingerprint reflected light, the photon-generated carrier migration distance is shortened, the magnitude of photocurrent is improved, the high signal-to-noise ratio of the photodiode is realized, and the detection sensitivity of the photoelectric detection substrate is improved.
The following describes an exemplary embodiment of the present invention with reference to the drawings.
Fig. 2 is a structural view of a photodetecting substrate according to an exemplary embodiment of the present invention. As shown in fig. 2, the photodetection substrate 1 includes a substrate 10 and a photodiode disposed on the substrate 10, the photodiode is configured to receive light reflected by a fingerprint and generate a photocurrent, the generated photocurrent can be output to the fingerprint identification module through a detection circuit on the substrate 10, and the fingerprint identification module performs fingerprint identification according to the magnitude of the photocurrent generated by the valleys and ridges of the fingerprint. The photodiode includes a first semiconductor layer 131 and a second semiconductor layer 132, and an intrinsic layer 133 disposed between the first semiconductor layer 131 and the second semiconductor layer 132, and the second semiconductor layer 132 is located on a side of the first semiconductor layer 131 away from the substrate base plate 10, that is, the second semiconductor layer 132 is closer to a side of incident light than the first semiconductor layer 131. The bandgap of the intrinsic layer 133 adjacent to the second semiconductor layer 132 is larger than that of the intrinsic layer 133 adjacent to the first semiconductor layer 131, and is an optical bandgap, which may also be referred to as a forbidden bandwidth. The wider band gap at the side of the intrinsic layer 133 close to the second semiconductor layer 132 can reduce absorption of fingerprint reflected light and increase transmission of the fingerprint reflected light, and the narrow band gap at the side of the intrinsic layer 133 close to the first semiconductor layer 131 can increase absorption of the fingerprint reflected light, so that the position where a photogenerated carrier is generated is closer to the first semiconductor layer 131, loss of the photogenerated carrier caused by short migration distance of the photogenerated carrier is avoided, and the quantity of the photogenerated carrier is increased.
According to the exemplary embodiment of the invention, the band gap of the intrinsic layer 133 adjacent to the second semiconductor layer 132 is set to be larger than the band gap of the intrinsic layer 133 adjacent to the first semiconductor layer 131, the wide band gap of the intrinsic layer 133 adjacent to the second semiconductor layer 132 can reduce the absorption of the fingerprint reflected light by the intrinsic layer 133 adjacent to the second semiconductor layer 132, so as to improve the fingerprint reflected light transmittance, and the narrow band gap of the intrinsic layer 133 adjacent to the first semiconductor layer 131 can increase the absorption of the fingerprint reflected light by the intrinsic layer 133 adjacent to the first semiconductor layer 131, so as to increase the number of photo-generated carriers, improve the magnitude of photocurrent, further realize a high signal-to-noise ratio of the photodiode, and improve the detection sensitivity of the photodetection substrate 1.
In some exemplary embodiments, the bandgap of the intrinsic layer 133 is arranged in a gradient in a direction away from the first semiconductor layer 131. That is, the band gap of the intrinsic layer is graded and gradually increased in a direction away from the first semiconductor layer 131.
In some exemplary embodiments, as shown in fig. 2, the intrinsic layer 133 includes a plurality of sub-intrinsic layers whose band gaps sequentially increase in a direction away from the first semiconductor layer 131. The plurality of sub intrinsic layers may include two, three, five or seven layers, which are set according to actual needs. The sub-intrinsic layer may have a thickness between 100 nm and 300 nm. The plurality of sub-intrinsic layers may include a first sub-intrinsic layer 134, a second sub-intrinsic layer 135, and a third sub-intrinsic layer 136, which are stacked, the first sub-intrinsic layer 134 being adjacent to the first semiconductor layer 131, the third sub-intrinsic layer 136 being adjacent to the second semiconductor layer 132,
in some exemplary embodiments, the bandgap of the intrinsic layer 133 is between 1.4ev and 2.4ev, and the bandgap difference of the adjacent sub-intrinsic layers is between 0.15ev and 0.3 ev. In an exemplary embodiment, the bandgap of the first sub intrinsic layer 134 is between 1.5ev and 1.7ev, for example 1.6 ev. The bandgap of the second sub-intrinsic layer 135 is between 1.75ev and 1.9ev, for example 1.8 ev. The third sub-intrinsic layer 136 has a bandgap between 1.95ev and 2.1ev, for example 2.0 ev. The second sub-intrinsic layer 135 may be referred to as a medium bandgap, the first sub-intrinsic layer 134 may be referred to as a narrow bandgap and the third sub-intrinsic layer 136 may be referred to as a wide bandgap compared to the second sub-intrinsic layer 135. The intrinsic layer 133 may be an amorphous silicon layer. The intrinsic layer 133 is thick and occupies almost the entire depletion layer, and most of the incident light is absorbed in the intrinsic layer 133 and generates a large number of electron-hole pairs.
In some exemplary embodiments, the first semiconductor layer 131 is an n-type semiconductor layer, for example, the first semiconductor layer 131 may be a phosphorus-doped amorphous silicon layer. The band gap of the first semiconductor layer 131 is between 1.5ev and 1.7ev, for example, 1.6 ev. The second semiconductor layer 132 is a p-type semiconductor layer, for example, the second semiconductor layer 132 may be a boron-doped amorphous silicon layer. The band gap of the second semiconductor layer 132 is between 1.95ev and 2.1ev, for example, 2.0 ev. The intrinsic layer 133 near the first semiconductor layer 131 can be understood as the first sub-intrinsic layer 134, and the bandgap of the first semiconductor layer 131 is the same as or close to that of the intrinsic layer 133 near the first semiconductor layer 131, i.e., the bandgap ratio of the first semiconductor layer 131 to the first sub-intrinsic layer 134 is between 0.9 and 1.2. The side of the intrinsic layer 133 close to the second semiconductor layer 132 may be understood as the third sub-intrinsic layer 136, and the bandgap of the second semiconductor layer 132 is the same as or close to that of the intrinsic layer 133 close to the second semiconductor layer 132, i.e., the bandgap ratio of the second semiconductor layer 132 to that of the third sub-intrinsic layer 136 is between 0.9 and 1.2. The band gap of the intrinsic layer 133 near the second semiconductor layer 132 is the same as or close to the band gap of the second semiconductor layer 132, and the band gap of the intrinsic layer 133 near the first semiconductor layer 131 is the same as or close to the band gap of the first semiconductor layer 131, so that the matching of the band gaps between the first semiconductor layer 131 and the intrinsic layer 133 and between the second semiconductor layer 132 and the intrinsic layer 133 is improved, the interface state defects between the first semiconductor layer 131 and the intrinsic layer 133 and between the second semiconductor layer 132 and the intrinsic layer 133 are reduced, the photocurrent is improved, the dark current is reduced, and the signal-to-noise ratio of the photodiode is increased.
Fig. 3 is a diagram illustrating simulation results of photocurrent and voltage of a photodetection substrate according to an exemplary embodiment of the present invention, and fig. 4 is a diagram illustrating simulation results of dark current and voltage of a photodetection substrate according to an exemplary embodiment of the present invention. The photodetecting substrate 1 according to the exemplary embodiment of the present invention is substantially the same as the conventional photodetecting substrate except for the structure of the intrinsic layer 133. Among them, the band gap of the first sub intrinsic layer 134, the band gap of the second sub intrinsic layer 135, the band gap of the third sub intrinsic layer 136, and the band gap of the intrinsic layer of the conventional photodetection substrate are 1.6ev, 1.8ev, the first semiconductor layer 131 is an n-type semiconductor layer, and 1.6ev, respectively, to obtain the simulation results. The second semiconductor layer 132 is a p-type semiconductor layer, and the band gap of the second semiconductor layer 132 is 2.0 ev. As shown by a dotted line frame in fig. 3, under the same illumination condition, the logarithm of the photocurrent of the photodetection substrate 1 according to the exemplary embodiment of the present invention is about-8.7, and the logarithm of the photocurrent of the conventional photodetection substrate is about-9.2, in contrast, the logarithm of the photocurrent of the photodetection substrate 1 according to the exemplary embodiment of the present invention is about 0.5 greater than that of the conventional photodetection substrate. As shown by the dotted line frame in fig. 4, the logarithm of the dark current of the photodetection substrate 1 according to the exemplary embodiment of the present invention is about-15, and the logarithm of the dark current of the conventional photodetection substrate is about-14, compared to that, the logarithm of the dark current of the photodetection substrate 1 according to the exemplary embodiment of the present invention is smaller than the logarithm of the dark current of the conventional photodetection substrate by about 1, and as can be seen from a comparison between fig. 3 and fig. 4, compared to the conventional photodetection substrate, the photocurrent of the photodetection substrate 1 according to the exemplary embodiment of the present invention is increased, the dark current is decreased, and further, the signal-to-noise ratio is increased, thereby improving the sensitivity of the photodetection substrate 1.
In some exemplary embodiments, the photodiode further includes a first electrode 11 and a second electrode 12, the first electrode 11 is disposed on a side of the first semiconductor layer 131 facing the substrate base plate 10, and the second electrode 12 is disposed on a side of the second semiconductor layer 132 facing away from the substrate base plate 10. In some exemplary embodiments, the material of the first electrode 11 includes at least one of silver Ag, copper Cu, aluminum Al, and molybdenum Mo, and may have a single layer structure or a plurality of composite structures, and is deposited by a magnetron sputtering method (Sputter). The material of the second electrode 12 includes indium tin oxide ITO, indium zinc oxide IZO, or amorphous indium tin oxide α -ITO, which may be a single layer, multiple layers, or a composite layer, and is deposited by a magnetron sputtering method (Sputter).
In some exemplary embodiments, the base substrate 10 includes a substrate 14 and a thin film transistor 15 disposed on the substrate 14, the thin film transistor 15 includes a gate electrode 161, an active layer 18, a first pole 191 and a second pole 192, and the first electrode 11 and the second pole 192 are connected. The first pole 191 may be a source electrode and the second pole 192 may be a drain electrode, and in other exemplary embodiments, the first pole 191 may be a drain electrode and the second pole 192 may be a source electrode. In an example, the substrate 10 main body structure may include a substrate 14, a gate metal layer 16 disposed on the substrate 14, a first insulating layer 17 disposed on a side of the gate metal layer 16 away from the substrate 14, an active layer 18 disposed on a side of the first insulating layer 17 away from the gate metal layer 16, a source drain metal layer 19 disposed on a side of the active layer 18 away from the first insulating layer 17, and a second insulating layer 20 disposed on a side of the source drain metal layer 19 away from the active layer 18, where the gate metal layer 16 includes a gate electrode 161, and an orthographic projection of the gate electrode 161 on the substrate 14 at least partially overlaps an orthographic projection of the active layer 18 on the substrate 14. The source-drain metal layer 19 includes a first pole 191 and a second pole 192, and a data line (not shown in the drawing) connected to the first pole 191, an end of the first pole 191 adjacent to the second pole 192 overlaps the active layer 18, an end of the second pole 192 adjacent to the first pole 191 overlaps the active layer 18, a conductive channel is formed between the first pole 191 and the second pole 192, the second insulating layer 20 includes an active via exposing the second pole 192, and the first electrode 11 is connected to the second pole 192 through the active via. The gate electrode 161, the active layer 18, the first electrode 191, and the second electrode 192 constitute the thin film transistor 15. Light reflected by the fingerprint is absorbed by the photodiode and converted into an electric signal and stored in the first electrode 11, the gate 161 of the thin film transistor 15 is connected with the scanning circuit, the thin film transistor 15 is turned on under the action of the scanning circuit, and the electric signal stored in the first electrode 11 can be transmitted to the fingerprint identification module through the second pole 192, the first pole 191 and the data line.
In some exemplary embodiments, the photodetecting substrate 1 further includes a third insulating layer 21 and a fourth insulating layer 22 disposed on a side of the second insulating layer 20 away from the substrate 14 and wrapping the photodiode, and a planarization layer 23 disposed on a side of the fourth insulating layer 22 away from the substrate 14, a first via hole exposing the second electrode 12 is disposed on the planarization layer 23, and the third insulating layer 21 and the fourth insulating layer 22 in the first via hole are etched away. The photodetection substrate 1 further includes a fifth insulating layer 24 disposed on a side of the flat layer 23 away from the substrate 14, a lead-out line 25 disposed on a side of the fifth insulating layer 24 away from the substrate 14, and a package layer 26 disposed on a side of the lead-out line 25 away from the substrate 14, the fifth insulating layer 24 includes a second via hole exposing the second electrode 12, the second via hole corresponds to the first via hole in position, and the fifth insulating layer 24 covers an inner wall of the first via hole. The lead-out line 25 is connected to the second electrode 12 through the second via hole. A bias voltage can be applied to the photodiode through the lead-out line 25 to increase the sensitivity of the photodetection substrate 1.
In some exemplary embodiments, the orthographic projection of the lead-out lines 25 on the substrate 14 covers the orthographic projection of the active layer 18 on the substrate 14. The orthographic projection of the outgoing line 25 on the substrate 14 covers the orthographic projection of the active layer 18 on the substrate 14, so that light can be prevented from being incident on the active layer 18, and the working stability of the thin film transistor 15 is ensured.
The following is an exemplary explanation of the manufacturing process of the photodetecting substrate. The "patterning process" as referred to herein includes processes of coating a photoresist, mask exposing, developing, etching, peeling a photoresist, etc., for a metal material, an inorganic material, or a transparent conductive material, and processes of coating an organic material, mask exposing, developing, etc., for an organic material. The deposition can be any one or more of sputtering, evaporation and chemical vapor deposition, the coating can be any one or more of spraying, spin coating and ink-jet printing, and the etching can be any one or more of dry etching and wet etching, which is not limited in the application. "thin film" refers to a layer of a material deposited, coated, or otherwise formed on a substrate. The "thin film" may also be referred to as a "layer" if it does not require a patterning process throughout the fabrication process. If the "thin film" requires a patterning process during the entire fabrication process, it is referred to as "thin film" before the patterning process and "layer" after the patterning process. The "layer" after the patterning process includes at least one "pattern".
(1) A base substrate 10 is formed. Fig. 5 is a schematic structural diagram after a substrate base plate is formed according to an exemplary embodiment of the present invention. As shown in fig. 5, forming the base substrate 10 includes:
a gate metal layer 16 is patterned. Patterning the gate metal layer 16 includes: a first metal film is deposited on the substrate 14, and the first metal film is patterned through a patterning process to form a gate metal layer 16 pattern on the substrate 14, the gate metal layer 16 pattern including a gate line (not shown), a gate electrode 161, and a gate connection electrode (not shown).
An active layer 18 is patterned. Forming the active layer 18 pattern includes: a first insulating film and an active layer film are sequentially deposited on the substrate 14 formed with the aforementioned patterns, and the active layer film is patterned through a patterning process to form a first insulating layer 17 covering the pattern of the gate metal layer 16 and an active layer 18 pattern disposed on the first insulating layer 17, the position of the active layer 18 corresponding to the position of the gate electrode 161.
Source drain metal layer 19 is patterned. Patterning the source-drain metal layer 19 includes: depositing a second metal film on the substrate 14 formed with the aforementioned pattern, patterning the second metal film through a patterning process, and forming a data line (not shown in the drawing) disposed on the first insulating layer 17, a first pole 191 and a second pole 192 pattern, wherein the first pole 191 and the data line are connected to each other in an integral structure, one end of the first pole 191 adjacent to the second pole 192 is disposed on the active layer 18, one end of the second pole 192 adjacent to the first pole 191 is disposed on the active layer 18, and a conductive channel is formed between the first pole 191 and the second pole 192. In this example, the first pole 191 may be a source electrode and the second pole 192 may be a drain electrode.
Active via k1 pattern is formed. Forming the active via k1 pattern includes: a second insulating film is deposited on the substrate 14 formed with the aforementioned pattern, and the second insulating film is patterned through a patterning process to form a pattern of active via holes k1, the second insulating film forming the second insulating layer 20, and the active via holes k1 exposing the surface of the second pole 192.
(2) The first electrode 11 is patterned. Forming the first electrode 11 pattern includes: a third metal film is deposited on the substrate 14 on which the aforementioned pattern is formed, and the third metal film is patterned through a patterning process, as shown in fig. 6, to form a pattern of the first electrode 11, and the first electrode 11 is connected to the second electrode 192 through an active via. Fig. 6 is a schematic structural view after a first electrode is formed according to an exemplary embodiment of the present invention.
(3) The photoelectric conversion layer 13 is patterned. Forming the photoelectric conversion layer 13 pattern includes: a first semiconductor thin film, a first intrinsic thin film, a second intrinsic thin film, and a third intrinsic thin film and a second semiconductor thin film are sequentially deposited on the substrate 14 where the aforementioned patterns are formed, and the second semiconductor thin film is patterned through a patterning process, as shown in fig. 7, to form a first semiconductor layer 131, a first sub intrinsic layer 134, a second sub intrinsic layer 135, and a third sub intrinsic layer 136, and a second semiconductor layer 132. The orthographic projection of the first semiconductor layer 131 on the substrate 14 is within the range of the orthographic projection of the first electrode 11 on the substrate 14. The first semiconductor layer 131 is an n-type semiconductor layer, for example, the first semiconductor layer 131 may be a phosphorus-doped amorphous silicon layer. The band gap of the first semiconductor layer 131 is between 1.5ev and 1.7ev, for example, 1.6 ev. The first sub-intrinsic layer 134, the second sub-intrinsic layer 135, and the third sub-intrinsic layer 136 constitute the intrinsic layer 133, and band gaps of the first sub-intrinsic layer 134, the second sub-intrinsic layer 135, and the third sub-intrinsic layer 136 sequentially increase. Amorphous silicon may be used as the material of the intrinsic layer 133. The band gap of the first sub intrinsic layer 134 is between 1.5ev and 1.7ev, the thickness of the first sub intrinsic layer 134 is between 100 nm and 300 nm, the band gap of the second sub intrinsic layer 135 is between 1.75ev and 1.9ev, the thickness of the second sub intrinsic layer 135 is between 100 nm and 300 nm, the band gap of the third sub intrinsic layer 136 is between 1.95ev and 2.1ev, and the thickness of the third sub intrinsic layer 136 is between 100 nm and 300 nm. The orthographic projections of the first sub intrinsic layer 134, the second sub intrinsic layer 135 and the third sub intrinsic layer 136 on the substrate 14 are within the range of the orthographic projection of the first electrode 11 on the substrate 14. The orthographic projection of the second semiconductor layer 132 on the substrate 14 is within the range of the orthographic projection of the first electrode 11 on the substrate 14. The second semiconductor layer 132 is a p-type semiconductor layer, for example, the second semiconductor layer 132 may be a boron-doped amorphous silicon layer. The band gap of the second semiconductor layer 132 is between 1.95ev and 2.1ev, for example, 2.0 ev. Fig. 7 is a schematic structural view after a second semiconductor layer is formed according to an exemplary embodiment of the present invention.
In some exemplary embodiments, the intrinsic layer is prepared by a PECVD method, mainly silane flow and deposition pressure affecting the band gap, and intrinsic thin films with different band gaps can be prepared by changing the deposition pressure. Deposition conditions of the first intrinsic thin film 4: deposition pressure 1000Pa to 1200Pa, such as 1100Pa, silane flow rate between 150sccm to 300 sccm; deposition conditions of the second intrinsic thin film: deposition pressures 1250Pa to 1350Pa, such as 1300Pa, with a silane flow rate between 150sccm to 300 sccm; the third intrinsic thin film is deposited at a pressure of 1450Pa to 1550Pa, such as 1500Pa, and a silane flow rate of 150sccm to 300 sccm. In the process of preparing the intrinsic thin film, other process parameters, except for deposition pressure, may be the same, and include silane flow rate, hydrogen flow rate, deposition temperature, and the like.
(4) The second electrode 12 is patterned. Forming the second electrode 12 pattern includes: a transparent conductive film is deposited on the substrate 14 on which the aforementioned pattern is formed, and the transparent conductive film is patterned through a patterning process, as shown in fig. 8, to form a second electrode 12 pattern. The orthographic projection of the second electrode 12 on the substrate 14 is within the range of the orthographic projection of the first electrode 11 on the substrate 14. Fig. 8 is a schematic structural view after forming a second electrode according to an exemplary embodiment of the present invention.
(5) A first via k2 pattern is formed. Forming the first via k2 pattern includes: on the substrate 14 of the aforementioned pattern, a third insulating film and a fourth insulating film are deposited, a flat film is coated on the fourth insulating film, and the flat film is patterned through a patterning process, as shown in fig. 9, to form a first via hole k2 pattern. The first via hole k2 exposes the second electrode 12, and the planarization film, the third insulating film, and the fourth insulating film within the first via hole k2 are etched away. The planarization film forms a planarization layer 23, the third insulation film forms a third insulation layer 21, the fourth insulation film forms a fourth insulation layer 22, the third insulation layer 21 and the fourth insulation layer 22 wrap the sidewalls of the first semiconductor layer 131, the intrinsic layer 133 and the second semiconductor layer 132, and leakage current formed on the sidewalls of the first semiconductor layer 131, the intrinsic layer 133 and the second semiconductor layer 132 can be prevented. Fig. 9 is a schematic structural diagram after a first via hole is formed according to an exemplary embodiment of the invention.
(6) A second via k3 pattern is formed. Forming the second via k3 pattern includes: on the base 14 where the foregoing pattern is formed, a fifth insulating film is deposited, and the fifth insulating film is patterned through a patterning process, as shown in fig. 10, to form a second via hole k3 pattern. The second via k3 corresponds to the first via position, and the second via k3 exposes the second electrode 12. The fifth insulating film forms a fifth insulating layer 24, and the fifth insulating layer 24 covers the inner wall of the first via hole. Fig. 10 is a schematic structural diagram after forming a second via hole according to an exemplary embodiment of the invention.
(7) Lead-out lines 25 are patterned. Forming the pattern of lead-out lines 25 includes: on the substrate 14 on which the foregoing pattern is formed, a third metal thin film is deposited, and the third metal thin film is patterned by a patterning process, as shown in fig. 11, to form a pattern of lead-out lines 25. The lead-out line 25 is connected to the second electrode 12 through the second via hole, and an orthographic projection of the lead-out line 25 on the substrate 14 covers an orthographic projection of the active layer 18 on the substrate 14. Fig. 11 is a schematic structural diagram after forming the lead-out lines according to the exemplary embodiment of the present invention.
(8) An encapsulation layer 26 is formed. Forming the encapsulation layer 26 includes: an inorganic encapsulation film is deposited on the substrate 14 with the pattern formed thereon, the inorganic encapsulation film covering the structure, and the inorganic encapsulation film forming an encapsulation layer 26.
Through the foregoing manufacturing process, the manufacturing of the photodetection substrate 1 is completed. The prepared photodetection substrate 1 includes:
a substrate 14;
a gate metal layer 16 disposed on the substrate, the gate metal layer 16 at least including a gate electrode 161, a gate line and a gate connection electrode;
a first insulating layer 17 disposed on a side of the gate metal layer 16 away from the substrate;
an active layer 18 disposed on a side of the first insulating layer 17 away from the gate metal layer 16;
the source-drain metal layer 19 is disposed on one side of the active layer 18 away from the first insulating layer 17, the source-drain metal layer 19 includes a first electrode 191, a second electrode 192, and a data line connected to the first electrode 191, the first electrode 191 may be a source electrode, and the second electrode 192 may be a drain electrode;
the second insulating layer 20 is arranged on one side, far away from the active layer 18, of the source drain metal layer 19, and an active through hole exposing the second pole 192 is formed in the second insulating layer 20;
the first electrode 11 is arranged on one side, far away from the source-drain metal layer 19, of the second insulating layer 20, and the first electrode 11 is connected with the second pole 192 through an active via hole;
a first semiconductor layer 131 disposed on the first electrode 11;
an intrinsic layer 133 disposed on the first semiconductor layer 131, wherein a band gap of the intrinsic layer 133 gradually increases along a direction away from the first semiconductor layer 131 to form a gradient band gap structure, the intrinsic layer 133 may include a first sub-intrinsic layer 134, a second sub-intrinsic layer 135 and a third sub-intrinsic layer 136 stacked, and the first sub-intrinsic layer 134 is disposed on the first semiconductor layer 131;
a second semiconductor layer 132 disposed on the intrinsic layer 133 at a side away from the first semiconductor layer 131;
a second electrode 12 disposed on a side of the second semiconductor layer 132 away from the intrinsic layer 133;
the third insulating layer 21, the fourth insulating layer 22 and the flat layer 23 are arranged on one side of the second electrode 12 far away from the second semiconductor layer 132, and a first through hole exposing the second electrode 12 is arranged on the flat layer 23;
a fifth insulating layer 24 disposed on the planarization layer 23, wherein a second via hole is disposed on the fifth insulating layer 24, an orthographic projection of the second via hole on the substrate 14 is located within an orthographic projection range of the first via hole on the substrate 14, the second via hole exposes the second electrode 12, and the fifth insulating layer 24 covers an inner wall of the first via hole;
the lead-out wire 25 is arranged on one side, far away from the flat layer 23, of the fifth insulating layer 24, the lead-out wire 25 is connected with the second electrode 12 through the second through hole, and the orthographic projection of the lead-out wire 25 on the substrate 14 covers the orthographic projection of the active layer 18 on the substrate 14;
an encapsulation layer 26 is formed.
In some exemplary embodiments, in the above manufacturing process, the substrate may be a glass substrate or a quartz substrate. The material of the first metal film, the second metal film and the third metal film may include at least one of silver Ag, copper Cu, aluminum Al and molybdenum Mo, may be a single-layer structure, or may be a plurality of composite structures, and is deposited by a magnetron sputtering method (Sputter). The materials of the first insulating film, the second insulating film, the third insulating film, the fourth insulating film and the fifth insulating film may include at least one of silicon oxide SiOx, silicon nitride SiNx, silicon oxynitride SiON, aluminum oxide AlOx, hafnium oxide HfOx and tantalum oxide TaOx, and may be single-layer, multi-layer or composite layers, and are deposited by Chemical Vapor Deposition (CVD) or Plasma Enhanced Chemical Vapor Deposition (PECVD). The first insulating layer 17 may also be referred to as a gate insulating layer, the second insulating layer 20 may be referred to as an interlayer insulating layer, the third insulating layer 21, the fourth insulating layer 22, and the fifth insulating layer 24 may be referred to as a passivation layer, and the material of the flat film may be an inorganic material such as silicon oxide SiOx, silicon nitride SiNx, or silicon oxynitride SiON, or may be an organic material such as a photosensitive organic resin material, and when the photosensitive organic resin material is used, a film is formed by coating. The material of the transparent conductive film comprises Indium Tin Oxide (ITO), Indium Zinc Oxide (IZO) or amorphous indium tin oxide (alpha-ITO), and can be single-layer, multiple or composite layer, and is deposited by a magnetron sputtering method (Sputter). The active layer 18 film may be made of amorphous silicon material a-Si. The inorganic packaging film may include at least one of silicon oxide SiOx, silicon nitride SiNx, silicon oxynitride SiON, aluminum oxide AlOx, hafnium oxide HfOx, and tantalum oxide TaOx, and may be a single layer, multiple layers, or a composite layer, and is deposited by Chemical Vapor Deposition (CVD) or Plasma Enhanced Chemical Vapor Deposition (PECVD).
As can be seen from the manufacturing process of the photodetection substrate 1 according to the exemplary embodiment of the present invention, when the intrinsic layer 133 is deposited, by controlling the deposition pressure, the bandgap gradient of the intrinsic layer 133 is increased in the direction away from the first semiconductor layer 131, that is, the first sub-intrinsic layer 134 forms a narrow bandgap, the second sub-intrinsic layer 135 forms a middle bandgap, the third sub-intrinsic layer 136 forms a wide bandgap, the light reflected by the fingerprint is less absorbed in the third sub-intrinsic layer 136, and thus the transmission is increased, and the light reflected by the fingerprint is mainly absorbed in the second sub-intrinsic layer 135 with a bandgap and the first sub-intrinsic layer 134 with a narrow bandgap, the drift distance of the photo-generated carriers is reduced, the number of the photo-generated carriers reaching the first electrode 11 is increased, and the photo current is further increased. In addition, the band gap of the first semiconductor layer 131 is close to the band gap of the first sub intrinsic layer 134, and the band gap of the second semiconductor layer 132 is close to the band gap of the third sub intrinsic layer 136, so that the matching of the band gaps between the first semiconductor layer 131 and the intrinsic layer 133 and between the second semiconductor layer 132 and the intrinsic layer 133 is improved, the interface state defects between the first semiconductor layer 131 and the intrinsic layer 133 and between the second semiconductor layer 132 and the intrinsic layer 133 are reduced, the photocurrent is improved, the dark current is reduced, and the signal-to-noise ratio of the photodiode is increased.
The embodiment of the invention also provides a preparation method of the photoelectric detection substrate, which comprises the following steps:
the method comprises the steps of forming a photodiode on a substrate, wherein the photodiode comprises a photoelectric conversion layer, the photoelectric conversion layer comprises a first semiconductor layer, a second semiconductor layer and an intrinsic layer arranged between the first semiconductor layer and the second semiconductor layer, the second semiconductor layer is located on one side, far away from the substrate, of the first semiconductor layer, and the band gap of one side, close to the second semiconductor layer, of the intrinsic layer is larger than that of one side, close to the first semiconductor layer, of the intrinsic layer.
In some exemplary embodiments, forming a photodiode on a substrate includes: depositing a first semiconductor film, a first intrinsic film, a second intrinsic film, a third intrinsic film and a second semiconductor film in sequence, and patterning the second semiconductor film through a patterning process to form a first semiconductor layer, a first sub intrinsic layer, a second sub intrinsic layer, a third sub intrinsic layer and a second semiconductor layer, wherein the first sub intrinsic layer, the second sub intrinsic layer and the third sub intrinsic layer form an intrinsic layer, and the band gaps of the first sub intrinsic layer, the second sub intrinsic layer and the third sub intrinsic layer are increased in sequence.
In some exemplary embodiments, the deposition conditions of the first intrinsic thin film include: the deposition pressure is 1000Pa to 1200Pa, the second intrinsic thin film deposition condition includes a deposition pressure of 1250Pa to 1350Pa, and the second intrinsic thin film deposition condition includes a deposition pressure of 1450Pa to 1550 Pa.
The embodiment of the invention also provides a display device which comprises the photoelectric detection substrate provided by the embodiment. The display device may include: any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.
The drawings in this application relate only to the structures to which the disclosure relates and other structures may be referred to in the general design. Without conflict, the features of the embodiments, i.e., embodiments, of the present application may be combined with each other to arrive at a new embodiment.
It will be understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the spirit and scope of the present invention as defined in the claims.
Claims (15)
1. A photodetecting substrate, characterized by comprising: the photoelectric conversion layer comprises a first semiconductor layer, a second semiconductor layer and an intrinsic layer arranged between the first semiconductor layer and the second semiconductor layer, the second semiconductor layer is positioned on one side, away from the substrate, of the first semiconductor layer, and the band gap of one side, close to the second semiconductor layer, of the intrinsic layer is larger than that of one side, close to the first semiconductor layer, of the intrinsic layer.
2. The photodetecting substrate according to claim 1, characterized in that: and the band gaps of the intrinsic layers are arranged in a gradient manner in the direction away from the first semiconductor layer.
3. The photodetecting substrate according to claim 1, characterized in that: the intrinsic layer comprises a plurality of sub intrinsic layers, and the band gaps of the sub intrinsic layers are sequentially increased in the direction far away from the first semiconductor layer.
4. The photodetecting substrate according to claim 3, characterized in that: the band gap difference of the adjacent sub intrinsic layers is between 0.15ev and 0.3 ev.
5. The photodetecting substrate according to claim 3, characterized in that: the plurality of sub intrinsic layers comprise a first sub intrinsic layer, a second sub intrinsic layer and a third sub intrinsic layer which are stacked, the first sub intrinsic layer is adjacent to the first semiconductor layer, the third sub intrinsic layer is adjacent to the second semiconductor layer, the band gap of the first sub intrinsic layer is between 1.5ev and 1.7ev, the band gap of the second sub intrinsic layer is between 1.75ev and 1.9ev, and the band gap of the third sub intrinsic layer is between 1.95ev and 2.1 ev.
6. The photodetecting substrate according to claim 5, characterized in that: the ratio of the band gap of the first semiconductor layer to the band gap of the first sub-intrinsic layer is 0.9-1.2, and the ratio of the band gap of the second semiconductor layer to the band gap of the third sub-intrinsic layer is 0.9-1.2.
7. The photodetecting substrate according to any one of claims 1 to 4, characterized in that: the band gap of the intrinsic layer is between 1.4ev and 2.4 ev.
8. The photodetecting substrate according to any one of claims 1 to 6, characterized in that: the first semiconductor layer is an n-type semiconductor layer, and the second semiconductor layer is a p-type semiconductor layer.
9. The photodetecting substrate according to any one of claims 1 to 6, characterized in that: the photodiode further comprises a first electrode and a second electrode, the first electrode is arranged on one side, facing the substrate base plate, of the first semiconductor layer, the second electrode is arranged on one side, far away from the substrate base plate, of the second semiconductor layer, the substrate base plate comprises a base plate and a thin film transistor arranged on the base plate, the thin film transistor comprises a grid electrode, an active layer, a first pole and a second pole, and the first electrode is connected with the second pole.
10. The photodetecting substrate according to claim 9, characterized in that: the substrate base plate comprises a first insulating layer arranged on the grid electrode, a second insulating layer covering the first electrode and the second electrode, a third insulating layer and a fourth insulating layer which are arranged on one side of the second insulating layer far away from the base plate and wrap the photodiode, a flat layer arranged on one side of the fourth insulating layer far away from the base plate, a fifth insulating layer arranged on one side of the flat layer far away from the base plate, and a leading-out wire arranged on one side of the fifth insulating layer far away from the base plate, a first via hole exposing the second electrode is disposed on the planarization layer, the fifth insulating layer includes a second via hole exposing the second electrode, the second via hole corresponds to the first via hole in position, the fifth insulating layer covers the inner wall of the first via hole, and the outgoing line is connected with the second electrode through the second via hole.
11. The photodetecting substrate according to claim 10, characterized in that: the orthographic projection of the lead-out wire on the substrate covers the orthographic projection of the active layer on the substrate.
12. A display device comprising the photodetecting substrate according to any one of claims 1 to 11.
13. A method for preparing a photoelectric detection substrate is characterized by comprising the following steps:
forming a photodiode on a substrate, wherein the photodiode comprises a photoelectric conversion layer, the photoelectric conversion layer comprises a first semiconductor layer, a second semiconductor layer and an intrinsic layer arranged between the first semiconductor layer and the second semiconductor layer, the second semiconductor layer is positioned on one side of the first semiconductor layer far away from the substrate, and the band gap of one side of the intrinsic layer close to the second semiconductor layer is larger than that of one side of the intrinsic layer close to the first semiconductor layer.
14. The method of manufacturing according to claim 13, wherein: forming a photodiode on a substrate, comprising: depositing a first semiconductor film, a first intrinsic film, a second intrinsic film, a third intrinsic film and a second semiconductor film in sequence, and patterning the second semiconductor film through a patterning process to form a first semiconductor layer, a first sub intrinsic layer, a second sub intrinsic layer, a third sub intrinsic layer and a second semiconductor layer, wherein the intrinsic layer is formed by the first sub intrinsic layer, the second sub intrinsic layer and the third sub intrinsic layer, and the band gaps of the first sub intrinsic layer, the second sub intrinsic layer and the third sub intrinsic layer are increased in sequence.
15. The method of claim 14, wherein: the deposition conditions of the first intrinsic thin film include: deposition pressure 1000Pa to 1200Pa, the second intrinsic thin film deposition condition including deposition pressure 1250Pa to 1350Pa, and the second intrinsic thin film deposition condition including deposition pressure 1450Pa to 1550 Pa.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023000963A1 (en) * | 2021-07-23 | 2023-01-26 | 京东方科技集团股份有限公司 | Pattern recognition substrate and display device |
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| CN108352393A (en) * | 2015-07-23 | 2018-07-31 | 奥特逻科集团 | High-efficiency wide-spectrum sensor |
| CN111628035A (en) * | 2020-06-10 | 2020-09-04 | 京东方科技集团股份有限公司 | Photoelectric detector and preparation method thereof |
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| CN102832269A (en) * | 2011-06-17 | 2012-12-19 | 中国科学院微电子研究所 | Photoelectric detection lamination, semiconductor ultraviolet detector and manufacturing method of semiconductor ultraviolet detector |
| CN108352393A (en) * | 2015-07-23 | 2018-07-31 | 奥特逻科集团 | High-efficiency wide-spectrum sensor |
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| WO2023000963A1 (en) * | 2021-07-23 | 2023-01-26 | 京东方科技集团股份有限公司 | Pattern recognition substrate and display device |
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