CN112382608A - Method for manufacturing copper interconnection line - Google Patents

Method for manufacturing copper interconnection line Download PDF

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Publication number
CN112382608A
CN112382608A CN202011214868.3A CN202011214868A CN112382608A CN 112382608 A CN112382608 A CN 112382608A CN 202011214868 A CN202011214868 A CN 202011214868A CN 112382608 A CN112382608 A CN 112382608A
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CN
China
Prior art keywords
copper
layer
manufacturing
interlayer film
copper interconnect
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CN202011214868.3A
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Chinese (zh)
Inventor
许家彰
蔡旻錞
陈建勋
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Shanghai Huali Integrated Circuit Manufacturing Co Ltd
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Shanghai Huali Integrated Circuit Manufacturing Co Ltd
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Priority to CN202011214868.3A priority Critical patent/CN112382608A/en
Publication of CN112382608A publication Critical patent/CN112382608A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76837—Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H01L21/76892—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances modifying the pattern
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
    • H01L2221/1005—Formation and after-treatment of dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
    • H01L2221/1068—Formation and after-treatment of conductors

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The invention discloses a method for manufacturing a copper interconnection line, which comprises the following steps: providing a front layer film with a flat surface, forming a barrier layer and a copper seed crystal layer on the front layer film, and electroplating on the copper seed crystal layer to form a copper layer; etching the copper layer, the copper seed crystal layer and the barrier layer in the selected area by a copper reactive ion etching process, and forming a copper interconnection line by overlapping the barrier layer, the copper seed crystal layer and the copper layer which are not etched; forming a cobalt layer to coat the top surface and the side surface of the copper interconnection line; and step four, filling an interlayer film between the copper interconnection lines. The invention can eliminate the problem of copper hole filling, can ensure that the integrity of the copper interconnection line is very good, thereby reducing the on-resistance and being well suitable for technical nodes below 7 nm.

Description

Method for manufacturing copper interconnection line
Technical Field
The invention relates to the field of manufacturing of semiconductor integrated circuits, in particular to a method for manufacturing a copper interconnection line.
Background
In the prior art, a damascene process is usually adopted to form a copper interconnection line, i.e. a back end of line (BEOL) copper wire, and a dual damascene process which simultaneously forms a copper interconnection line and a through hole is also usually adopted, as shown in fig. 1A to fig. 1C, the dual damascene process is a schematic device structure diagram in each step of the manufacturing method of the prior damascene process, and the manufacturing method of the prior damascene process comprises the following steps:
step one, as shown in fig. 1A, a front layer film 101, in fig. 1A, the front layer film 101 is a metal front interlayer film (PMD), and a contact hole (CT) is formed in the front layer film 101.
Step two, as shown in fig. 1A, a nitrogen-Doped silicon carbide (NDC) layer 102 is formed, and the NDC layer 102 serves as a barrier layer for upward diffusion of the bottom metal layer.
A SiO2 layer 103 is formed on the NDC layer 102.
The low K dielectric layer 104 is formed, and the material of the low K dielectric layer 104 includes BD or BD ii. BD is a dielectric material composed of elements such as C, H, O, Si and the like, and has a K value of 2.5-3.3. BD ii is an improved version of BD. In FIG. 1A, the low K dielectric layer 104 is shown as BDII.
And step three, forming an NDC layer 103 on the top surface of the low-K dielectric layer 104 to serve as a metal diffusion barrier layer on the top.
A nitrogen free anti-reflective coating (NFDARC)106 is then formed on the surface of the NDC layer 103.
Step four, forming a metal hard mask layer (MHM)107 on the surface of the NFDARC layer 106, wherein the material of the metal hard mask layer 107 is generally TiN, and the metal hard mask layer 107 is also represented by TiN-MHM in fig. 1A.
And step five, opening the metal hard mask layer 107 of the groove forming area corresponding to the copper interconnection line through the photoetching and etching process, and then forming a groove.
In the dual damascene process, a structure which is provided with an opening of a through hole and a groove at the same time can be formed by combining the forming process of the through hole.
And step six, filling metal in the through hole and the groove, wherein the step comprises the following steps:
a barrier layer 108 is formed, the barrier layer 108 typically being a stack of a TaN layer and a Ta layer.
A copper seed layer (not shown) is formed, on which a copper layer 109 is formed by electroplating.
In fig. 1A, copper layer 109 needs to fill both the trench and the via opening and will extend to the surface outside the via opening and trench. As technology nodes shrink, the difficulty of filling the via openings and trenches with copper layer 109 increases, and as technology nodes are below 7nm, via openings and trenches cannot be filled well.
And step seven, performing Chemical Mechanical Polishing (CMP) on the copper. As shown in fig. 1B, the low K dielectric layer 104 is stopped after the copper CMP.
Step eight, forming a cobalt layer 110 covering the surface of the copper layer 109 to improve the Electron Mobility (EM) performance of copper.
In the existing method, the hole filling (gap fill) capability of the copper interconnection line has great challenge, defects (defects) and Cu holes (void) are generated to cause the reliability problem, and the poor hole filling causes the resistance (Rc) to be higher. Therefore, if the rear-end copper wire process method of the technology node below 7nm is formed by using the traditional existing method, the huge challenge of copper hole filling capacity is encountered, not only the defect problem but also the problems of high derivative Rc, EM … and the like exist, so that the development period is prolonged, and the whole development progress is influenced.
Disclosure of Invention
The technical problem to be solved by the invention is to provide a manufacturing method of a copper interconnection line, which can eliminate the problem of copper hole filling, can ensure that the integrity of the copper interconnection line is very good, can reduce the on-resistance and can be well suitable for technical nodes below 7 nm.
In order to solve the above technical problems, the method for manufacturing the copper interconnection line provided by the invention comprises the following steps:
providing a front layer film with a flat surface, forming a barrier layer and a copper seed crystal layer on the front layer film, and electroplating on the copper seed crystal layer to form a copper layer.
And secondly, etching the copper layer, the copper seed crystal layer and the barrier layer in the selected area by a copper reactive ion etching process, and forming a copper interconnection line by overlapping the barrier layer, the copper seed crystal layer and the copper layer which are not etched.
And step three, forming a cobalt layer to coat the top surface and the side surface of the copper interconnection line.
And step four, filling an interlayer film between the copper interconnection lines.
In a further improvement, the front layer film is a previous interlayer film, and the front layer film is formed on the semiconductor substrate.
In a further refinement, the semiconductor substrate comprises a silicon substrate.
In a further improvement, the previous interlayer film is a metal front interlayer film, and a contact hole is formed in the metal front interlayer film.
In a further improvement, a semiconductor device is formed on the semiconductor substrate.
In a further refinement, the barrier layer comprises a stack of layers of TaN and Ta.
In a further improvement, the TaN layer is formed by a Physical Vapor Deposition (PVD) process, and the Ta layer is formed by a PVD process.
In a further improvement, the copper seed layer is formed by a PVD process.
In a further improvement, the selected area is defined in step two by a photolithography process.
In a further refinement, the lithography process employs Extreme Ultraviolet (EUV) lithography.
The further improvement is that the step four comprises the following sub-steps:
and depositing the interlayer film, wherein the interlayer film is filled between the copper interconnection lines and extends to the surface of the copper interconnection lines.
Performing CMP to remove the interlayer film on the surface of the copper interconnect lines and to level the interlayer film between the copper interconnect lines and the surface of the copper interconnect lines.
In a further refinement, the deposition process for the interlayer film employs a Flowable Chemical Vapor Deposition (FCVD) process.
In a further improvement, the technology nodes of the semiconductor device include 16nm and 7nm or less.
In a further improvement, in the third step, the cobalt layer is formed on the top surface and the side surface of the copper interconnection line by using a selective formation process.
In a further refinement, said selective formation process of said cobalt layer comprises CVD.
In a further improvement, the cobalt layer is removed from the top surface of the copper interconnect line after CMP of the interlayer film is completed.
The copper interconnection line is formed by etching a copper reactive ion etching process on the basis of a copper layer formed on a flat surface, and compared with the existing Damascus process, the copper interconnection line does not need a copper hole filling process, so that the defect that the copper can not be well filled in a groove of the copper interconnection line when the technical node is smaller, such as below 7nm, can be avoided.
Meanwhile, the copper layer is formed on a plane, the integrity is very good, and the on-resistance can be reduced.
The copper interconnection line can well protect the cobalt layer, thereby reducing the Electric Mobility (EM) of copper and improving the reliability.
The interlayer film between the copper interconnection lines can be realized by an FCVD process, the FCVD pore filling capability is very good, and the interlayer film with high structural strength can be obtained by utilizing the FCVD characteristic.
The single process of the invention is simplified, and the development speed can be improved.
The invention can be well applied to the technical nodes below 7 nm.
Drawings
The invention will be described in further detail with reference to the following detailed description and accompanying drawings:
FIGS. 1A-1C are schematic views of device structures in steps of a conventional damascene process;
FIG. 2 is a flow chart of a method of fabricating a copper interconnect line in accordance with an embodiment of the present invention;
fig. 3A to 3E are schematic views of device structures in the steps of the method for manufacturing the copper interconnect line according to the embodiment of the present invention.
Detailed Description
Fig. 2 is a flowchart of a method of manufacturing a copper interconnect line according to an embodiment of the present invention; fig. 3A to 3E are schematic views of device structures in steps of a method for manufacturing a copper interconnect according to an embodiment of the present invention; the manufacturing method of the copper interconnection line comprises the following steps:
step one, as shown in fig. 3A, a front layer film 1 having a flat surface is provided, a barrier layer 2 and a copper seed layer (not shown) are formed on the front layer film 1, and a copper layer 3 is formed on the copper seed layer by electroplating.
In the embodiment of the present invention, the front layer film 1 is a previous interlayer film, and the front layer film 1 is formed on a semiconductor substrate. For example: the former interlayer film is a metal front interlayer film (PMD) in which a contact hole is formed.
The semiconductor substrate includes a silicon substrate. A semiconductor device is formed on the semiconductor substrate.
In the embodiment of the invention, the technical nodes of the semiconductor device comprise 16nm and below 7nm, namely the method provided by the embodiment of the invention can be suitable for the technical nodes below 7nm, and the existing Damascus process cannot realize good copper filling in the technical nodes below 7 nm.
The barrier layer 2 comprises a stack of layers of TaN and Ta.
The TaN layer is formed using a PVD process, such as a sputtering process, and the Ta layer is formed using a PVD process, such as a sputtering process.
The copper seed crystal layer is formed by adopting a PVD process.
As can be seen from fig. 3A, the copper layer 3 does not need to be pore-filled and the integrity is very good.
And secondly, as shown in fig. 3B, etching the copper layer 3, the copper seed layer and the barrier layer 2 in the selected area by a copper reactive ion etching process, and overlapping the un-etched barrier layer 2, the copper seed layer and the copper layer 3 to form a copper interconnection line.
In an embodiment of the present invention, the selected region is defined by a photolithography process. The photoetching process adopts EUV photoetching.
And step three, as shown in fig. 3C, forming a cobalt layer 4 to coat the top surface and the side surface of the copper interconnection line.
In the embodiment of the present invention, the cobalt layer 4 is formed on the top surface and the side surface of the copper interconnection line by using a selective formation process.
The selective formation process of the cobalt layer 4 includes CVD.
Step four, as shown in fig. 3E, an interlayer film 5 is filled between the copper interconnection lines.
The fourth step comprises the following sub-steps:
as shown in fig. 3D, the deposition of the interlayer film 5 is performed, and the interlayer film 5 is filled between the copper interconnect lines and extends onto the surface of the copper interconnect lines. Preferably, the deposition process of the interlayer film 5 adopts an FCVD process. FCVD is excellent in pore-filling ability, and an oxide layer having high structural strength can be obtained as the interlayer film 5 by utilizing the FCVD characteristic.
As shown in fig. 3E, CMP is performed to remove the interlayer film 5 on the surface of the copper interconnect lines and to level the interlayer film 5 between the copper interconnect lines and the surface of the copper interconnect lines.
After the CMP of the interlayer film 5 is completed, the cobalt layer 4 of the top surface of the copper interconnect line is removed.
The copper interconnection line is formed by etching through a copper reactive ion etching process on the basis of the copper layer 3 formed on the flat surface, and compared with the existing Damascus process, the copper interconnection line does not need a copper hole filling process, so that the defect that the copper can not be well filled in a groove of the copper interconnection line when the technical node is smaller, such as below 7nm, can be avoided.
Meanwhile, the copper layer 3 of the embodiment of the invention is formed on a plane, the integrity is very good, and the on-resistance can be reduced.
The copper interconnection line provided by the embodiment of the invention can well protect the cobalt layer 4, so that the Electric Mobility (EM) of copper can be reduced, and the reliability can be improved.
The interlayer film 5 between the copper interconnection lines in the embodiment of the invention can be realized by an FCVD process, the FCVD hole filling capability is very good, and the interlayer film 5 with high structural strength can be obtained by utilizing the FCVD characteristic.
The single process of the embodiment of the invention is simplified, and the development speed can be improved.
The embodiment of the invention can be well applied to the technical nodes below 7 nm.
The present invention has been described in detail with reference to the specific embodiments, but these are not to be construed as limiting the invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.

Claims (16)

1. A method for manufacturing a copper interconnection line is characterized by comprising the following steps:
providing a front layer film with a flat surface, forming a barrier layer and a copper seed crystal layer on the front layer film, and electroplating on the copper seed crystal layer to form a copper layer;
etching the copper layer, the copper seed crystal layer and the barrier layer in the selected area by a copper reactive ion etching process, and forming a copper interconnection line by overlapping the barrier layer, the copper seed crystal layer and the copper layer which are not etched;
forming a cobalt layer to coat the top surface and the side surface of the copper interconnection line;
and step four, filling an interlayer film between the copper interconnection lines.
2. The method of manufacturing a copper interconnect line according to claim 1, wherein: the front layer film is a previous interlayer film and is formed on the semiconductor substrate.
3. The method of manufacturing a copper interconnect line according to claim 2, wherein: the semiconductor substrate includes a silicon substrate.
4. The method of manufacturing a copper interconnect line according to claim 2, wherein: the former interlayer film is a metal front interlayer film, and a contact hole is formed in the metal front interlayer film.
5. The method of manufacturing a copper interconnect line according to claim 2, wherein: a semiconductor device is formed on the semiconductor substrate.
6. The method of manufacturing a copper interconnect line according to claim 1, wherein: the barrier layer comprises a stack of a TaN layer and a Ta layer.
7. The method of manufacturing a copper interconnect line according to claim 6, wherein: the TaN layer is formed by adopting a PVD process, and the Ta layer is formed by adopting a PVD process.
8. The method of manufacturing a copper interconnect line according to claim 1, wherein: the copper seed crystal layer is formed by adopting a PVD process.
9. The method of manufacturing a copper interconnect line according to claim 1, wherein: and step two, defining the selected area through a photoetching process.
10. The method for manufacturing a copper interconnect according to claim 9, wherein: the photoetching process adopts EUV photoetching.
11. The method of manufacturing a copper interconnect line according to claim 1, wherein: the fourth step comprises the following sub-steps:
performing deposition of the interlayer film, the interlayer film being filled between the copper interconnection lines and extending onto surfaces of the copper interconnection lines;
performing CMP to remove the interlayer film on the surface of the copper interconnect lines and to level the interlayer film between the copper interconnect lines and the surface of the copper interconnect lines.
12. The method for manufacturing a copper interconnect according to claim 11, wherein: the deposition process of the interlayer film adopts an FCVD process.
13. The method of manufacturing a copper interconnect line according to claim 5, wherein: the technology nodes of the semiconductor device include 16nm and 7nm or less.
14. The method of manufacturing a copper interconnect line according to claim 1, wherein: and in the third step, the cobalt layer is formed on the top surface and the side surface of the copper interconnection line by adopting a selective forming process.
15. The method for manufacturing a copper interconnect according to claim 14, wherein: the selective formation process of the cobalt layer includes CVD.
16. The method for manufacturing a copper interconnect according to claim 11, wherein: after the CMP of the interlayer film is completed, the cobalt layer of the top surface of the copper interconnect line is removed.
CN202011214868.3A 2020-11-04 2020-11-04 Method for manufacturing copper interconnection line Pending CN112382608A (en)

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Application Number Priority Date Filing Date Title
CN202011214868.3A CN112382608A (en) 2020-11-04 2020-11-04 Method for manufacturing copper interconnection line

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Application Number Priority Date Filing Date Title
CN202011214868.3A CN112382608A (en) 2020-11-04 2020-11-04 Method for manufacturing copper interconnection line

Publications (1)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101164121A (en) * 2005-03-09 2008-04-16 兰姆研究有限公司 Plasma oxidation and removal of oxidized material
TW201419446A (en) * 2012-11-05 2014-05-16 Taiwan Semiconductor Mfg Integrated circuit device having a copper interconnect

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101164121A (en) * 2005-03-09 2008-04-16 兰姆研究有限公司 Plasma oxidation and removal of oxidized material
TW201419446A (en) * 2012-11-05 2014-05-16 Taiwan Semiconductor Mfg Integrated circuit device having a copper interconnect

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