CN113380761A - Semiconductor device and method for manufacturing the same - Google Patents

Semiconductor device and method for manufacturing the same Download PDF

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Publication number
CN113380761A
CN113380761A CN202110525480.3A CN202110525480A CN113380761A CN 113380761 A CN113380761 A CN 113380761A CN 202110525480 A CN202110525480 A CN 202110525480A CN 113380761 A CN113380761 A CN 113380761A
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groove
metal layer
layer
barrier layer
forming
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孙祥烈
许静
罗军
赵超
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Institute of Microelectronics of CAS
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Institute of Microelectronics of CAS
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5283—Cross-sectional geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76847—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned within the main fill metal
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53242—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a noble metal, e.g. gold

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  • Condensed Matter Physics & Semiconductors (AREA)
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  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The invention discloses a semiconductor device and a preparation method thereof, wherein the semiconductor device comprises: a dielectric layer; the first groove is positioned in the medium layer; the second groove is positioned in the dielectric layer, the line width of the first groove is smaller than the preset width, and the line width of the second groove is larger than the preset width; the first metal layer is positioned in the first groove and at the bottom and the side wall of the second groove; and the second metal layer is positioned in the second groove. The technical effect of meeting the performance requirements of both the large-size interconnection structure and the small-size interconnection structure is achieved.

Description

Semiconductor device and method for manufacturing the same
Technical Field
The invention relates to the field of semiconductors, in particular to a semiconductor device and a preparation method thereof.
Background
The integrated circuit includes many connected structures, and typically, a copper interconnection structure is used, but the present inventors have found that the above-mentioned techniques have at least the following technical problems: with the continuous reduction of the size of the device, the resistance of the copper interconnection structure is increased sharply, the problem of electromigration reliability is aggravated, and the traditional copper interconnection technology is difficult to meet the requirement of the device performance.
Disclosure of Invention
The embodiment of the application provides a semiconductor device and a preparation method thereof, solves the technical problem that in the prior art, the performance requirement of a large-size interconnection structure and the performance requirement of a small-size interconnection structure cannot be considered at the same time, and achieves the technical effect of meeting the performance requirements of both the large-size interconnection structure and the small-size interconnection structure.
The present invention provides a semiconductor device including: a dielectric layer; the first groove is positioned in the medium layer; the second groove is positioned in the medium layer, the line width of the first groove is smaller than the preset width, and the line width of the second groove is larger than the preset width; the first metal layer is positioned in the first groove and the bottom and the side wall of the second groove; and the second metal layer is positioned in the second groove.
The application provides the following technical scheme through an embodiment of the application: the preset width is between 20nm and 40 nm.
The application provides the following technical scheme through an embodiment of the application: the electromigration reliability of the first metal layer is superior to that of the second metal layer, and the resistivity of the second metal layer is smaller than that of the first metal layer.
The application provides the following technical scheme through an embodiment of the application: the material of the first metal layer comprises ruthenium or cobalt, and the material of the second metal layer comprises copper.
The application provides the following technical scheme through an embodiment of the application: and the barrier layer is positioned at the bottom and the side wall of the first groove and the bottom and the side wall of the second groove, and the material of the barrier layer comprises tantalum nitride.
The invention also provides a preparation method of the semiconductor device, which comprises the following steps: providing a dielectric layer, and forming a first groove and a second groove in the dielectric layer, wherein the line width of the first groove is smaller than a preset width, and the line width of the second groove is larger than the preset width; forming a first metal layer in the first groove and the bottom and the side wall of the second groove; and forming a second metal layer in the second groove.
The application provides the following technical scheme through an embodiment of the application: the preset width is between 20nm and 40 nm.
The application provides the following technical scheme through an embodiment of the application: the electromigration reliability of the first metal layer is superior to that of the second metal layer, and the resistivity of the second metal layer is smaller than that of the first metal layer.
The application provides the following technical scheme through an embodiment of the application: the material of the first metal layer comprises ruthenium or cobalt, and the material of the second metal layer comprises copper.
The application provides the following technical scheme through an embodiment of the application: before forming the first metal layer and the second metal layer after forming the first groove and the second groove, further comprising: forming a barrier layer on the bottom and the side wall of the first groove and the bottom and the side wall of the second groove; after the forming of the barrier layer, the method further comprises the following steps: and carrying out argon plasma bombardment treatment on the barrier layer.
The application provides the following technical scheme through an embodiment of the application: before forming the first metal layer and the second metal layer after forming the first groove and the second groove, further comprising: and forming a barrier layer on the bottom and the side wall of the first groove and the bottom and the side wall of the second groove, wherein the barrier layer is made of tantalum nitride and comprises a first barrier layer and a second barrier layer positioned on the surface of the first barrier layer, the process for forming the first barrier layer comprises an atomic layer deposition process, and the process for forming the second barrier layer comprises a physical vapor deposition process.
One or more technical solutions provided in the embodiments of the present application have at least the following technical effects or advantages:
1. the line width of the first groove is smaller than that of the second groove; the first metal layer is positioned in the first groove; the second metal layer is located in the second groove, so that the technical problem that performance requirements of a large-size interconnection structure and performance requirements of a small-size interconnection structure cannot be met in the prior art is effectively solved, and the technical effects that the small-size interconnection structure can have the performance of the first metal layer and the large-size interconnection structure can have the performance of the second metal layer are further achieved.
2. Forming a first metal layer in the first groove due to the fact that the line width of the first groove is smaller than that of the second groove; the technical means of forming the second metal layer in the second groove effectively solves the technical problem that the performance requirements of the large-size interconnection structure and the small-size interconnection structure in the prior art cannot be considered at the same time, and further achieves the technical effects that the small-size interconnection structure can have the performance of the first metal layer, and the large-size interconnection structure can have the performance of the second metal layer.
3. The material of the first metal layer comprises ruthenium or cobalt, and the material of the second metal layer comprises copper, so that the large-size interconnection structure and the small-size interconnection structure ensure the electromigration reliability and resistance.
4. The first metal layer is also located at the bottom and the side wall of the second groove, and when the first metal layer is formed in the first groove, the method further comprises the following steps: and forming a first metal layer at the bottom and the side wall of the second groove, wherein the first metal layer positioned in the second groove can be used as a barrier layer of the second metal layer, so that the occupation ratio of the barrier layer can be reduced, the resistance of the communication structure can be reduced, and the first metal layer positioned in the second groove can also be used as a seed layer of the second metal layer, so that the seed-layer-free electroplating of the second metal layer can be realized.
5. The process for forming the first barrier layer comprises an atomic layer deposition process, the process for forming the second barrier layer comprises a physical vapor deposition process, the continuity of the first barrier layer and the second barrier layer can be improved, and the resistance of the barrier layers can be reduced by forming the second barrier layer through the physical vapor deposition process.
6. After the barrier layer is formed, the method further comprises the following steps: and the barrier layer is subjected to argon plasma bombardment treatment, so that the nucleation rate of the metal layer can be improved, the thickness of the barrier layer can be reduced, and the connection resistance is reduced.
7. Before forming the second metal layer after forming the first metal layer, further comprising: the first metal layer is subjected to argon plasma bombardment treatment, so that the adhesion between the first metal layer and the second metal layer can be improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on the drawings without creative efforts.
Fig. 1 is a flowchart of a method of manufacturing a semiconductor device of the present invention.
FIGS. 2 to 7 are schematic structural views showing steps of a method for manufacturing a semiconductor device according to the present invention; fig. 7 is a schematic structural diagram of the semiconductor device of the present invention.
In the figure: 10. a dielectric layer; 201. a first groove; 202. a second groove; 301. a first barrier layer; 302. a second barrier layer; 401. a first metal layer; 402. a second metal layer.
Detailed Description
Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is illustrative only and is not intended to limit the scope of the present disclosure. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present disclosure.
Various structural schematics according to embodiments of the present disclosure are shown in the figures. The figures are not drawn to scale, wherein certain details are exaggerated and possibly omitted for clarity of presentation. The shapes of various regions, layers, and relative sizes and positional relationships therebetween shown in the drawings are merely exemplary, and deviations may occur in practice due to manufacturing tolerances or technical limitations, and a person skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions, as actually required.
In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present. In addition, if a layer/element is "on" another layer/element in one orientation, then that layer/element may be "under" the other layer/element when the orientation is reversed.
The inventors of the present application have discovered that as device dimensions continue to shrink, copper metal resistance increases dramatically for small interconnect structures due to electron interface scattering and surface scattering effects, as well as size effects; as dimensions decrease, electromigration reliability of copper increases; in order to prevent copper diffusion, a barrier layer with a certain thickness is needed, the resistance of the interconnection structure is further increased, and copper metal cannot meet the performance requirement of the small-size interconnection structure; but copper has a low resistivity and is essential for performance of large size interconnect structures. Generally, the same metal is filled in the communication structure in the same dielectric layer, and the requirements of the small-size interconnection structure and the large-size interconnection structure on the reliability and the resistivity of electromigration cannot be met.
Example one
As shown in fig. 1, there is provided a method of manufacturing a semiconductor device, including: providing a dielectric layer 10, and forming a first groove 201 and a second groove 202 in the dielectric layer 10, wherein the line width of the first groove 201 is smaller than that of the second groove 202; forming a first metal layer 401 in the first groove 201; a second metal layer 402 is formed in the second recess 202.
S10: a dielectric layer 10 is provided, and a first groove 201 and a second groove 202 are formed in the dielectric layer 10, wherein the line width of the first groove 201 is smaller than the line width of the second groove 202, as shown in fig. 2.
In one embodiment, the first recess 201 extends through the dielectric layer 10 and the second recess 202 extends through the dielectric layer 10.
In one embodiment, dielectric layer 10 comprises silicon dioxide and other low dielectric constant materials, and the like.
In one embodiment, a photolithography process is used to form the first recess 201 and the second recess 202 in the dielectric layer 10.
In one embodiment, the line width of the first groove 201 is smaller than the predetermined width, and the line width of the second groove 202 is larger than the predetermined width.
In one embodiment, the predetermined width is between 20nm and 40nm, for example, the predetermined width may be 20nm, 25nm, 30nm, 35nm, 40 nm.
In one embodiment, the line width of the first groove 201 is less than 30nm, for example, the line width of the first groove 201 may be 7nm, 10nm, 15nm, 20nm, 28nm, and the line width of the second groove 202 is greater than 30nm, for example, the line width of the second groove 202 may be 31nm, 35nm, 40nm, 50nm, 60 nm.
In one embodiment, after step S10 and before step S20, the method further comprises:
s11: a barrier layer is formed on the bottom and sidewalls of the first recess 201 and the bottom and sidewalls of the second recess 202. In one embodiment, step S11 further includes: a barrier layer is formed on the upper surface of the dielectric layer 10.
In one embodiment, step S11 includes:
s111: forming a first barrier layer 301 on the bottom and sidewalls of the first recess 201 and the bottom and sidewalls of the second recess 202, as shown in fig. 3;
s112: a second barrier layer is formed on the surface of the first barrier layer 301, as shown in fig. 4.
In one embodiment, first barrier layer 301 comprises tantalum or tantalum nitride, etc., and second barrier layer 302 comprises tantalum or tantalum nitride, etc.
In one embodiment, the process of forming the first barrier layer 301 comprises an atomic layer deposition process and the process of forming the second barrier layer 302 comprises a physical vapor deposition process.
In one embodiment, the thickness of the first barrier layer 301 is between 5 angstroms and 30 angstroms, for example, the thickness of the first barrier layer 301 may be 5 angstroms, 8 angstroms, 10 angstroms, 20 angstroms, and 30 angstroms, and the thickness of the second barrier layer 302 may be between 5 angstroms and 30 angstroms, for example, the thickness of the second barrier layer 302 may be 5 angstroms, 8 angstroms, 10 angstroms, 20 angstroms, and 30 angstroms.
In one embodiment, after step S11, the method further includes:
s12: and performing argon plasma bombardment treatment on the barrier layer.
S20: a first metal layer 401 is formed in the first recess 201, as shown in fig. 5.
In one embodiment, step S20 further includes: a first metal layer 401 is formed on the bottom and sidewalls of the second recess 202.
In one embodiment, step S20 further includes: a first metal layer 401 is formed on the dielectric layer 10.
In one embodiment, step S20 further includes: a first metal layer 401 is formed on the upper surface of the barrier layer.
In one embodiment, the material of the first metal layer 401 includes ruthenium, cobalt, or the like.
The ruthenium metal has small mean free path, can reduce size effect, has high melting point and good electromigration reliability.
In one embodiment, after step S20 and before step S30, the method further comprises:
s21: the first metal layer 401 is subjected to argon plasma bombardment treatment.
S30: a second metal layer 402 is formed in the second recess 202, as shown in fig. 6.
In one embodiment, step S30 further includes: a second metal layer 402 is formed on the dielectric layer 10.
In one embodiment, step S30 further includes: a second metal layer 402 is formed on the upper surface of the first metal layer 401.
In one embodiment, the material of second metal layer 402 comprises copper.
In one embodiment, the process of forming the first metal layer 401 includes a physical vapor deposition, chemical vapor deposition, or atomic layer deposition process.
In one embodiment, the process of forming second metal layer 402 includes an electroplating process.
In one embodiment, the electromigration reliability of the first metal layer 401 is better than the electromigration reliability of the second metal layer 402, the resistivity of the second metal layer 402 being less than the resistivity of the first metal layer 401.
In one embodiment, after step S30, the method further includes:
s40: the barrier layer, the first metal layer 401 and the second metal layer 402 on the dielectric layer 10 are removed as shown in fig. 7.
In one embodiment, the barrier layer, the first metal layer 401 and the second metal layer 402 on the dielectric layer 10 are removed using a chemical mechanical polishing process.
Example two
As shown in fig. 7, there is provided a semiconductor device including: a dielectric layer 10; a first groove 201 located in the dielectric layer 10; the second groove 202 is positioned in the dielectric layer 10, and the line width of the first groove 201 is smaller than that of the second groove 202; a first metal layer 401 located in the first groove 201; and a second metal layer 402 located in the second recess 202.
In one embodiment, the line width of the first groove 201 is smaller than the predetermined width, and the line width of the second groove 202 is larger than the predetermined width.
In one embodiment, the predetermined width is between 20nm and 40nm, for example, the predetermined width may be 20nm, 25nm, 30nm, 35nm, 40 nm.
In one embodiment, the line width of the first groove 201 is less than 30nm, for example, the line width of the first groove 201 may be 7nm, 10nm, 15nm, 20nm, 28nm, and the line width of the second groove 202 is greater than 30nm, for example, the line width of the second groove 202 may be 31nm, 35nm, 40nm, 50nm, 60 nm.
In one embodiment, the first metal layer 401 is also located at the bottom and sidewalls of the second recess 202.
In one embodiment, the electromigration reliability of the first metal layer 401 is better than the electromigration reliability of the second metal layer 402, the resistivity of the second metal layer 402 being less than the resistivity of the first metal layer 401.
In one embodiment, the material of the first metal layer 401 includes ruthenium, cobalt, or the like, and the material of the second metal layer 402 includes copper.
In one embodiment, further comprising: and a barrier layer at the bottom and sidewalls of the first recess 201 and the bottom and sidewalls of the second recess 202.
In one embodiment, the barrier layer includes a first barrier layer 301 and a second barrier layer 302 on a surface of the first barrier layer 301.
In one embodiment, first barrier layer 301 comprises tantalum or tantalum nitride, etc., and second barrier layer 302 comprises tantalum or tantalum nitride, etc.
In one embodiment, the thickness of the first barrier layer 301 is between 5 angstroms and 30 angstroms, for example, the thickness of the first barrier layer 301 may be 5 angstroms, 8 angstroms, 10 angstroms, 20 angstroms, and 30 angstroms, and the thickness of the second barrier layer 302 may be between 5 angstroms and 30 angstroms, for example, the thickness of the second barrier layer 302 may be 5 angstroms, 8 angstroms, 10 angstroms, 20 angstroms, and 30 angstroms.
The technical scheme in the embodiment of the application at least has the following technical effects or advantages:
1. the line width of the first groove 201 is smaller than that of the second groove 202; a first metal layer 401 located in the first groove 201; the second metal layer 402 is located in the second groove 202, so that the technical problem that performance requirements of a large-size interconnection structure and performance requirements of a small-size interconnection structure in the prior art cannot be met at the same time is effectively solved, and the technical effects that the small-size interconnection structure can have the performance of the first metal layer 401, and the large-size interconnection structure can have the performance of the second metal layer 402 are further achieved.
2. As the line width of the first groove 201 is smaller than the line width of the second groove 202, a first metal layer 401 is formed in the first groove 201; the technical means for forming the second metal layer 402 in the second groove 202 effectively solves the technical problem that the performance requirements of the large-size interconnection structure and the small-size interconnection structure in the prior art cannot be considered at the same time, thereby achieving the technical effects that the small-size interconnection structure can have the performance of the first metal layer 401, and the large-size interconnection structure can have the performance of the second metal layer 402.
3. The material of the first metal layer 401 includes ruthenium or cobalt, etc., and the material of the second metal layer 402 includes copper, so that the electromigration reliability and resistance are ensured by both the large-size interconnect structure and the small-size interconnect structure.
4. The first metal layer 401 is further located at the bottom and the sidewall of the second groove 202, and when the first metal layer 401 is formed in the first groove 201, the method further includes: the first metal layer 401 is formed on the bottom and the side wall of the second groove 202, the first metal layer 401 located in the second groove 202 can be used as a barrier layer of the second metal layer 402, so that the occupation ratio of the barrier layer can be reduced, the resistance of the communication structure can be reduced, the first metal layer 401 located in the second groove 202 can also be used as a seed layer of the second metal layer 402, and the seed-layer-free electroplating of the second metal layer 402 can be realized.
5. The process for forming the first barrier layer 301 includes an atomic layer deposition process, the process for forming the second barrier layer 302 includes a physical vapor deposition process, the continuity of the first barrier layer 301 and the second barrier layer 302 can be improved, the resistivity of the atomic layer deposited tantalum nitride barrier layer is higher than that of the physical vapor deposition tantalum nitride, and the resistance of the barrier layer can be reduced by forming the second barrier layer 302 through the physical vapor deposition process.
6. After the barrier layer is formed, the method further comprises the following steps: and the barrier layer is subjected to argon plasma bombardment treatment, so that the nucleation rate of the metal layer can be improved, the thickness of the barrier layer can be reduced, and the connection resistance is reduced.
7. After forming the first metal layer 401 and before forming the second metal layer 402, the method further includes: the adhesion between the first metal layer 401 and the second metal layer 402 can be improved by performing the argon plasma bombardment treatment on the first metal layer 401.
In the above description, the technical details of patterning, etching, and the like of each layer are not described in detail. It will be appreciated by those skilled in the art that layers, regions, etc. of the desired shape may be formed by various technical means. In addition, in order to form the same structure, those skilled in the art can also design a method which is not exactly the same as the method described above. In addition, although the embodiments are described separately above, this does not mean that the measures in the embodiments cannot be used in advantageous combination.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the invention.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.

Claims (11)

1. A semiconductor device, comprising:
a dielectric layer;
the first groove is positioned in the medium layer;
the second groove is positioned in the medium layer, the line width of the first groove is smaller than the preset width, and the line width of the second groove is larger than the preset width;
the first metal layer is positioned in the first groove and the bottom and the side wall of the second groove;
and the second metal layer is positioned in the second groove.
2. The semiconductor device according to claim 1, wherein the predetermined width is between 20nm and 40 nm.
3. The semiconductor device of claim 1, wherein the electromigration reliability of the first metal layer is better than the electromigration reliability of the second metal layer, the resistivity of the second metal layer being less than the resistivity of the first metal layer.
4. The semiconductor device according to claim 1, wherein a material of the first metal layer comprises ruthenium or cobalt, and a material of the second metal layer comprises copper.
5. The semiconductor device according to claim 1, further comprising: and the barrier layer is positioned at the bottom and the side wall of the first groove and the bottom and the side wall of the second groove, and the material of the barrier layer comprises tantalum nitride.
6. A method of manufacturing a semiconductor device, comprising:
providing a dielectric layer, and forming a first groove and a second groove in the dielectric layer, wherein the line width of the first groove is smaller than a preset width, and the line width of the second groove is larger than the preset width;
forming a first metal layer in the first groove and the bottom and the side wall of the second groove;
and forming a second metal layer in the second groove.
7. The method according to claim 6, wherein the predetermined width is between 20nm and 40 nm.
8. The method of manufacturing a semiconductor device according to claim 6, wherein the electromigration reliability of the first metal layer is superior to that of the second metal layer, and the resistivity of the second metal layer is smaller than that of the first metal layer.
9. The method for manufacturing a semiconductor device according to claim 6, wherein a material of the first metal layer comprises ruthenium or cobalt, and a material of the second metal layer comprises copper.
10. The method for manufacturing a semiconductor device according to claim 6, further comprising, before forming the first metal layer and the second metal layer after forming the first groove and the second groove: forming a barrier layer on the bottom and the side wall of the first groove and the bottom and the side wall of the second groove; after the forming of the barrier layer, the method further comprises the following steps: and carrying out argon plasma bombardment treatment on the barrier layer.
11. The method for manufacturing a semiconductor device according to claim 6, further comprising, before forming the first metal layer and the second metal layer after forming the first groove and the second groove: and forming a barrier layer on the bottom and the side wall of the first groove and the bottom and the side wall of the second groove, wherein the barrier layer is made of tantalum nitride and comprises a first barrier layer and a second barrier layer positioned on the surface of the first barrier layer, the process for forming the first barrier layer comprises an atomic layer deposition process, and the process for forming the second barrier layer comprises a physical vapor deposition process.
CN202110525480.3A 2021-05-13 2021-05-13 Semiconductor device and method for manufacturing the same Pending CN113380761A (en)

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Application publication date: 20210910