CN112380074B - Connector processing method and device, processing module and electronic equipment - Google Patents
Connector processing method and device, processing module and electronic equipment Download PDFInfo
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Abstract
The application provides a connector processing method, a connector processing device, a processing module and electronic equipment. The method comprises the following steps: acquiring a first pin signal of a first type pin and a second pin signal of a second type pin; in the current detection period, when any one of the first pin signal and the second pin signal is changed at first, updating the first pin signal and the second pin signal in a first appointed time after the first change according to the pin signals of the first type pin and the second type pin at a target time, so as to obtain the updated first pin signal and the updated second pin signal, wherein the target time comprises a time before the first change time and spaced by a second appointed time. In the scheme, the hot plug interrupt triggered by the fluctuation of the pin signal can be avoided, so that the processing flow is simplified, and the accuracy of detecting the type of the hardware module is improved.
Description
Technical Field
The present invention relates to the field of digital signal processing technologies, and in particular, to a connector processing method, a device, a processing module, and an electronic apparatus.
Background
In the computer field, there are various types of connectors for connecting other devices or modules. For the connector which can be compatibly connected with hardware modules of different types, if the connector has long pins and short pins at the same time, during the process of plugging or unplugging the hardware modules on the connector, the hot plug interruption is easily caused by the long pins and the short pins to increase the processing flow, thereby influencing the normal operation of the equipment.
Disclosure of Invention
The application provides a connector processing method, a device, a processing module and electronic equipment, which can simplify the processing flow when judging the type of an inserted or pulled hardware module, and are beneficial to improving the accuracy of detecting the type of the hardware module.
In order to achieve the above object, the technical solution provided by the embodiments of the present application is as follows:
In a first aspect, an embodiment of the present application provides a connector processing method, applied to a processing module, where the processing module is configured to connect with a connector, the connector includes a first type pin and a second type pin, and a length of the first type pin is greater than a length of the second type pin, and the method includes:
acquiring a first pin signal of the first type pin and a second pin signal of the second type pin;
In the current detection period, when any one of the first pin signal and the second pin signal is changed first, updating the first pin signal and the second pin signal in a first specified duration after the first change according to the pin signals of the first type pin and the second type pin at a target time, so as to obtain updated first pin signal and second pin signal, wherein the target time comprises a time before the first change time and a time with a second specified duration spaced from the first change time.
In the above embodiment, the first specified duration is generally slightly longer than the duration of the plugging or unplugging hardware module, and the first specified duration after the pin signal is first changed generally includes the duration used for the plugging or unplugging action. By resetting the pin signals of the first type of pins and the second type of pins in the first designated time after the pin signals are changed to the pin signals with the second designated time before the pin signals are changed, false triggering of hot plug interruption caused by fluctuation of the pin signals when the hardware module is plugged or pulled out can be avoided, and subsequent false alarm correction processing flow triggered by the hot plug interruption is avoided, so that the processing flow is simplified, and the accuracy of detecting the type of the hardware module is improved.
With reference to the first aspect, in some optional embodiments, updating the first pin signal and the second pin signal in the first specified duration after the first change according to the pin signals of the first type of pins and the second type of pins at the target time to obtain updated first pin signals and second pin signals includes:
Updating the first pin signal in the first specified time after the first change to the pin signal of the first type pin at the target time, and updating the second pin signal in the first specified time after the first change to the pin signal of the second type pin at the target time.
In the above embodiment, in the current detection period, the first specified period after the change first includes the period during which the hardware module is inserted or pulled out. Therefore, the first pin signal and the second pin signal during the process of inserting or extracting the hardware module can be respectively updated into the pin signals corresponding to one moment before the insertion or extracting, so that misjudgment caused by fluctuation of the signals of the first type pins and the second type pins during the action of inserting or extracting the connector is avoided, and further the accuracy of judgment is improved.
With reference to the first aspect, in some optional embodiments, the connector is configured to connect to a hard disk, where a type of the hard disk includes at least one of SATA, U.2, SAS, and updating the first pin signal in the first specified duration after the first change to a pin signal of the first type of pin at the target time, and updating the second pin signal in the first specified duration after the first change to a pin signal of the second type of pin at the target time includes:
When the pin signals of the first type pins and the second type pins are high-level signals at the target moment, updating the first pin signals and the second pin signals in the first appointed time period after the first change to the high-level signals;
when the pin signals of the first type pins and the second type pins are low-level signals at the target moment, updating the first pin signals and the second pin signals in the first appointed time period after the first change to the low-level signals;
When the pin signal of the first type pin is a low level signal at the target time, and when the pin signal of the second type pin is a high level signal at the target time, updating the first pin signal in the first designated time period after the first change to the low level signal, and updating the second pin signal in the first designated time period after the first change to the high level signal.
In the above embodiment, the pin signal during the insertion or extraction period can be updated by simple logic operation without detecting whether the edge signal of the pin signal belongs to the rising edge or the falling edge, so as to improve the accuracy of the hardware module type detection.
With reference to the first aspect, in some optional embodiments, the method further includes:
and determining the state of the connector or the type of the connected hardware module according to the first pin signal and the second pin signal after the first designated time period is over.
In the above embodiment, after the pin signal during the insertion or extraction period is updated, the post-stage pin signal is used to perform detection and judgment, so that the accuracy of judging the type of the hardware module can be improved.
With reference to the first aspect, in some optional embodiments, the connector is configured to connect to a hard disk, where a type of the hard disk includes at least one of SATA, U.2, SAS, and the method further includes:
After the first specified duration is over, if the first pin signal of the first type of pins is a low level signal and the second pin signal of the second type of pins is a high level signal, outputting an interrupt signal representing a hot plug interrupt.
In the above embodiment, if the type of the hard disk to which the connector is connected is U.2, after the first specified duration is over, the first pin signal of the first type of pin is a low level signal, and the second pin signal of the second type of pin is a high level signal. Therefore, whether the hard disk connected with the connector is the U.2SSD can be accurately judged, so that the hot plug of the U.2SSD can be realized by the interrupt signal of the hot plug interrupt, and the situation that the PCIe hot plug processing flow is triggered by errors caused by reporting the hot plug interrupt when the SATA hard disk is inserted is avoided.
With reference to the first aspect, in some optional embodiments, before obtaining the updated first pin signal and the updated second pin signal, the method further includes:
judging whether the duration of the first pin signal is a first preset signal and the duration of the second pin signal is a second preset signal is smaller than or equal to a first specified duration;
When the duration is less than or equal to the first specified duration, determining a reference time in the duration, wherein the target time is a time before and spaced from a time when the first pin signal or the second pin signal changes by the second specified duration, or a time before and spaced from the reference time by a third specified duration, and the third specified time is greater than the first specified duration.
In the above embodiment, by determining whether the duration of the first pin signal is the first preset signal and the duration of the second pin signal is the second preset signal is less than or equal to the first specified duration, it is beneficial to determine the type of the hardware module plugged or unplugged on the connector. For example, if the connector is used for plugging a u.2ssd or SATA hard disk, if the first pin signal is a low level signal and the duration of the second pin signal being a high level signal is less than or equal to a specified duration, the plugged or unplugged hard disk may be determined to be a SATA hard disk, so as to update the pin signal of the SATA hard disk during plugging.
With reference to the first aspect, in some optional embodiments, when the duration is less than or equal to the first specified duration, determining the reference time in the duration includes:
And when the duration is less than or equal to the first designated duration, determining a starting time of the duration as the reference time or determining an ending time of the duration as the reference time.
In a second aspect, an embodiment of the present application further provides a connector processing device, applied to a processing module, where the processing module is configured to connect with a connector, the connector includes a first type pin and a second type pin, and a length of the first type pin is greater than a length of the second type pin, and the device includes:
The acquisition unit is used for acquiring a first pin signal of the first type pin and a second pin signal of the second type pin;
And the updating unit is used for updating the first pin signal and the second pin signal in a first specified duration after the first change according to the pin signals of the first type pin and the second type pin at a target time when any pin signal in the first pin signal and the second pin signal is changed at first in a current detection period, so as to obtain the updated first pin signal and the updated second pin signal, wherein the target time comprises a time which is before the time of the first change and is longer than the time of the first change by a second specified time interval.
In a third aspect, an embodiment of the present application further provides a processing module, where the processing module includes a memory and a processor that are coupled to each other, and the memory stores a computer program, where the computer program, when executed by the processor, causes the processing module to perform the method described above.
In a fourth aspect, an embodiment of the present application further provides an electronic device, where the electronic device includes a motherboard module and the processing module described above.
In a fifth aspect, embodiments of the present application further provide a computer readable storage medium having a computer program stored therein, which when run on a computer causes the computer to perform the above-described method.
Drawings
In order to more clearly illustrate the technical solution of the embodiments of the present application, the drawings that are required to be used in the embodiments will be briefly described. It is to be understood that the following drawings illustrate only certain embodiments of the application and are therefore not to be considered limiting of its scope, for the person of ordinary skill in the art may admit to other equally relevant drawings without inventive effort.
Fig. 1 is a schematic diagram of a processing module and a connector according to an embodiment of the present application.
Fig. 2 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
Fig. 3 is a flowchart of a connector processing method according to an embodiment of the present application.
Fig. 4 is a schematic diagram of timing signals before and after updating of the first pin signal and the second pin signal according to an embodiment of the present application.
Fig. 5 is a block diagram of a connector processing device according to an embodiment of the present application.
Icon: 10-a processing module; 11-a processor; 12-memory; 20-an electronic device; a 21-motherboard module; a 30-connector; 100-connector processing means; 110-an acquisition unit; 120-updating unit.
Detailed Description
The technical solutions in the embodiments of the present application will be described below with reference to the accompanying drawings in the embodiments of the present application. It should be noted that the terms "first," "second," and the like are used merely to distinguish between descriptions and should not be construed as indicating or implying relative importance.
Applicants have found that in a server or Computer device, the type of hard disk connector of SFF-8639 can be compatible with the type of hard disk (or type of interface to the hard disk) to which it is connected, including but not limited to SATA (SERIAL ADVANCED Technology Attachment, serial advanced technology attachment, an industry standard based serial hardware driver interface) interface, U.2 interface, SAS (SERIAL ATTACHED SCSI, serial SCSI) interface, etc., SCSI refers to a Small Computer system interface, all english being called Small Computer SYSTEM INTERFACE. The Solid state disk (Solid STATE DISK, SSD) of U.2 interfaces can support hot plug, that is, when the server or the computer device detects that the hard disk accessed by the connector is U.2SSD, the hot plug of the U.2SSD can be realized by triggering PCIe hot plug interrupt. Because the interface of the SFF-8639 connector has long and short pins, when the SATA hard disk is inserted, the level signal of the pins is the same as the level signal of the U.2SSD during the insertion or extraction, thereby triggering the misinformation of the interruption of the U.2SSD and further triggering the hot plug flow of PCIe.
In view of the above problems, the applicant of the present application proposes the following examples to solve the above problems. Embodiments of the present application will be described in detail below with reference to the accompanying drawings. The following embodiments and features of the embodiments may be combined with each other without conflict.
Referring to fig. 1, an embodiment of the present application provides a processing module 10, which can be used for connecting with long pins and short pins of a connector 30, and correcting pin signals during the process of plugging and unplugging a hard disk of the connector 30, so as to avoid false triggering of PCIe hot plug processing flow due to fluctuation of the pin signals during the process of plugging and unplugging the hard disk.
The processing module 10 may include a processor 11 and a memory 12. The memory 12 has stored therein a computer program. The computer programs, when executed by the processing module 10, may cause the processing module 10 to perform steps in a connector processing method described below.
Wherein the memory 12 may be integrated with the processor 11 or may exist separately. For example, the processing module 10 may be a CPLD (Complex Programming Logic Device, complex programmable logic device) module, and may include both the processor 11 and the memory 12.
The processing module 10 may be connected to a first type pin (e.g., "IFDET #" pin in fig. 1) and a second type pin (e.g., "PRSNT #" pin in fig. 1) of the connector 30, for collecting and correcting pin signals of the first type pin and pin signals of the second type pin. The first type of pins are longer pins in the interface of the connector 30, and the second type of pins are shorter pins in the interface of the connector 30.
It will be appreciated that the interface of the connector 30 in this embodiment has both long and short pins (or called long and short probes), and the interface of the connector 30 can be connected to a corresponding hardware module, and the connected hardware module can be determined according to the actual type of the connector 30. For example, for the SFF-8639 connector, the connected hardware module is a hard disk. The SFF-8639 connector can be compatible with and connected with SATA hard disks, U.2SSD, SAS and other hard disks.
In the SFF-8639 connector, the first type of pin is a P4 pin, the pin signal of the P4 pin can be called IFDET signal, and the signal can be expressed as IFDET # IFDET signal; the second type of pin is the P10 pin, and the pin signal of the P10 pin may be referred to as a PRSNT signal, and the PRSNT signal may be represented by "prsnt#" and may be seen in fig. 4. The length of the P4 pin is greater than the P10 pin, as is well known to those skilled in the art.
In the present embodiment, the memory 12 may be cured or stored with the connector processing device 100, and the connector processing device 100 may be a software functional module for implementing each step in the connector processing method.
Referring to fig. 2, an embodiment of the present application further provides an electronic device 20, which may include, but is not limited to, a motherboard module 21 and the processing module 10 described above. The main board module 21 is connected to the processing module 10 and may be used for data interaction with the processing module 10. The electronic device 20 may be, but is not limited to, a server, a personal computer, or the like. The motherboard module 21 may be well known to those skilled in the art, and will not be described here.
Referring to fig. 3, the embodiment of the present application further provides a connector processing method, which can be applied to the above processing module 10, and the processing module 10 executes or implements the steps of the method. The method may comprise the steps of:
step S210, a first pin signal of the first type pin and a second pin signal of the second type pin are obtained;
Step S220, in the current detection period, when any one of the first pin signal and the second pin signal changes first, updating the first pin signal and the second pin signal in the first specified duration after the first change according to the pin signals of the first type pin and the second type pin at the target time, so as to obtain updated first pin signal and second pin signal, where the target time includes a time before the first change time and a time spaced from the first change time by a second specified time.
In the above embodiment, the first specified duration is generally slightly longer than the duration of the plugging or unplugging hardware module, and the first specified duration after the pin signal is first changed generally includes the duration used for the plugging or unplugging action. By resetting the pin signals of the first type of pins and the second type of pins in the first designated time after the pin signals are changed to the pin signals with the second designated time before the pin signals are changed, false triggering of hot plug interruption caused by fluctuation of the pin signals when the hardware module is plugged or pulled out can be avoided, and subsequent false alarm correction processing flow triggered by the hot plug interruption is avoided, so that the processing flow is simplified, and the accuracy of detecting the type of the hardware module is improved.
The steps of the method will be described in detail below, as follows:
In step S210, the processing module may receive the pin signals of the first type of pins of the connector in real time, and receive the pin signals of the second type of pins in real time. The pin signals of the first type of pins are first pin signals, and the pin signals of the second type of pins are second pin signals. The first pin signal may be a level signal of any one of the first type pins, and the second pin signal may be a level signal of any one of the second type pins.
It can be appreciated that the manner of acquiring the first pin signal and the second pin signal may be determined according to practical situations. For example, the processing module may collect the first pin signal of the first type of pin and collect the second pin signal of the second type of pin with a set detection period. The detection period may be determined according to actual conditions, and is not particularly limited herein.
In step S220, the pin signal changes, which can be understood as: the pin signal changes from a high level signal to a low level signal or from a low level signal to a high level signal. The duration of the current detection period is usually a preset duration, and can be determined according to actual conditions. For example, the current detection period may be triggered when any one of the first pin signal and the second pin signal changes. For example, if the first pin signal changes, the preset duration before and after the first pin signal changes may be used as the current detection period. The preset duration is usually a shorter duration and is greater than the first specified duration and the second specified duration. The first designated time length and the second designated time length are usually not more than 1 second, and can be determined according to actual conditions.
For example, the first specified duration may be 10 milliseconds, 50 milliseconds, 100 milliseconds, etc. The first designated duration can be used for representing the interval duration of connection of the long and short pins (the first type pins and the second type pins) of the connector with the probes in the hardware module when the hardware module is plugged/unplugged on the connector, or the interval duration of disconnection of the long and short pins with the probes in the hardware module; or the first specified duration may be slightly longer than the aforementioned interval duration. The second specified duration may be slightly longer than the first specified duration. The preset time period (current detection period) may be a time period of 1 second, 2 seconds, or the like.
For example, in the present embodiment, each 1 second period before and after the first foot signal is changed may be taken as the current detection period, or each 1 second period before and after the second foot signal is changed may be taken as the current detection period, and thus, one period of inserting or extracting the hardware module may be included in one detection period.
In the current detection period, any pin signal in the first pin signal and the second pin signal is changed first, which can be understood as: in the current detection period, the first pin signal and the second pin signal may change, and at this time, the moment when the first change occurs is the moment when the first change occurs in the first pin signal and the second pin signal; or only one of the first pin signal and the second pin signal changes, and at this time, the moment when the first change occurs is the moment when the single pin signal changes.
As an alternative embodiment, step S120 may include: updating the first pin signal in the first specified time after the first change to the pin signal of the first type pin at the target time, and updating the second pin signal in the first specified time after the first change to the pin signal of the second type pin at the target time.
It is understood that, when the connector is plugged into the hardware module, for different types of hardware modules, due to the influence of the high and low pins of the connector, signals of the first type pin and the second type pin fluctuate during the action of plugging into or unplugging from the connector, and the signals of the pins during plugging into or unplugging cannot be used as the signals of the pins for judging the type of hardware. In the conventional processing manner, if the processing module collects the first pin signal and the second pin signal during the insertion or extraction period, there may be misjudgment at this time. For example, when a SATA hard disk is inserted, during the insertion or extraction, there is a case where the u.2ssd is erroneously triggered to interrupt, and at this time, the PCIe hot plug flow is erroneously triggered, thereby increasing the processing flow.
In the embodiment of the application, in the current detection period, the first designated time period after the pin signal is changed first comprises the time period during which the hardware module is inserted or pulled out. Therefore, the first pin signal and the second pin signal during the process of plugging or unplugging the hardware module can be respectively updated into the pin signals corresponding to a moment before plugging or unplugging, so that the signals of the first type pins and the second type pins are prevented from fluctuating during the process of plugging or unplugging the connector. After updating and correcting the pin signals, the reliability of the corrected pin signals of the first type pin and the corrected pin signals of the second type pin can be improved during the action of inserting or extracting the connector, misjudgment caused by signal fluctuation is avoided, and the PCIe hot plug flow is not triggered by mistake, so that the processing flow of the pin signals is simplified.
As an optional embodiment, the connector is configured to connect to a hard disk, where a type of the hard disk includes at least one of SATA, U.2, SAS, and step S120 may include:
When the pin signals of the first type pins and the second type pins are high-level signals at the target moment, updating the first pin signals and the second pin signals in the first appointed time period after the first change to the high-level signals;
when the pin signals of the first type pins and the second type pins are low-level signals at the target moment, updating the first pin signals and the second pin signals in the first appointed time period after the first change to the low-level signals;
When the pin signal of the first type pin is a low level signal at the target time, and when the pin signal of the second type pin is a high level signal at the target time, updating the first pin signal in the first designated time period after the first change to the low level signal, and updating the second pin signal in the first designated time period after the first change to the high level signal.
For example, please refer to fig. 4, taking the connector as the SFF-8639 connector, the hard disk as the SATA hard disk, and the u.2ssd as an example, the implementation process of step S120 is illustrated as follows:
In fig. 4, the time corresponding to the broken line a may be understood as the target time, that is, a time before the time at which the change first occurs and at an interval of a second specified period of time. The time corresponding to the broken line B may be understood as the time when the pin signal changes first and is separated from the time when the pin signal changes by a first designated time length, where the first designated time length shown in fig. 4 is T1 or T2. In other embodiments, the first specified duration may be slightly longer than T1 or T2. For example, the starting time of the first specified duration may be F1, and the ending time may be a time corresponding to the E line, where the E line is later than the B line. F1 is the time when the pin signal first changes during insertion into the hardware module, and F2 is the time when the pin signal first changes during extraction from the hardware module. T0 may be the second specified duration described above. T1 may be: during insertion of the hardware module, the long pins of the connector contact the probes of the hardware module for a period of time during which the short pins contact the probes of the hardware module. T2 may be: during the process of extracting the hardware module, the length of time between the short pins of the connector leaving the probes of the hardware module and the long pins leaving the probes of the hardware module.
After the SATA hard disk or the u.2ssd is inserted into the connector, the processing module may determine the type of the connected hard disk based on IFDET # (first pin signal) of the P4 pin (first type pin) and prsnt# (second pin signal) of the P10 pin (second type pin) of the connector. If IFDET # is a low level signal (which may be represented by a number "0"), prsnt# is a high level signal (which may be represented by a number "1"), indicating that the hard disk is typically a u.2ssd. That is, the processing module may determine that the currently inserted hard disk is a U.2SSD. If IFDET # and prsnt# are both low-level signals, it indicates that the hard disk connected to the connector is a SATA hard disk, that is, the processing module may determine that the currently inserted hard disk is a SATA hard disk.
Referring to fig. 4 again, before the pin signal is updated, if the SATA hard disk is plugged into the connector, then IFDET # and prsnt# are respectively 0 and 1 during T1 and T2, at this time, the processing module may misjudge the SATA hard disk as a u.2ssd, so that the hot plug interrupt of the u.2ssd may be triggered by mistake, and further the normal operation of the SATA hard disk or the electronic device is affected.
When updating the pin signal, for the insertion operation, IFDET # and prsnt# in the period T1 may be updated to IFDET # and prsnt# respectively at the target time of the a dotted line, which are both 1 (high level signal), so as to obtain updated IFDET # and prsnt# which are both high level signals, as shown in the updated plot of fig. 4.
For the unplugging action, the electronic device does not need to determine the type of the unplugged hard disk, and can directly update IFDET # and prsnt# during T2 to IFDET # and prsnt# at the target time of the C-dashed line, respectively. For example, if IFDET # and prsnt# are both 0 at the target time of the C dotted line, IFDET # and prsnt# during T2 are both updated to 0. If IFDET # is 0 and prsnt# is 1 at the target time of the C dotted line, IFDET # is updated to 0 during T2 and prsnt# is updated to 1 during T2, as shown in the updated plot of fig. 4. Thus, the pin signal during the plugging or unplugging period can be updated through simple logic operation. After the pin signals are updated, the interruption and the later correction of the false report U.2SSD can not occur, so that the processing flow of the pin signals is simplified, and the accuracy of the detection of the hard disk type is improved.
As an optional implementation manner, in step S120, the first pin signal and the second pin signal in the first specified period after the first change may be updated by delaying the first pin signal and the second pin before the first change, where the delay time is the first specified period. That is, step S120 may be:
Delaying the first pin signal before the first change by a first specified period of time and delaying the second pin signal before the first change by the first specified period of time.
For example, referring to fig. 4 again, during the insertion period, for the SATA hard disk, the pin signal with IFDET # 1 and prsnt# 1 at the time F1 may be delayed, where the delay time is the first specified duration. The first designated duration may be T1 or a duration slightly longer than T1, so that it may be ensured that IFDET # is 1 and prsnt# is 1 in the inserted T1 period, and the situation that IFDET # is 0 and prsnt# is 1 before SATA hard disk update as in fig. 4 does not occur, so that the problem of false alarm hot plug interrupt due to IFDET # being 0 and prsnt# being 1 is avoided.
Similarly, during the pulling-out period, for the SATA hard disk, the pin signal with IFDET # 0 and prsnt# 0 at the time F2 may be delayed, where the delay time is the first specified duration. The first specified duration may be T2 or a duration slightly longer than T2, so that it may be ensured that IFDET # is 0 and prsnt# is 0 during the pulled-out T2 period, and no cases such as IFDET # being 0 and prsnt# being 1 before SATA hard disk update in fig. 4 occur.
It should be noted that, when the electronic device processes the pin signals of other types of hard disks, the processing procedure is similar to the processing manner of the pin signals of the SATA hard disk described above, and will not be repeated here.
As an alternative embodiment, the method may further comprise:
and determining the state of the connector or the type of the connected hardware module according to the first pin signal and the second pin signal after the first designated time period is over.
Referring to fig. 4 again, in this embodiment, after the first specified duration is over, it can be understood that: any time during the period from the end of the first specified duration to the end of the first specified duration of the next detection period, that is, any time during the updated B to D period in fig. 4 may be used. The type of hardware module or the type of hard disk into which the current connector is inserted may be determined by IFDET # (first pin signal) and prsnt# (second pin signal) at any time in the updated B to D period.
For example, during the period from B to D, if IFDET # and prsnt# are both 0, the processing module may determine that the hard disk into which the connector is currently inserted is a SATA hard disk.
For another example, during the period from B to D, if IFDET # is 0 and prsnt# is 1, the processing module may determine that the hard disk into which the connector is currently inserted is u.2ssd.
If IFDET # and PRSNT# are both 1, it is typical that the connector is not inserted into the hard disk.
In the above embodiment, after the pin signal during the insertion or extraction period is updated, the pin signal at the later time is used to perform detection and judgment, so that the accuracy of judging the type of the hardware module can be improved.
As an alternative embodiment, the method may further comprise:
After the first specified duration is over, if the first pin signal of the first type of pins is a low level signal and the second pin signal of the second type of pins is a high level signal, outputting an interrupt signal representing a hot plug interrupt.
Understandably, if the type of the hard disk to which the connector is connected is U.2, after the first specified duration is over, the first pin signal of the first type pin is a low level signal, and the second pin signal of the second type pin is a high level signal, at this time, an interrupt signal of the plug interrupt needs to be reported to a system (such as a motherboard module of the electronic device) for the system to perform the interrupt of the hot plug, so that the u.2ssd can implement the hot plug operation.
If the processing module determines that the hard disk connected to the connector is a SATA hard disk, that is, if IFDET # and prsnt# are both 0 during the period from B to D, the processing module may not need to report a hot plug interrupt.
In the embodiment, whether the hard disk connected with the connector is the U.2SSD can be accurately judged, so that the hot plug of the U.2SSD is realized by the interrupt signal of the hot plug interrupt, and the influence on the normal operation of the SATA hard disk caused by reporting the hot plug interrupt when the SATA hard disk is inserted is avoided.
In this embodiment, the processing module may update the first pin signal and the second pin signal in the first specified duration in real time through the step S120 described above; or updating the first pin signal and the second pin signal in the first designated time length in a delay processing mode, and then reporting the hot plug interrupt.
For example, during real-time processing, the first pin signal and the second pin signal in the first designated time after the signal is changed in the current detection period are directly updated to the first pin signal and the second pin signal at the target time respectively, so as to realize the real-time updating processing of the pin signals.
For example, when the delay processing is performed, the memory firstly caches the collected unprocessed first pin signal and the second pin signal, and then the processing module corrects and updates the first pin signal and the second pin signal within a first designated time period after the current cached signal is changed (that is, updates the first pin signal and the second pin signal within the first designated time period after the cached signal is changed into the first pin signal and the second pin signal at the target time respectively). And finally, taking the updated first pin signal and second pin signal as the basis of whether to output an interrupt signal representing the hot plug interrupt.
For example, before step S220, the method may further include:
judging whether the duration of the first pin signal is a first preset signal and the duration of the second pin signal is a second preset signal is smaller than or equal to a first specified duration;
When the duration is less than or equal to the first specified duration, determining a reference time in the duration, wherein the target time is a time before and spaced from a time when the first pin signal or the second pin signal changes by the second specified duration, or a time before and spaced from the reference time by a third specified duration, and the third specified time is greater than the first specified duration.
In this embodiment, the processing module may collect, with a shorter collection period, the first pin signal of the first type pin and the second pin signal of the second type pin, so as to determine that the first pin signal is a first preset signal, and the second pin signal is a duration of the second preset signal.
Understandably, the memory in the processing module or the memory externally connected to the processing module may buffer the acquired first pin signals of the unprocessed first type pins and the acquired second pin signals of the second type pins. The time period for buffering the first pin information and the second pin signal may be the time period of the current detection period. That is, the processing module may empty the first pin signal and the second pin signal that are buffered before in the memory every predetermined time interval, and then buffer the first pin signal and the second pin signal that are acquired in the current latest cycle in the memory. Thereafter, the processing module may analyze the first pin signal and the second pin signal of the current buffer.
Such as: judging whether the duration of the first pin signal is a first preset signal and the duration of the second pin signal is a second preset signal is smaller than or equal to a first specified duration; when the duration is less than or equal to the first specified duration, the operation that currently causes the signal fluctuation is represented as a plug-in or plug-out operation (the duration of the signal fluctuation due to the plug-in operation is shorter); then, updating the first pin signal in the duration (such as during the period T1 or T2 before the update in fig. 4) to the first pin signal at the target time (such as the time a before the update in fig. 4); and updating the second pin signal for the duration (e.g., during T1 or T2 before the update of fig. 4) to the second pin signal for the target time (e.g., time a before the update of fig. 4). Finally, the processing module can analyze and judge according to the levels of the updated first pin signal and the updated second pin signal. For example, if the updated first pin signal is a low level signal and the updated second pin signal is a high level signal, an interrupt signal indicating a hot plug interrupt is output. In addition, the processing module may determine the type of the hardware module connected to the connector according to the updated level values of the first pin signal and the second pin signal.
In this embodiment, the first preset signal and the second preset signal may be determined according to actual situations. For example, for a connector for connecting a SATA hard disk or a u.2ssd, the first preset signal may be a low level signal and the second preset signal may be a high level signal. Thus, the duration of T1 or T2 before updating in fig. 4 may be detected, that is, the duration of the first pin signal is a low level signal and the second pin signal is a high level signal.
Since the hardware module is plugged into or pulled out of the connector, if the SATA hard disk is used, the first pin signal is a low level signal, and the duration of the second pin signal is a high level signal (e.g., T1 and T2 in fig. 4) is short, which is usually several milliseconds or several tens milliseconds. In the case of SATA hard disk, the first pin signal is a low level signal, and the second pin signal is a high level signal for a relatively long duration, typically exceeding 1 second. Therefore, the type of hard disk (or the type of hardware module) that is inserted or extracted can be distinguished by the length of the duration. The first specified duration is less than 1 second and greater than any of T1 and T2, for example, 500 milliseconds.
For example, referring to fig. 4, if it is determined that the first pin signal is a low level signal and the duration of the second pin signal being a high level signal is less than or equal to the first specified duration, the reference time may be any time of T1 or T2. For example, for the first pin signal and the second pin signal during T1 before update, the reference time may be a start time of T1 or an end time of T1. The target time may be a time before the reference time and spaced apart by a third specified time period, and the third specified time period is longer than the first specified time period, i.e., the third specified time period may be greater than any of T1 and T2.
When the duration is required to be detected, the duration of the acquisition period is required to be smaller than the first specified duration, or the acquisition period is smaller than the interval duration of the connection of the long and short pins of the connector with the probes in the hardware module, or the interval duration of the disconnection of the long and short pins with the probes in the hardware module. For example, the first specified duration may be 100 milliseconds, the acquisition period may be 1 millisecond, and the processing module may acquire the first pin signal of the first type pin and the second pin signal of the second type pin once every 1 millisecond.
When the duration of the first pin signal being the low level signal and the duration of the second pin signal being the high level signal being less than or equal to the first specified duration, in step S220, the update mode of the pin signal may be the foregoing implementation mode, that is: updating the first pin signal in the first specified time after the first change to the pin signal of the first type pin at the target time, and updating the second pin signal in the first specified time after the first change to the pin signal of the second type pin at the target time.
Or the updating mode of the pin signal can be: for the first pin signal and the second pin signal with the duration less than the first designated duration, the inverse level signal of the pin signal of the first type pin at the target moment can be utilized to update the first pin signal in the duration; and updating the second pin signal in the duration time by using the inverse level signal of the pin signal of the second type pin at the target time without updating the first pin signal and the second pin signal in other time periods.
The inverse level signal of the pin signal can be understood as: a level signal opposite to the level of the pin signal. For example, if the pin signal is a high level signal, the inverse level signal of the pin signal is a low level signal; if the pin signal is a low level signal, the inverse level signal of the pin signal is a high level signal.
Referring to fig. 5, an embodiment of the present application further provides a connector processing apparatus 100, which can be applied to the above-mentioned processing module, and is used for executing or implementing each step in the connector processing method. The connector processing device 100 includes at least one software function module that may be stored in a memory in the form of software or Firmware (Firmware) or cured in a processing module Operating System (OS). The processor in the processing module is configured to execute executable modules stored in the memory, such as software functional modules and computer programs included in the connector processing device 100.
The connector processing apparatus 100 may include the acquisition unit 110 and the update unit 120, and the following operations may be performed:
an obtaining unit 110, configured to obtain a first pin signal of the first type pin and a second pin signal of the second type pin;
and the updating unit 120 is configured to update, in the current detection period, the first pin signal and the second pin signal within a first specified duration after the first change according to the pin signals of the first type pin and the second type pin at a target time when any pin signal in the first pin signal and the second pin signal changes first, so as to obtain an updated first pin signal and second pin signal, where the target time includes a time before the first change time and a time spaced from the first change time by a second specified time.
Optionally, the updating unit 120 may be further configured to: updating the first pin signal in the first specified time after the first change to the pin signal of the first type pin at the target time, and updating the second pin signal in the first specified time after the first change to the pin signal of the second type pin at the target time.
Optionally, the connector is used to connect to a hard disk, where the type of the hard disk includes at least one of SATA, U.2, SAS, and the updating unit 120 may be further used to:
When the pin signals of the first type pins and the second type pins are high-level signals at the target moment, updating the first pin signals and the second pin signals in the first appointed time period after the first change to the high-level signals;
when the pin signals of the first type pins and the second type pins are low-level signals at the target moment, updating the first pin signals and the second pin signals in the first appointed time period after the first change to the low-level signals;
When the pin signal of the first type pin is a low level signal at the target time, and when the pin signal of the second type pin is a high level signal at the target time, updating the first pin signal in the first designated time period after the first change to the low level signal, and updating the second pin signal in the first designated time period after the first change to the high level signal.
Optionally, the connector processing apparatus 100 may further include a type determining unit, configured to determine a state of the connector or a type of the connected hardware module according to the first pin signal and the second pin signal after the first specified duration is over.
Optionally, the type of the hard disk includes at least one of SATA, U.2, and SAS, and the connector processing apparatus 100 may further include an interrupt reporting unit, configured to output an interrupt signal indicating a hot plug interrupt if, after the first specified duration is over, the first pin signal of the first type of pin is a low level signal and the second pin signal of the second type of pin is a high level signal.
Optionally, the connector processing apparatus 100 may further include a judging unit and a reference time determining unit. Before the updating unit 120 performs step S220, the judging unit is configured to: judging whether the duration of the first pin signal is a first preset signal and the duration of the second pin signal is a second preset signal is smaller than or equal to a first specified duration. The reference time determining unit is used for: when the duration is less than or equal to the first specified duration, a reference time is determined in the duration, the target time being a time before the first time at which the change occurs and spaced from the second specified duration, or a time before the reference time and spaced from the reference time by a third specified duration, the third specified time being greater than the first specified duration.
Optionally, the reference time determining unit is further configured to: and when the duration is less than or equal to the first designated duration, determining a starting time of the duration as the reference time or determining an ending time of the duration as the reference time.
In this embodiment, the processor may be an integrated circuit chip with signal processing capability. The processor may be a general purpose processor. For example, the processor may be a central Processing unit (Central Processing Unit, CPU), digital signal processor (DIGITAL SIGNAL Processing, DSP), application Specific Integrated Circuit (ASIC), field-Programmable gate array (Field-Programmable GATE ARRAY, FPGA) or other Programmable logic device, discrete gate or transistor logic, discrete hardware components, which may implement or perform the methods, steps, and logic blocks disclosed in embodiments of the application.
The memory may be, but is not limited to, random access memory, read only memory, programmable read only memory, erasable programmable read only memory, electrically erasable programmable read only memory, and the like. In this embodiment, the memory may be configured to store a correspondence between the first pin signal, the second pin signal, and the hardware module type, a first specified duration, a second specified duration, and so on. Of course, the memory may also be used to store a program that the processor executes after receiving the execution instructions.
It will be appreciated that the configuration shown in fig. 1 is merely a schematic diagram of one configuration of a process module, and that a process module may include many more components than those shown in fig. 1. The components shown in fig. 1 may be implemented in hardware, software, or a combination thereof.
It should be noted that, for convenience and brevity of description, specific working processes of the processing module, the electronic device, and the connector processing apparatus 100 described above may refer to corresponding processes of each step in the foregoing method, and will not be described in detail herein.
The embodiment of the application also provides a computer readable storage medium. The readable storage medium has stored therein a computer program which, when run on a computer, causes the computer to perform the connector processing method as described in the above embodiments.
From the foregoing description of the embodiments, it will be apparent to those skilled in the art that the present application may be implemented in hardware, or by means of software plus a necessary general hardware platform, and based on this understanding, the technical solution of the present application may be embodied in the form of a software product, which may be stored in a non-volatile storage medium (may be a CD-ROM, a U-disc, a mobile hard disk, etc.), and includes several instructions for causing a computer device (may be a personal computer, a server, or a network device, etc.) to execute the method described in the respective implementation scenario of the present application.
In summary, the application provides a connector processing method, a device, a processing module and an electronic apparatus. The method comprises the following steps: acquiring a first pin signal of a first type pin and a second pin signal of a second type pin; in the current detection period, when any one of the first pin signal and the second pin signal is changed at first, updating the first pin signal and the second pin signal in a first appointed time after the first change according to the pin signals of the first type pin and the second type pin at a target time, so as to obtain the updated first pin signal and the updated second pin signal, wherein the target time comprises a time before the first change time and spaced by a second appointed time. In this scheme, the first specified duration is generally slightly longer than the duration of plugging or unplugging the hardware module, and the first specified duration after the pin signal is first changed generally includes the duration used for the plugging or unplugging action. By resetting the pin signals of the first type of pins and the second type of pins within the first designated time period after the pin signals are changed to the pin signals of the second designated time period before the pin signals are changed, false triggering of hot plug interruption caused by fluctuation of the pin signals when the hardware module is plugged or pulled out can be avoided, and subsequent false alarm correction processing flow triggered by the hot plug interruption is avoided, so that the processing flow is simplified, and the accuracy of detecting the type of the hardware module is improved.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus, system and method may be implemented in other manners as well. The above-described apparatus, system, and method embodiments are merely illustrative, for example, flow charts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present application. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions. In addition, functional modules in the embodiments of the present application may be integrated together to form a single part, or each module may exist alone, or two or more modules may be integrated to form a single part.
The above description is only of the preferred embodiments of the present application and is not intended to limit the present application, but various modifications and variations can be made to the present application by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application.
Claims (8)
1. A connector processing method, applied to a processing module, where the processing module is configured to connect with a connector, the connector includes a first type pin and a second type pin, and the length of the first type pin is greater than that of the second type pin, the method includes:
acquiring a first pin signal of the first type pin and a second pin signal of the second type pin;
In the current detection period, when any one of the first pin signal and the second pin signal is changed at first, updating the first pin signal and the second pin signal in a first appointed time period after the first change according to the pin signals of the first type pin and the second type pin at a target time, so as to obtain updated first pin signal and second pin signal, wherein the target time comprises a time which is before the time of the first change and is spaced from the time of the first change by a second appointed time period;
Updating the first pin signal and the second pin signal in the first specified duration after the first change according to the pin signals of the first type pin and the second type pin at the target time to obtain updated first pin signals and second pin signals, wherein the updating comprises the following steps:
Updating the first pin signal in the first specified time period after the first change to the pin signal of the first type pin at the target time, and updating the second pin signal in the first specified time period after the first change to the pin signal of the second type pin at the target time;
Before obtaining the updated first pin signal and the updated second pin signal, the method further includes:
judging whether the duration of the first pin signal is a first preset signal and the duration of the second pin signal is a second preset signal is smaller than or equal to a first specified duration;
When the duration is less than or equal to the first specified duration, a reference time is determined in the duration, the target time being a time before the first time at which the change occurs and spaced from the second specified duration, or a time before the reference time and spaced from the reference time by a third specified duration, the third specified time being greater than the first specified duration.
2. The method according to claim 1, wherein the method further comprises:
and determining the state of the connector or the type of the connected hardware module according to the first pin signal and the second pin signal after the first designated time period is over.
3. The method of claim 1, wherein the connector is for connecting a hard disk, the type of hard disk comprising at least one of SATA, U.2, the method further comprising:
After the first specified duration is over, if the first pin signal of the first type of pins is a low level signal and the second pin signal of the second type of pins is a high level signal, outputting an interrupt signal representing a hot plug interrupt.
4. The method of claim 1, wherein determining a reference time in the duration when the duration is less than or equal to the first specified duration comprises:
And when the duration is less than or equal to the first designated duration, determining a starting time of the duration as the reference time or determining an ending time of the duration as the reference time.
5. A connector processing device, characterized in that it is applied to a processing module, the processing module is used for being connected with a connector, the connector includes a first type pin and a second type pin, the length of the first type pin is greater than the second type pin, the device includes:
The acquisition unit is used for acquiring a first pin signal of the first type pin and a second pin signal of the second type pin;
The updating unit is used for updating the first pin signal and the second pin signal in the first specified time after the first change according to the pin signals of the first type pin and the second type pin at the target time when any pin signal in the first pin signal and the second pin signal is changed at first in the current detection period to obtain the updated first pin signal and the updated second pin signal, wherein the target time comprises a time which is a second specified time interval from the first changed time before the first changed time;
The updating unit is specifically configured to update the first pin signal in the first specified duration after the first change to a pin signal of the first type pin at the target time, and update the second pin signal in the first specified duration after the first change to a pin signal of the second type pin at the target time;
the device also comprises a judging unit and a reference moment determining unit;
The judging unit is used for judging whether the duration time of the first pin signal which is a first preset signal and the second pin signal which is a second preset signal is smaller than or equal to a first appointed time;
The reference time determining unit is configured to determine, when the duration is less than or equal to the first specified duration, a reference time in the duration, where the target time is a time before the first time when the change occurs and spaced from the second specified duration, or a time before the reference time and spaced from the third specified duration, where the third specified time is longer than the first specified duration.
6. A processing module comprising a memory, a processor coupled to each other, the memory storing a computer program, which when executed by the processor, causes the processing module to perform the method of any of claims 1-4.
7. An electronic device comprising a motherboard module and a processing module as recited in claim 6.
8. A computer readable storage medium, characterized in that the computer readable storage medium has stored therein a computer program which, when run on a computer, causes the computer to perform the method according to any of claims 1-4.
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