CN112463445B - Link recovery method, device, equipment and computer readable storage medium - Google Patents
Link recovery method, device, equipment and computer readable storage medium Download PDFInfo
- Publication number
- CN112463445B CN112463445B CN202011301997.6A CN202011301997A CN112463445B CN 112463445 B CN112463445 B CN 112463445B CN 202011301997 A CN202011301997 A CN 202011301997A CN 112463445 B CN112463445 B CN 112463445B
- Authority
- CN
- China
- Prior art keywords
- link
- pcie
- state information
- pcie switch
- switch chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 51
- 238000011084 recovery Methods 0.000 title claims abstract description 50
- 238000004590 computer program Methods 0.000 claims description 11
- 230000002045 lasting effect Effects 0.000 claims description 6
- 230000000694 effects Effects 0.000 abstract description 4
- 230000005540 biological transmission Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000002159 abnormal effect Effects 0.000 description 3
- 230000006872 improvement Effects 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005055 memory storage Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/14—Error detection or correction of the data by redundancy in operation
- G06F11/1402—Saving, restoring, recovering or retrying
- G06F11/1405—Saving, restoring, recovering or retrying at machine instruction level
- G06F11/141—Saving, restoring, recovering or retrying at machine instruction level for bus or memory accesses
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Debugging And Monitoring (AREA)
Abstract
The invention discloses a link recovery method, which comprises the following steps: collecting link state information corresponding to each PCIe link; judging whether the state information of each link meets a preset state threshold value; and if not, sending a reset instruction to the PCIe switch chip so that the PCIe switch chip performs unified reset operation on the PCIe links by using PCIe switch downlink ports connected with the PCIe links. The link recovery method provided by the invention greatly reduces the operation complexity, improves the reset efficiency, saves time and meets the requirement of the system on the timeout time. The invention also discloses a link recovery device, equipment and a storage medium, and has corresponding technical effects.
Description
Technical Field
The present invention relates to the field of storage technologies, and in particular, to a link recovery method, apparatus, device, and computer readable storage medium.
Background
In the field of storage, reliability of data is particularly important. The reliability of the storage complete machine cannot be separated from the hung equipment, data transmission depends on the support of a data transmission link, in order to improve the data transmission speed, most of the existing storage equipment adopts a high-speed serial computer expansion bus (PCIe) link for data transmission, and when the PCIe link fails, the PCIe link needs to be recovered, so that the PCIe equipment is quickly reset.
In a full flash memory storage system, the nvme disks are usually used as storage devices, the number of connected nvme disks is more and more, and the situations of link degradation or speed reduction of the nvme disks are more and more frequent. The existing PCIe link recovery mode is to sequentially reset each PCIe link, which is complex in operation and long in time consumption and cannot meet the requirement of a system on timeout time.
In summary, how to effectively solve the problems that the existing link recovery mode is complex in operation, long in time consumption, incapable of meeting the requirement of the system on the timeout time, and the like is a problem that needs to be solved urgently by a person skilled in the art at present.
Disclosure of Invention
The invention aims to provide a link recovery method, which greatly reduces the operation complexity, improves the reset efficiency, saves time and meets the requirement of a system on timeout time; another object of the present invention is to provide a link recovery apparatus, device and computer-readable storage medium.
In order to solve the technical problems, the invention provides the following technical scheme:
a method of link recovery, comprising:
collecting link state information corresponding to each PCIe link;
judging whether the link state information meets a preset state threshold value;
and if not, sending a reset instruction to a PCIe switch chip so that the PCIe switch chip performs unified reset operation on each PCIe link by using a PCIe switch downlink port connected with each PCIe link.
In a specific embodiment of the present invention, before sending the reset instruction to the PCIe switch chip, the method further includes:
acquiring equipment state information of PCIe equipment corresponding to each PCIe link;
and storing each piece of equipment state information.
In a specific embodiment of the present invention, after the PCIe switch chip performs a unified reset operation on each PCIe link by using a PCIe switch downstream port connected to each PCIe link, the method further includes:
calling pre-stored state information of each device;
and sending the state information of each device to the corresponding PCIe device through each target PCIe link obtained by recovery.
In a specific embodiment of the present invention, the collecting link status information corresponding to each PCIe link includes:
collecting link speeds corresponding to the PCIe links respectively;
judging whether each link state information meets a preset state threshold value or not, including:
and judging whether the link speeds meet a preset speed threshold value.
In a specific embodiment of the present invention, the acquiring link state information corresponding to each PCIe link includes:
acquiring link bandwidths corresponding to the PCIe links respectively;
judging whether each link state information meets a preset state threshold value or not, including:
and judging whether the bandwidth of each link meets a preset bandwidth threshold value.
In a specific embodiment of the present invention, the performing, by the PCIe switch chip, a unified reset operation on each PCIe link by using a PCIe switch downstream port connected to each PCIe link includes:
the PCIe switch chip utilizes the PCIe switch downlink port to send an enable reset signal lasting for a preset time to each PCIe link, and the unified reset operation is carried out on each PCIe link.
A link recovery apparatus comprising:
the link information acquisition module is used for acquiring link state information corresponding to each PCIe link;
the judging module is used for judging whether the link state information meets a preset state threshold value;
and the reset module is used for sending a reset instruction to a PCIe switch chip when determining that the link state information which does not meet the preset state threshold exists in the link state information, so that the PCIe switch chip performs unified reset operation on the PCIe links by using PCIe switch downlink ports connected with the PCIe links.
In an embodiment of the present invention, the method further comprises:
the device information acquisition module is used for acquiring the device state information of the PCIe devices corresponding to the PCIe links before sending a reset instruction to the PCIe switch chip;
and the information storage module is used for storing the state information of each device.
A link recovery device comprising:
a memory for storing a computer program;
a processor for implementing the steps of the link recovery method as described above when executing the computer program.
A computer-readable storage medium, having stored thereon a computer program which, when being executed by a processor, carries out the steps of the link recovery method as set forth above.
The link recovery method provided by the invention collects the link state information corresponding to each PCIe link; judging whether the state information of each link meets a preset state threshold value; and if not, sending a reset instruction to the PCIe switch chip so that the PCIe switch chip performs unified reset operation on the PCIe links by using PCIe switch downlink ports connected with the PCIe links. Through setting up PCIe switch chip to link up each PCIe link with the PCIe switch downstream port of PCIe switch chip, when detecting that there is the PCIe link that link state information does not satisfy the predetermined state threshold, carry out unified reset operation to each PCIe link through PCIe switch downstream port. Compared with the existing mode of sequentially resetting each PCIe link, the method has the advantages of greatly reducing the operation complexity, improving the resetting efficiency, saving time and meeting the requirement of the system on timeout.
Correspondingly, the invention also provides a link recovery device, equipment and a computer readable storage medium corresponding to the link recovery method, which have the technical effects and are not described herein again.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the prior art descriptions will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a flowchart of an implementation of a link recovery method according to an embodiment of the present invention;
FIG. 2 is a flow chart of another embodiment of a link recovery method according to the present invention;
FIG. 3 is a flow chart of another implementation of a link recovery method according to an embodiment of the present invention;
fig. 4 is a block diagram of a link recovery apparatus according to an embodiment of the present invention;
fig. 5 is a block diagram of a link recovery device according to an embodiment of the present invention.
Detailed Description
In order that those skilled in the art will better understand the disclosure, the invention will be described in further detail with reference to the accompanying drawings and specific embodiments. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be obtained by a person skilled in the art without making any creative effort based on the embodiments in the present invention, belong to the protection scope of the present invention.
The first embodiment is as follows:
referring to fig. 1, fig. 1 is a flowchart of an implementation of a link recovery method in an embodiment of the present invention, where the method may include the following steps:
s101: and collecting link state information corresponding to each PCIe link.
The upper computer is in communication connection with the PCIe devices through the PCIe links, and in the process of running of the storage system, the upper computer can acquire link state information corresponding to the PCIe links in real time or according to preset time intervals.
S102: and judging whether the state information of each link meets a preset state threshold value, if so, executing the step S103, and if not, not processing.
Presetting a state threshold value of the PCIe link, after collecting link state information corresponding to each PCIe link, judging whether the state information of each link meets the preset state threshold value, if not, indicating that an abnormal PCIe link exists, and executing a step S103, if so, indicating that each PCIe link is normal and not processing.
S103: and sending a reset instruction to the PCIe switch chip so that the PCIe switch chip performs unified reset operation on the PCIe links by using PCIe switch downlink ports connected with the PCIe links.
And PCIe switch chips are arranged between the upper computer and each PCIe link, and each PCIe link is connected with a PCIe switch downlink port of each PCIe switch chip. When determining that the link state information which does not meet the preset state threshold exists in the link state information, sending a reset instruction to the PCIe switch chip, carrying out unified reset operation on the PCIe links by the PCIe switch chip through PCIe switch downlink ports connected with the PCIe links to enable a hot reset to take effect, enabling the PCIe state machine LTSSM to recover to a normal state, and retraining each PCIe link to enable the PCIe link to recover to a normal state. Compared with the conventional mode of sequentially resetting each PCIe link, the method can quickly recover the abnormal PCIe link, greatly reduces the operation complexity, improves the resetting efficiency, saves time, meets the requirement of a system on timeout, completes the guarantee of data storage, and improves the reliability and the availability of the storage equipment.
The link recovery method provided by the invention collects the link state information corresponding to each PCIe link; judging whether the state information of each link meets a preset state threshold value; if not, a reset instruction is sent to the PCIe switch chip, so that the PCIe switch chip performs unified reset operation on the PCIe links by using PCIe switch downlink ports connected with the PCIe links. Through setting up PCIe switch chip to link up each PCIe link with the PCIe switch downstream port of PCIe switch chip, when detecting that there is the PCIe link that link state information does not satisfy the predetermined state threshold, carry out unified reset operation to each PCIe link through PCIe switch downstream port. Compared with the existing mode of sequentially resetting each PCIe link, the method has the advantages of greatly reducing the operation complexity, improving the resetting efficiency, saving time and meeting the requirement of the system on timeout.
It should be noted that, based on the first embodiment, the embodiment of the present invention further provides a corresponding improvement scheme. In the following embodiments, steps that are the same as or correspond to those in the first embodiment may be referred to each other, and corresponding advantageous effects may also be referred to each other, which are not described in detail in the following modified embodiments.
The second embodiment:
referring to fig. 2, fig. 2 is a flowchart of another implementation of a link recovery method in an embodiment of the present invention, where the method may include the following steps:
s201: and collecting the link speed corresponding to each PCIe link.
In the operation process of the storage system, the upper computer can acquire the link speed corresponding to each PCIe link in real time or according to a preset time interval.
S202: and judging whether the speeds of all the links meet a preset speed threshold value, if so, executing the step S203, and if not, not processing.
The method comprises the steps of presetting a speed threshold value of a PCIe link, and judging whether the speed of each link meets the preset speed threshold value after acquiring the link speed corresponding to each PCIe link.
S203: and acquiring the equipment state information of the PCIe equipment corresponding to each PCIe link.
And when determining that the link speed which does not meet the preset speed threshold exists in the link speeds, acquiring the equipment state information of the PCIe equipment corresponding to each PCIe link. The device state information may include information such as resources, operational addresses, etc. currently occupied by the PCIe device. The PCIe device may include a nvme disk.
S204: and storing the state information of each device.
And after the device state information of the PCIe devices corresponding to the PCIe links is acquired, storing the device state information. The backup operation of the device state information of each PCIe device is realized by storing the device state information of each PCIe device in advance.
S205: and sending a reset instruction to the PCIe switch chip so that the PCIe switch chip sends an enable reset signal lasting for a preset time to each PCIe link by using the PCIe switch downlink port, and performing unified reset operation on each PCIe link.
After the state information of each device is stored, a reset instruction is sent to the PCIe switch chip, and the PCIe switch chip sends an enable reset signal lasting for a preset time to each PCIe link by using a PCIe switch downlink port to perform unified reset operation on each PCIe link. The PCIe links are subjected to unified reset operation by sending the enabling reset signals lasting for the preset time to the PCIe links, so that the accuracy of the reset signals is ensured, and the probability of misoperation is reduced. The enable reset signal may be a pull-down reset signal.
It should be noted that the preset time period may be set and adjusted according to actual situations, which is not limited in the embodiment of the present invention. Such as may be set to two milliseconds.
S206: and calling pre-stored state information of each device.
And after the unified reset operation on each PCIe link is completed, pre-stored state information of each device is called.
S207: and sending the state information of each device to the corresponding PCIe device through each target PCIe link obtained through recovery.
After the prestored state information of each device is called, the state information of each device is sent to the corresponding PCIe device through the recovered target PCIe link, so that each PCIe device is recovered to the running state before the link is abnormal, and the data are ensured not to be lost.
Example three:
referring to fig. 3, fig. 3 is a flowchart of another implementation of a link recovery method in an embodiment of the present invention, where the method may include the following steps:
s301: and collecting link bandwidths corresponding to the PCIe links respectively.
In the operation process of the storage system, the upper computer can acquire the link bandwidth corresponding to each PCIe link in real time or according to a preset time interval.
S302: and judging whether the bandwidth of each link meets a preset bandwidth threshold, if so, executing the step S303, and if not, not processing.
The method comprises the steps of presetting a bandwidth threshold of a PCIe link, and judging whether the bandwidth of each link meets the preset bandwidth threshold after acquiring the link bandwidth corresponding to each PCIe link.
S303: and acquiring the equipment state information of the PCIe equipment corresponding to each PCIe link.
S304: and storing the state information of each device.
S305: and sending a reset instruction to the PCIe switch chip so that the PCIe switch chip sends an enable reset signal lasting for a preset time to each PCIe link by using the PCIe switch downlink port, and performing unified reset operation on each PCIe link.
S306: and calling pre-stored state information of each device.
S307: and sending the state information of each device to the corresponding PCIe device through each target PCIe link obtained by recovery.
Corresponding to the above method embodiment, the present invention further provides a link recovery apparatus, and the link recovery apparatus described below and the link recovery method described above may be referred to correspondingly.
Referring to fig. 4, fig. 4 is a block diagram of a link recovery apparatus according to an embodiment of the present invention, where the apparatus may include:
a link information collection module 41, configured to collect link state information corresponding to each PCIe link;
a determining module 42, configured to determine whether each of the link state information satisfies a preset state threshold;
the resetting module 43 is configured to send a resetting instruction to a PCIe switch chip when it is determined that link state information that does not meet a preset state threshold exists in each piece of link state information, so that the PCIe switch chip performs a unified resetting operation on each PCIe link by using a PCIe switch downstream port connected to each PCIe link.
The link recovery device provided by the invention collects the link state information corresponding to each PCIe link; judging whether the state information of each link meets a preset state threshold value; and if not, sending a reset instruction to the PCIe switch chip so that the PCIe switch chip performs unified reset operation on the PCIe links by using PCIe switch downlink ports connected with the PCIe links. Through setting up PCIe switch chip to link up each PCIe link with the PCIe switch downstream port of PCIe switch chip, when detecting that there is the PCIe link that link state information does not satisfy the predetermined state threshold, carry out unified reset operation to each PCIe link through PCIe switch downstream port. Compared with the existing mode of sequentially and singly resetting each PCIe link, the method has the advantages of greatly reducing the operation complexity, improving the resetting efficiency, saving time and meeting the requirement of the system on timeout time.
In one embodiment of the present invention, the apparatus may further include:
the device information acquisition module is used for acquiring the device state information of the PCIe devices corresponding to the PCIe links before sending a reset instruction to the PCIe switch chip;
and the information storage module is used for storing the state information of each device.
In one embodiment of the present invention, the apparatus may further include:
the state information calling module is used for calling the pre-stored state information of each device after the PCIe switch chip carries out unified reset operation on each PCIe link by using a PCIe switch downlink port connected with each PCIe link;
and the state information sending module is used for sending the state information of each device to the corresponding PCIe device through each target PCIe link obtained by recovery.
In a specific embodiment of the present invention, the link information collecting module 41 is specifically a module for collecting link speeds corresponding to the PCIe links respectively;
the determining module 42 is specifically a module for determining whether each link speed meets a preset speed threshold.
In a specific embodiment of the present invention, the link information collecting module 41 is specifically a module that collects link bandwidths corresponding to the PCIe links respectively;
the determining module 42 is specifically a module that determines whether each link bandwidth meets a preset bandwidth threshold.
In a specific embodiment of the present invention, the reset module 43 is specifically a module that the PCIe switch chip uses the PCIe switch downstream port to send an enable reset signal with a duration preset to each PCIe link, and performs a unified reset operation on each PCIe link.
Corresponding to the above method embodiment, referring to fig. 5, fig. 5 is a schematic diagram of a link recovery device provided in the present invention, where the link recovery device may include:
a memory 51 for storing a computer program;
the processor 52, when executing the computer program stored in the memory 51, may implement the following steps:
collecting link state information corresponding to each PCIe link; judging whether the state information of each link meets a preset state threshold value; and if not, sending a reset instruction to the PCIe switch chip so that the PCIe switch chip performs unified reset operation on the PCIe links by using PCIe switch downlink ports connected with the PCIe links.
For the introduction of the device provided by the present invention, please refer to the above method embodiment, which is not described herein again.
Corresponding to the above method embodiment, the present invention further provides a computer-readable storage medium having a computer program stored thereon, the computer program, when executed by a processor, implementing the steps of:
collecting link state information corresponding to each PCIe link; judging whether the state information of each link meets a preset state threshold value; if not, a reset instruction is sent to the PCIe switch chip, so that the PCIe switch chip performs unified reset operation on the PCIe links by using PCIe switch downlink ports connected with the PCIe links.
The computer-readable storage medium may include: various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.
For the introduction of the computer-readable storage medium provided by the present invention, please refer to the above method embodiments, which are not described herein again.
In the present specification, the embodiments are described in a progressive manner, and each embodiment focuses on differences from other embodiments, and the same or similar parts between the embodiments are referred to each other. The apparatuses, devices and computer-readable storage media disclosed in the embodiments correspond to the methods disclosed in the embodiments, so that the description is simple, and the relevant points can be referred to the description of the method.
The principle and the embodiment of the present invention are explained by applying specific examples, and the above description of the embodiments is only used to help understanding the technical solution and the core idea of the present invention. It should be noted that, for those skilled in the art, without departing from the principle of the present invention, it is possible to make various improvements and modifications to the present invention, and those improvements and modifications also fall within the scope of the claims of the present invention.
Claims (10)
1. A method of link recovery, comprising:
collecting link state information corresponding to each PCIe link;
judging whether the link state information meets a preset state threshold value;
and if not, sending a reset instruction to a PCIe switch chip so that the PCIe switch chip performs unified reset operation on each PCIe link by using a PCIe switch downlink port connected with each PCIe link.
2. The link recovery method of claim 1, before sending the reset command to the PCIe switch chip, further comprising:
acquiring equipment state information of PCIe equipment corresponding to each PCIe link;
and storing each piece of equipment state information.
3. The link recovery method according to claim 2, wherein after the PCIe switch chip performs the unified reset operation on each PCIe link by using a PCIe switch downstream port connected to each PCIe link, the method further comprises:
calling pre-stored state information of each device;
and sending the state information of each device to the corresponding PCIe device through each target PCIe link obtained through recovery.
4. The link recovery method of claim 1, wherein collecting link state information corresponding to each PCIe link includes:
collecting link speeds corresponding to the PCIe links respectively;
judging whether each link state information meets a preset state threshold value or not, including:
and judging whether the link speeds meet a preset speed threshold value.
5. The link recovery method of claim 1, wherein collecting link state information corresponding to each PCIe link comprises:
collecting link bandwidths corresponding to the PCIe links respectively;
judging whether each link state information meets a preset state threshold value or not, including:
and judging whether the bandwidth of each link meets a preset bandwidth threshold value.
6. The link recovery method according to any one of claims 1 to 5, wherein the PCIe switch chip performs a unified reset operation on each PCIe link by using a PCIe switch downstream port connected to each PCIe link, and the method includes:
the PCIe switch chip utilizes the PCIe switch downlink port to send an enable reset signal lasting for a preset time to each PCIe link, and the unified reset operation is carried out on each PCIe link.
7. A link recovery apparatus, comprising:
the link information acquisition module is used for acquiring link state information corresponding to each PCIe link;
the judging module is used for judging whether the link state information meets a preset state threshold value;
and the reset module is used for sending a reset instruction to a PCIe switch chip when determining that the link state information which does not meet the preset state threshold exists in the link state information, so that the PCIe switch chip performs unified reset operation on the PCIe links by using PCIe switch downlink ports connected with the PCIe links.
8. The link recovery apparatus according to claim 7, further comprising:
the device information acquisition module is used for acquiring the device state information of the PCIe devices corresponding to the PCIe links before sending a reset instruction to the PCIe switch chip;
and the information storage module is used for storing the state information of each device.
9. A link recovery device, comprising:
a memory for storing a computer program;
a processor for implementing the steps of the link recovery method according to any one of claims 1 to 6 when executing said computer program.
10. A computer-readable storage medium, characterized in that a computer program is stored on the computer-readable storage medium, which computer program, when being executed by a processor, carries out the steps of the link recovery method according to any one of claims 1 to 6.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011301997.6A CN112463445B (en) | 2020-11-19 | 2020-11-19 | Link recovery method, device, equipment and computer readable storage medium |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011301997.6A CN112463445B (en) | 2020-11-19 | 2020-11-19 | Link recovery method, device, equipment and computer readable storage medium |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112463445A CN112463445A (en) | 2021-03-09 |
| CN112463445B true CN112463445B (en) | 2022-07-22 |
Family
ID=74836651
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011301997.6A Active CN112463445B (en) | 2020-11-19 | 2020-11-19 | Link recovery method, device, equipment and computer readable storage medium |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112463445B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN118193289B (en) * | 2024-03-21 | 2024-08-20 | 无锡众星微系统技术有限公司 | Method and device for recovering PCIe configuration space |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106326160A (en) * | 2015-06-26 | 2017-01-11 | 华为技术有限公司 | Processing system and processing method |
| CN110008164A (en) * | 2019-04-12 | 2019-07-12 | 苏州浪潮智能科技有限公司 | A kind of NTB link management method, system and relevant apparatus |
| CN111371582A (en) * | 2018-12-26 | 2020-07-03 | 大唐移动通信设备有限公司 | PCIE link fault processing method and device |
-
2020
- 2020-11-19 CN CN202011301997.6A patent/CN112463445B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106326160A (en) * | 2015-06-26 | 2017-01-11 | 华为技术有限公司 | Processing system and processing method |
| CN111371582A (en) * | 2018-12-26 | 2020-07-03 | 大唐移动通信设备有限公司 | PCIE link fault processing method and device |
| CN110008164A (en) * | 2019-04-12 | 2019-07-12 | 苏州浪潮智能科技有限公司 | A kind of NTB link management method, system and relevant apparatus |
Also Published As
| Publication number | Publication date |
|---|---|
| CN112463445A (en) | 2021-03-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP1703395A2 (en) | Multiprocessor system with a management processor | |
| KR20080016685A (en) | Point-to-point link negotiation method and apparatus | |
| CN107038137B (en) | Hot-plug equipment and method | |
| CN103491134A (en) | Container monitoring method and device and agency service system | |
| CN113359968B (en) | Method, system, device and medium for resetting PCIE (peripheral component interface express) device based on ARM (advanced RISC machine) platform | |
| CN112463445B (en) | Link recovery method, device, equipment and computer readable storage medium | |
| CN115793963A (en) | Hard disk fault processing method, device, equipment and storage medium | |
| CN111984573A (en) | Resetting method of PCIE Switch expansion chip of controller | |
| CN114826962A (en) | Link fault detection method, device, equipment and machine readable storage medium | |
| CN116560889A (en) | Data link management method, device, computer equipment and storage medium | |
| CN106131241A (en) | A kind of method for connecting network, device and mobile terminal | |
| CN111417034A (en) | Switch and hot plug method, device and system for switch board card thereof | |
| CN114168071A (en) | Distributed cluster capacity expansion method, distributed cluster capacity expansion device and medium | |
| CN111124818B (en) | Monitoring method, device and equipment for Expander | |
| CN101686119A (en) | Method, device and system of communication between single boards | |
| CN117033277A (en) | Single-wire communication control device and data processing method | |
| CN114880266B (en) | Fault processing method and device, computer equipment and storage medium | |
| CN101369238A (en) | Exception monitoring and reset processing method for USB equipment | |
| CN111177028B (en) | Method and equipment for dynamic multi-level caching | |
| CN112527719A (en) | JBOF connection method, device and system based on PCIe link | |
| CN112463521B (en) | Fault-tolerant method and device for improving reliability of serial high-speed bus equipment | |
| CN115941531B (en) | Network original message extraction method based on newly added kernel driving module | |
| CN104077198A (en) | Doorbell (DB) recovery method and device and input/output (I/O) device comprising DB recovery device | |
| CN115203116B (en) | AXI bus transmission method, system and chip | |
| CN113672537B (en) | SATA (Serial advanced technology attachment) equipment hot plug management method and device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |