CN112379868A - Programming method for network data packet processing based on reconfigurable chip - Google Patents
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Abstract
The invention provides a programming method for processing a network data packet based on a reconfigurable chip, which respectively designs the following three program modules according to the processing logic of the data packet: the data packet receiving program module is used for realizing the receiving and the storage of the data packet; the data packet processing program module is used for designing a corresponding callback function according to the data packet processing requirement so as to generate corresponding configuration information for the reconfigurable chip, and therefore the data packet is processed by configuring the processing logic of the reconfigurable chip; and the data packet sending program module is used for sending the data packet after the data packet is processed. The programming method is based on the reconfigurable chip, is specially optimized for the dual programmability of software and hardware of the reconfigurable chip, can embody the superiority of the reconfigurable technology to the maximum extent, and is modular, so that the programming method has the characteristics of high reusability, good code readability and good maintainability.
Description
Technical Field
The invention relates to the technical field of network data packet processing, in particular to a programming method for network data packet processing based on a reconfigurable chip.
Background
The reconfigurable chip has the characteristics of software and hardware dual programming, and the hardware architecture and the function dynamically change in real time along with the change of the software, so the reconfigurable chip is also called as a software defined chip. The emergence of reconfigurable chips opens the channel that one person pursues for a long time, namely 'application definition software and software definition chips' and then 'application definition chips' are realized, and the wide adaptability also makes the reconfigurable chips become powerful competitors for replacing application-specific integrated circuits, programmable devices and classical processors.
To illustrate the uniqueness of a reconfigurable chip, a four-quadrant graph is constructed, for example with software programmability and hardware programmability as two axes, and in particular, with reference to fig. 1, an attribute classification of a dynamically reconfigurable chip is shown. It can be seen that the reconfigurable chip has incomparable advantages over conventional chips.
In the prior art, the programming method for processing the network data packet is based on the traditional chip, so that the characteristics of software and hardware dual programming of the reconfigurable chip and the characteristic of an application definition chip cannot be effectively utilized. Moreover, the code structure of the traditional programming method for processing the network data packet is unclear, and the traditional programming method is inconvenient to be made into a universal programming frame, so that the code reuse rate is low.
Disclosure of Invention
In order to solve the technical problems, the invention discloses a programming method for processing a network data packet based on a reconfigurable chip, which is different from the traditional programming method for processing the network data packet.
In order to achieve the above object, the technical solution of the present invention provides a programming method for processing a network data packet based on a reconfigurable chip, which respectively designs the following three program modules according to the processing logic of the data packet: the data packet receiving program module is used for realizing the receiving and the storage of the data packet; the data packet processing program module is used for designing a corresponding callback function according to the data packet processing requirement so as to generate corresponding configuration information for the reconfigurable chip, and therefore the data packet is processed by configuring the processing logic of the reconfigurable chip; and the data packet sending program module is used for sending the data packet after the data packet is processed.
Further, in the data packet processing program module, the data flow graph is designed by analyzing the algorithm characteristics of the data packet processing requirements, and after the data flow graph is determined, the data flow graph is mapped to a data path of the reconfigurable chip according to the hardware characteristics of the reconfigurable processor, so that corresponding configuration information is generated.
Further, the data packet receiving program module includes a data packet receiving program code and a data packet storing program code, the data packet receiving program code includes a loop function for circularly waiting whether to receive the data packet, and the data packet storing program code is used for storing the data packet after receiving the data packet.
Further, when designing the data packet storage program code, after receiving a data packet, storing a data block of the received data packet to a storage space to be finally placed, and reserving an additional storage space when pre-dividing the storage space for the data packet, so as to reserve the storage space for an additional data block to be added subsequently.
Further, when designing the packet storage program code, pre-partitioning storage space for the received packet based on the received packet and packet processing requirements.
Further, the data packet storage program code includes at least two different storage space pre-partitioning functions to execute the different storage space pre-partitioning functions for different processing requirements, so as to pre-partition the corresponding storage space for different data packet processing requirements.
Further, the programming method further comprises: designing a data packet processing requirement setting program module, wherein the data packet processing requirement setting program module is used for setting the data packet processing requirement when the data packet processing requirement is changed every time, and the data packet processing requirement setting program module is executed before the data packet receiving program module, so that when the data packet receiving program module executes the data packet storage program codes, a corresponding storage space pre-division function is automatically executed based on the set data packet processing requirement.
Further, in the packet processing requirement setting program module, the setting of the packet processing requirement is performed by setting a corresponding identifier, and the packet storage program code automatically determines the storage space pre-partitioning function to be executed based on the identifier.
Furthermore, in the packet sending program module, the data path of the reconfigurable chip is notified to send out the processed packet by writing flag bits corresponding to the length, the base address and the like of the processed packet into the register.
The embodiment of the invention also provides a network data packet processing method based on a reconfigurable chip, which respectively executes the receiving, processing and sending of data packets through the data packet receiving program module, the data packet processing program module and the data packet sending program module which are designed by the programming method.
Drawings
FIG. 1 is a schematic diagram showing attribute classification of a dynamically reconfigurable chip;
FIG. 2 is a schematic diagram showing the basic price of a reconfigurable processor;
FIG. 3 is a design flow diagram of a programming method according to an embodiment of the invention;
fig. 4 is a comparison diagram showing the data structure before and after packet processing;
FIG. 5 is a schematic diagram showing the format of an ESP packet;
FIG. 6 is a design flow diagram of a programming method according to a further embodiment of the present invention.
Detailed Description
The technical solution of the present invention will be further described with reference to the following specific examples, but the present invention is not limited to these examples.
Referring to fig. 2, the basic architecture of a reconfigurable processor or reconfigurable chip is shown. Like a conventional instruction stream driven processor, the reconfigurable processor is also mainly composed of a control unit, a data path, a memory, and an input/output interface. The main difference with the instruction stream processor is that the control unit controls the behavior of the datapath by means of configuration information instead of instructions, the instructions stored in the memory also being replaced by configuration information. Often, the data path is composed of a Processing Element Array (PEA), and the computation function thereof can be reconstructed mainly because the PEA integrates a plurality of basic arithmetic operation units (such as adders, multipliers and the like) and logic operation units (such as and, or, not, xor and the like logic gates) therein. The control unit may select and organize these arithmetic units by configuration information to achieve a specific function.
In order to effectively utilize the characteristics of software and hardware dual programming of a reconfigurable chip or a processor, the embodiment of the invention provides a programming method for network data packet processing based on the reconfigurable chip. As shown in fig. 3, in the embodiment of the present invention, the programming method designs the following three program modules according to the processing logic of the network data packet:
(1) and the data packet receiving program module is used for realizing the receiving and the storage of the data packet.
(2) And (3) a data packet processing program module, configured to design a corresponding callback function according to a processing requirement of the network data packet, so as to generate corresponding configuration information for the reconfigurable chip, so as to process the data packet received in (1) by configuring a processing logic of the reconfigurable chip. The module part is a general callback function, is realized by a user through a reconfigurable chip technology, adds different processing logics according to different application requirements, and reduces the load due to the use of hardware.
(3) And the data packet sending program module is used for finishing sending the data packet after the data packet is processed.
In a general concrete development environment, the program modules (1) and (3) are basically not changed once the development is completed. When different requirements are changed each time, only the callback function in the program module (2) needs to be changed.
Therefore, a universal development framework and a programming method are formed, the code is particularly favorable for multiplexing, and the method is suitable for being used in a reconfigurable chip.
In the data packet processing program module in the step (2), the data flow graph is designed by analyzing the algorithm characteristics of the data packet processing requirements, and after the data flow graph is determined, the data flow graph is mapped to a data path of a reconfigurable processing chip according to the hardware characteristics of a reconfigurable processor, so that corresponding configuration information is generated.
As for (1) the packet reception program module, it may include a packet reception program code which is a round function for round-robin waiting whether or not a packet is received, and a packet storage program code for storing a packet after receiving the packet. The space for storing the data packet may be a storage space in the reconfigurable chip, or a storage space of another external device accessible by the reconfigurable chip.
In the packet sending program module in (3), the data path of the reconfigurable chip is notified to send out the processed packet by writing flag bits corresponding to the length, base address, and the like of the processed packet into a register.
Since a large amount of data copies are often involved in the processing of the data packets, the actual processing performance is affected, and the network data packet processing usually involves variable-length protocol processing. In a further embodiment of the present invention, in the data packet storage program code of the data packet receiving program module in (1), after the data packet is received, according to the characteristics of the processed data packet, the data space is pre-segmented, the data blocks of the data packet are stored in the memory space to be finally stored in advance, and meanwhile, a lower space is reserved for new data blocks to be added, so that it is ensured that no extra copy work is needed in the processing process.
For the sake of easy understanding, the following description will be made by taking an example in which a normal IP packet is encapsulated into an ESP packet. Referring to fig. 4, a comparison of data structures before and after packet processing is shown. As can be seen from fig. 4, the data packet is encrypted in the same memory segment. Two new data segments are then added before and after the encrypted memory, each for storing the other parts of the ESP packet. For a detailed description of ESPs and related principles, see, for example, RFC 2406-IP Encapsulating Security Payload (ESP).
In the above embodiment, the copy operation of the original data packet is not involved, but when the data blocks of the original data packet are copied to the memory, the data space is allocated in advance to prepare for inserting the new data blocks. Thus, in a zero copy manner, encapsulation of a standard ESP packet is completed.
Therefore, the programming method of the present invention also has the following advantages: the data packet is directly processed on the original memory segment, so that the copy work in the memory processing process is reduced as much as possible.
Since the type of the received original data packet may be different during the actual processing of the data packet (e.g., IPV4 packet or IPV6 packet), and the processing requirements may also be changed (e.g., ESP protocol processing requirements, NVGRE, VXLAN protocol processing requirements, etc.), the size (or length) and the insertion position of the additionally inserted data segment before and after the processing of the data packet may also be different.
For ease of understanding, the example of encapsulating IPV4 packets and IPV6 packets into ESP packets, respectively, is given. Referring to fig. 5, the ESP packet formats in transport mode and tunnel mode are shown, respectively. Wherein, fig. 5 (a) shows a packet format of an original IPv4 packet; fig. 5 (b) shows a data packet format after encapsulating IPv4 packets into ESP packets of a transmission mode; fig. 5 (c) shows a data packet format after encapsulating an IPv4 packet into an ESP packet of tunnel mode; fig. 5 (d) shows a packet format of the original IPv6 packet; fig. 5 (e) shows a data packet format after encapsulating IPv6 packets into ESP packets of a transmission mode; fig. 5 (f) shows a packet format after encapsulating the IPv6 packet into an ESP packet in tunnel mode. It will be seen that the length of the additional data segments inserted before and after packet processing, and the insertion location, depend on the original packet received and the particular processing requirements.
In order to meet the requirements of different data packets and processing requirements on storage space, in (1) a data packet storage program code of a data packet receiving program module, after receiving a data packet, a redundant storage space is divided in advance based on the received data packet and specific processing requirements to reserve storage space for an additionally added data segment.
Because the storage spaces which need to be pre-partitioned are different according to different processing requirements, the program code needs to be rewritten according to specific processing requirements each time the processing requirements are changed, in order to reduce the workload of modifying subsequent codes, at least two different storage space pre-partitioning functions (for example, a storage space pre-partitioning function according to the processing requirements of the ESP protocol, a storage space pre-partitioning function according to the processing requirements of the NVGRE protocol, and the like) can be pre-designed in the data packet storage program code so as to execute different storage space pre-partitioning functions according to different processing requirements, thereby meeting the partitioning requirements of different processing requirements on the storage space. In the embodiment, when the processing requirement is changed every time, the corresponding storage space pre-partitioning function can be manually selected and executed, so that the workload of repeatedly writing or modifying codes is saved. It is understood, of course, that the type and number of pre-designed memory space pre-partitioning functions are not particularly limited.
In a further embodiment, in order to ensure that the program code structure is clear, so as to facilitate the reuse of the code, referring to fig. 6, the programming method of the present invention may further include: designing a data packet processing requirement setting program module, wherein the data packet processing requirement setting program module is used for setting the data packet processing requirement when the data packet processing requirement is changed every time, and the data packet processing requirement setting program module is executed before the data packet receiving program module, so that when the data packet receiving program module executes the data packet storage program codes, a corresponding storage space pre-division function is automatically executed based on the set processing requirement.
Specifically, in the packet processing requirement setting program module, the processing requirement can be set by setting the corresponding identifier. For example, for an ESP protocol processing requirement, an identifier a of 1 may be set; for NVGRE protocol processing requirements, the identifier a may be set to 2; for VXLAN protocol processing requirements, identifier a may be set to 3, and so on. It is understood that the identifier a may be set to 1.1 for the transmission mode in the ESP protocol processing requirement, and may be set to 1.2 for the transmission mode in the ESP protocol processing requirement. It should be noted that the type and number of the processing requirements are not particularly limited, and may be flexibly set according to actual requirements.
Therefore, when the program code of the data packet storage is executed subsequently, when the storage space is pre-divided for the received data packet, the identifier set in the program module for setting the data packet processing requirement is firstly identified, so that the storage space pre-division function needing to be executed is automatically judged according to the identifier to divide the storage space of the data packet. For example, when the identifier a is determined to be 1.1, the memory space pre-partition function Alldivide _ memory may be executed to pre-partition the memory space for the received packet according to the ESP packet format in the transmission mode; when the outage identifier a is 2, a storage space pre-partition function A2divide _ memory may be performed to pre-partition the storage space for the received data packet in NVGRE data packet format.
Through the embodiment, the processing requirement setting program module is independently added, so that when different processing requirements are changed each time, only the identifier in the module needs to be changed, other program codes do not need to be modified, and the program code reuse rate is greatly improved.
Different from the traditional network data packet processing programming method, the programming method is based on the reconfigurable chip and specially optimizes the dual programmability of software and hardware of the reconfigurable chip, thereby reflecting the superiority of the reconfigurable technology to the greatest extent.
The invention provides a modular programming method which has the characteristics of high reusability, good code readability and good maintainability because of being modular.
In addition, the programming method of the invention is zero copy of the data packet, and the data packet is directly processed on the memory of the original data packet, so that the workload of copying the data can be greatly reduced.
The invention is based on reconfigurable chip, its advantages and functions mainly include:
1. the invention is based on the reconfigurable chip, can fully utilize the characteristics of software and hardware dual programming of the reconfigurable chip, and realizes the purpose of 'application definition chip';
2. the data packet receiving and sending are completely realized by hardware, and meanwhile, the data packet processing is responsible for the reconfigurable chip, so that the load is reduced, and the processing performance is improved;
3. the invention has zero copy to the original data in the processing process, and can segment the insertion position of the data packet when receiving the data packet, thereby directly processing the data packet on the memory space of the original data packet without involving excessive data copy and well ensuring the processing performance;
4. the method is particularly suitable for the quick programming of variable length protocols before and after data packet processing through a programming frame and an insertion position segmentation technology of a received packet, is a universal frame, and has clear code structure and high code reuse rate.
In addition, the embodiment of the invention also provides a network data packet processing method based on a reconfigurable chip, which respectively executes the receiving, processing and sending of data packets through the data packet receiving program module, the data packet processing program module and the data packet sending program module which are designed by the programming method.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various changes and modifications can be made without departing from the inventive concept of the present invention, and these changes and modifications are all within the scope of the present invention.
Claims (10)
1. A programming method for processing network data packets based on a reconfigurable chip is characterized in that the following three program modules are respectively designed according to the processing logic of the data packets:
the data packet receiving program module is used for realizing the receiving and the storage of the data packet;
the data packet processing program module is used for designing a corresponding callback function according to the data packet processing requirement so as to generate corresponding configuration information for the reconfigurable chip, and therefore the data packet is processed by configuring the processing logic of the reconfigurable chip;
and the data packet sending program module is used for sending the data packet after the data packet is processed.
2. The programming method according to claim 1, wherein in the packet processing program module, a data flow graph is designed by analyzing algorithm characteristics of packet processing requirements, and after the data flow graph is determined, the data flow graph is mapped onto a data path of the reconfigurable chip according to hardware characteristics of the reconfigurable processor, so as to generate corresponding configuration information.
3. The programming method according to claim 1 or 2, wherein the packet reception program module includes a packet reception program code including a round-robin function for circularly waiting whether a packet is received or not and a packet storage program code for storing a packet after receiving a packet.
4. The programming method according to claim 3, wherein in designing the packet storage program code, upon receiving a packet, storing a block of the received packet to a storage space to be finally placed, and reserving an additional storage space when the storage space is pre-divided for the packet, to reserve the storage space for an additional block to be subsequently added.
5. The programming method of claim 4, wherein the packet storage program code is designed to pre-partition storage space for a received packet based on the received packet and packet processing requirements.
6. The programming method according to claim 5, wherein the packet storage program code comprises at least two different memory pre-partitioning functions to perform the different memory pre-partitioning functions for different processing requirements, thereby pre-partitioning the corresponding memory for different packet processing requirements.
7. The programming method according to claim 6, further comprising: designing a data packet processing requirement setting program module, wherein the data packet processing requirement setting program module is used for setting the data packet processing requirement when the data packet processing requirement is changed every time, and the data packet processing requirement setting program module is executed before the data packet receiving program module, so that when the data packet receiving program module executes the data packet storage program codes, a corresponding storage space pre-division function is automatically executed based on the set data packet processing requirement.
8. The programming method according to claim 7, wherein in the packet processing requirement setting program module, setting of the packet processing requirement is performed by setting a corresponding identifier, and the packet storage program code automatically determines the memory space pre-partitioning function to be executed based on the identifier.
9. The programming method according to any one of claims 1 to 2 and 4 to 8, wherein in the packet transmission program module, the data path of the reconfigurable chip is notified to transmit the processed packet by writing flag bits corresponding to the length, base address, and the like of the processed packet into a register.
10. A method for processing network packets based on reconfigurable chips, characterized in that the packet reception, processing and transmission are respectively performed by a packet reception program module, a packet processing program module and a packet transmission program module designed by the programming method according to any one of claims 1 to 9.
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