CN112650709A - On-site programmable gate array, configuration method and system - Google Patents

Abstract

A programmable semiconductor system includes a programmable integrated circuit and a memory device capable of implementing multiple boot processes with backup default configurations. In one embodiment, the programmable integrated circuit includes a configurable logic block, a routing connection array, and a configuration memory to perform logic functions. The storage device includes a first memory and a second memory. The first memory stores user configuration data representing user-defined logic functions, and the second memory stores a backup default page containing default configuration data for programming or starting the programmable integrated circuit to default settings when the user configuration data fails to start or program the programmable integrated circuit. In one aspect, the user configuration data includes an address of the second memory containing default configuration data.

Description

On-site programmable gate array, configuration method and system

Technical Field

Exemplary embodiments of the present application relate to the field of programmable semiconductor devices for logic operations in computer hardware and software. More particularly, exemplary embodiments of the present application relate to methods, configurable semiconductor devices, and systems for enhancing the integrity of Field-Programmable Gate arrays (FPGAs) or Programmable Logic Devices (PLDs) during configuration.

Background

With the increasing popularity of digital communication, Artificial Intelligence (AI), Internet of Things (IoT) and/or robotic control, there is an increasing demand for fast, flexible, and efficient hardware and/or semiconductors with processing capabilities. To meet this demand, high-speed, flexible semiconductor chips are often more desirable. An existing way to meet this need is to use Application-Specific Integrated Circuits (ASICs). The approach of using application specific integrated circuits has the disadvantage of lacking flexibility while consuming a lot of resources.

Another approach that has become increasingly popular is to utilize Programmable Semiconductor Devices (PSDs), such as Programmable Logic Devices (PLDs) or Field Programmable Gate Arrays (FPGAs). The programmable semiconductor device is characterized in that: after the programmable semiconductor device is manufactured, an end user is allowed to program and/or reprogram one or more desired functions to suit the user's application.

However, the disadvantages of the existing field programmable gate arrays or programmable logic devices are: are vulnerable to corruption when dealing with defective and/or corrupted configuration data.

Disclosure of Invention

One embodiment of the present application discloses a Programmable Semiconductor System (PSS) capable of enhancing programmability and/or integrity of a Programmable Semiconductor device, also referred to as a Programmable Integrated Circuit (PIC), through Multi-boot with Backup Default Configuration (MBC) operations. In one aspect, a programmable integrated circuit includes configurable Logic Blocks (LBs), an array of routing connections, and configuration memory that performs user-defined Logic functions. In one example, each logic block includes one or more look-up Tables (LUTs) configured to provide one or more output signals based on a set of input signals and configuration data stored in a configuration memory. The application can enhance the reliability of the programmable integrated circuit through multiple boot operations with backup default configuration functions.

The programmable semiconductor system includes a programmable integrated circuit and a memory device, wherein the memory device further includes a first memory and a second memory. The first memory stores user-defined configuration data for programming or booting the programmable integrated circuit; the second memory stores a Backup Default Page (BDP) or a Backup Default Image (BDI). In one aspect, the backup Default page contains manufacturer-supplied Default Configuration Data (DCD) to program or boot the programmable ic when the user-defined Configuration Data fails to boot the programmable ic. In another embodiment, the user-defined configuration data comprises a memory address pointing to a second memory containing alternative configuration data, such as default configuration data.

In one embodiment, the programmable semiconductor system further includes a Dual-Mode Port (DMP) to provide Dual functionality for information transfer. In one aspect, a dual mode port is operable to process configuration data during a configuration mode. Alternatively, the dual mode port may be operable to process user data during a logical mode of operation.

Other features and advantages of exemplary embodiments of the present invention will be apparent from the following detailed description, figures and claims.

Drawings

Exemplary embodiments of the present invention will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the invention, which, however, should not be taken to limit the specific embodiments, but are for explanation and understanding only.

FIGS. 1A-1B are block diagrams illustrating a Programmable Semiconductor Device (PSD) capable of enhancing its integrity and/or reliability using multiple boot processes with backup default configurations in accordance with one embodiment of the present invention;

FIG. 2 is a block diagram illustrating routing logic or routing fabric containing a programmable interconnect array capable of routing a Backup Default (BD) bit stream in accordance with one embodiment of the present invention;

FIGS. 3A-3B are block diagrams illustrating a Programmable Semiconductor System (PSS) including a storage device and a field Programmable gate array for implementing a multiple boot process with a backup default configuration according to one embodiment of the invention;

4A-4B illustrate another embodiment of a programmable semiconductor system or processing system including a memory device and a field programmable gate array to implement a multiple boot process with backup default configuration functionality, according to one embodiment of the present invention;

FIGS. 5A-5B are block diagrams illustrating a programmable semiconductor system including a programmable integrated circuit capable of multiple boot or dual boot operations according to one embodiment of the invention;

FIG. 6A is a block diagram illustrating a programmable semiconductor system including a programmable integrated circuit capable of multiple boot or dual boot operations according to one embodiment of the invention;

FIG. 6B is a block diagram illustrating a programmable semiconductor system including a Dual-Mode Port (DMP) for implementing configuration operations and user data operations, in accordance with one embodiment of the present invention;

FIG. 7 is a system or computer that uses a programmable semiconductor system and/or programmable integrated circuit to provide multiple boot processes with backup default configurations to enhance programmability of the programmable integrated circuit, according to one embodiment of the present invention;

FIG. 8 is a block diagram illustrating various applications of a programmable semiconductor system or programmable semiconductor device containing a field programmable gate array or programmable logic device capable of implementing a multiple boot process with backup default configuration functionality to enhance overall reliability, according to one embodiment of the invention;

FIG. 9 is a flow diagram illustrating a configuration of a programmable integrated circuit implementing a multiple boot process with a backup default configuration according to one embodiment of the invention;

FIG. 10 is a logic flow diagram illustrating a process for configuring a programmable integrated circuit through a multiple boot process with a backup default configuration in accordance with one embodiment of the present invention; and

FIG. 11 is a logic flow diagram illustrating a process for performing a configuration operation or a data operation through a dual mode port in accordance with one embodiment of the present invention.

Detailed Description

Embodiments of the present invention disclose a method and/or apparatus to provide a Programmable Semiconductor Device (Programmable Semiconductor Device PSD) or a Programmable Integrated Circuit (Programmable Integrated Circuit PIC) configured to enhance reliability through multiple boot operations with backup default configurations.

The following detailed description is intended to provide an understanding of one or more embodiments of the invention. Those of ordinary skill in the art will realize that the following detailed description is illustrative only and is not intended to be in any way limiting. Other embodiments will be apparent to those skilled in the art having the benefit of this disclosure and/or this description.

In the interest of clarity, not all of the routine features of the implementations described herein are shown and described. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific decisions may be made to achieve the developers' specific goals, such as compliance with application-and business-related constraints, which will vary from one implementation to another and from one developer to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking of engineering for those of ordinary skill in the art having the benefit of this disclosure.

The various embodiments of the invention illustrated in the drawings are not necessarily drawn to scale. On the contrary, the dimensions of the various features may be exaggerated or minimized for clarity. In addition, some of the drawings may be simplified for clarity. Accordingly, not all components of a given apparatus (e.g., device) or method may be depicted in a figure. The same reference indicators will be used throughout the drawings and the following detailed description to refer to the same or like parts.

In accordance with embodiments of the present invention, the components, process steps, and/or data structures described herein may be implemented using various types of operating systems, computing platforms, computer programs, and/or general purpose machines. Moreover, those of ordinary skill in the art will recognize that devices of a less general purpose nature, such as hardware devices, Field-Programmable Gate Arrays (FPGAs), Application-Specific Integrated Circuits (ASICs), and the like, may also be used without departing from the scope and spirit of the inventive concepts disclosed herein. If the method comprising a series of process steps is implemented by a computer or a machine, and the process steps can be stored as a series of instructions readable by the machine, they can be stored on a tangible medium such as a computer storage device, for example but not limited to: magnetoresistive Memory (MRAM), phase change Memory or Ferroelectric Memory (FeRAM), Read Only Memory (ROM), Programmable Read-Only Memory (PROM), Electrically Erasable Programmable Read-Only Memory (EEPROM), Jump Drive (Jump Drive), magnetic storage medium (e.g., magnetic tape, magnetic disk Drive, etc.), optical storage medium (e.g., compact disc Read-Only Memory, digital compact disc Read-Only Memory, paper card, paper tape, etc.), and other known types of program Memory.

The terms "system" or "device" are used generically herein to describe any number of components, elements, subsystems, devices, packet switch elements, packet switches, access switches, routers, networks, computer and/or communication devices or mechanisms, or combinations of components thereof. The term "computer" includes processors, memories, and buses capable of executing instructions, where a computer refers to a computer or a cluster of computers, a personal computer, a workstation, a mainframe, or a combination of computers.

In one embodiment, a Programmable Semiconductor System (PSS) is configured to enhance the programmability and/or integrity of a Programmable Semiconductor device or Programmable integrated circuit through Multi-boot with Backup Default Configuration (MBC) operations. In one aspect, a programmable integrated circuit includes a configurable logic block, a routing connection array, and a configuration memory that performs user-defined logic functions. In one example, each logic block contains a look-up table configured to provide one or more output signals based on a set of input signals and configuration data stored in a configuration memory. The programmable semiconductor system includes a programmable integrated circuit and a memory device, wherein the memory device further includes a first memory and a second memory. The first memory stores user-defined configuration data for programming or booting the programmable integrated circuit; the second memory stores a Backup Default Page (BDP) or a Backup Default Image (BDI). In one aspect, the backup Default page contains manufacturer-supplied Default Configuration Data (DCD) for programming or booting the programmable integrated circuit when the user-defined Configuration Data fails to boot the programmable integrated circuit. In another embodiment, the user-defined configuration data comprises a memory address pointing to a second memory containing alternative configuration data, such as default configuration data.

Fig. 1A is a block diagram illustrating a programmable semiconductor device capable of enhancing its integrity and/or reliability using a multiple boot-up (MBC) process with a backup default configuration, in accordance with one embodiment of the present invention. A Programmable semiconductor Device, also known as a field Programmable gate array, a Programmable integrated circuit and/or a Programmable Logic Device (Programmable Logic Device PLD), includes MBC modules 120 that enable multiple boot processes with backup default configurations. The function of multiple boots with backup default configuration is to enhance the reliability of the programmable integrated circuit through multiple restart or configuration procedures. It should be noted that the basic concept of the exemplary embodiments of the present invention does not change, either by adding or removing one or more modules (circuits or elements) from the programmable semiconductor device 170.

The Programmable semiconductor device comprises an array of configurable logic Blocks 180, with Input/Output Blocks (IOs) 182 and Programmable Interconnect Resources (PIR) 188 surrounding the configurable logic Blocks 180, the Programmable Interconnect Resources 188 comprising vertical interconnects and horizontal interconnects extending between the logic Blocks 180 and rows and columns of the Input/Output Blocks 182. The Programmable interconnect resources 188 also include Interconnect Array Decoders (IADs) or Programmable Interconnect Arrays (PIAs). It should be noted that the terms "programmable interconnect resource", "interconnect array decoder", "programmable interconnect array" are used interchangeably hereinafter.

In one example, each logic block includes a programmable combinational circuit and a selectable output register programmed to implement at least a portion of the user logic function. Programmable interconnects, connections, or channels of interconnect resources are signal paths created between logic blocks 180 using various switches to perform logic functions. Each input/output block 182 is programmable to selectively use one input/output pin (not shown) of the programmable semiconductor device.

In one embodiment, the Programmable integrated circuit may be Partitioned into a plurality of Programmable Partitioned areas (PPRs) 172, wherein each Programmable partition area 172 includes a portion of logic blocks 180, some Programmable interconnect resources 188, and input/output blocks 182. A benefit of organizing the programmable integrated circuits into multiple programmable partition regions 172 is to optimize management of storage capacity, power supply, and/or network output.

A bitstream is a binary sequence (or file) containing programming information or data for a programmable integrated circuit, field programmable gate array, or programmable logic device. The bitstream is created to reflect the user's logical functions and certain control information. In order for a field programmable gate array or programmable logic device to function properly, at least a portion of the registers or flip-flops in the field programmable gate array need to be programmed or configured before they can function. It should be noted that the bitstream is used as input configuration data for the field programmable gate array.

The benefit of using multiple boot processes with backup default configuration is to enhance the reliability of the programmable integrated circuit or field programmable gate array during configuration.

FIG. 1B is a block diagram illustrating a programmable integrated circuit containing multiple regions capable of using multiple boot processes with backup default configurations to enhance its reliability, according to one embodiment of the invention. To simplify the above discussion, the terms "programmable semiconductor device," "programmable integrated circuit," "field programmable gate array," "programmable logic device" all refer to the same or similar devices, and are used interchangeably hereinafter. The programmable integrated circuit 100 includes a plurality of programmable partition regions 102 and 108, a programmable interconnect array 150, and a region input/output port 166. The programmable partition area 102 and 108 further includes a control unit 110, a memory 112, and a logic block 116. It is noted that the control unit 110 may be configured as a single control unit, and likewise, the memory 112 may be configured as a single memory to store the configuration. It should be noted that the basic concepts of the exemplary embodiments of this invention may be altered without changing the basic concepts of the exemplary embodiments of this invention by adding or removing one or more blocks (circuits or elements) from the programmable integrated circuit 100.

The Logic block 116, also referred to as a Configurable Function Unit (CFU), includes a plurality of Logic Array Blocks (LABs) 118, also referred to as Configurable Logic Unit (CLU). For example, each Logic array block 118, among other circuits, may be further organized to include a set of programmable Logic Elements (Logic Elements LEs), Configurable Logic Slices (Configurable Logic Slices CLS), or macrocells (not shown in fig. 1B). In one example, each logic array block may include 32-512 programmable logic elements. Input/output pins (not shown in FIG. 1B), logic array blocks, and logic elements are connected by the programmable interconnect array 150 and/or other buses (e.g., bus 162 or 114) to enable communication between the programmable interconnect array 150 and the programmable partition area 102 and 108.

Each logic element includes programmable circuitry such as a product term matrix, a lookup table, and/or a register. Logic elements are also referred to as cells (cells), Configurable Logic blocks (Configurable Logic Block CLBs), Configurable Logic slices, Configurable functional units, macrocells, and the like. Each logic element may be independently configured to perform sequential and/or combinational logic operations. It should be noted that the basic concept of a programmable semiconductor device does not change, either by adding or removing one or more modules and/or circuits from the programmable semiconductor device.

The control unit 110, also referred to as configuration logic, may be one single control unit. For example, the control unit 110 manages and/or configures individual logic elements in the logic array block 118 based on configuration information stored in the memory 112. It should be noted that some input/output ports or input/output pins are configurable, and thus may be configured as input pins and/or output pins. Some of the input/output pins are programmed as bi-directional input/output pins, while other input/output pins are programmed as uni-directional input/output pins. A control unit, such as unit 110, is used to process and/or manage programmable semiconductor device operations in accordance with the system clock signal.

The logic block 116 includes a plurality of logic array blocks that can be programmed by an end user. Each logic array block contains a plurality of logic elements, wherein each logic element further comprises one or more Lookup Tables (LUTs) and one or more registers (or D-type flip-flops or latches). Depending on the application, the logic element may be configured to perform user-specific functions based on a predefined library of functions implemented by the configuration software. In some applications, the programmable semiconductor device also includes a set of fixed circuits for performing specific functions. For example, the fixed circuitry includes, but is not limited to, a processor, a Digital Signal Processing (Digital Signal Processing DSP) unit, a wireless transceiver, and the like.

The programmable interconnect array 150 is coupled to the logic block 116 through various internal buses, such as buses 114 or 162. In some embodiments, bus 114 or bus 162 is part of programmable interconnect array 150. Each bus includes channels or conductors for transmitting signals. It should be noted that the terms "channel," "routing channel," "wire," "bus," "connection," and "interconnect" all refer to the same or similar connections and are used interchangeably herein. The programmable interconnect array 150 may also be used to receive and/or transmit data directly or indirectly from/to other devices through input/output pins and logic array blocks.

Memory 112 includes a plurality of memory cells located on a programmable partition area. In addition, the memory 112 may be combined into a single memory cell in a programmable semiconductor device. In one embodiment, memory 112 is a non-volatile memory storage unit used for both configuration and user memory. The non-volatile memory storage unit may be, but is not limited to, a magnetic random access memory, a flash memory, a ferroelectric random access memory, and/or a phase change memory. Depending on the application, a portion of the memory 112 may be designated, allocated, or configured as a Block RAM (BRAM) for storing large amounts of data in a programmable semiconductor device.

The programmable semiconductor device includes a large number of programmable logic blocks 116 or configurable logic blocks 116 interconnected by a programmable interconnect array 150, where each programmable logic block is further divided into a plurality of logic array blocks 118. Each logic array block 118 also includes a number of look-up tables, multiplexers (multiplexer mux), and/or registers. During configuration, the user programs a truth table for each look-up table to implement the desired logic function. It should be noted that each Logic array block may be further organized to include a plurality of Logic Elements (Logic Elements LEs), which may be considered Configurable Logic cells (Configurable Logic Cell CLC) or Configurable Logic slices. For example, a four-input (16-bit) lookup table receives a lookup table input from a routing fabric (not shown in FIG. 1B). Based on a truth table programmed into a lookup table during configuration of a configuration programmable semiconductor device, a combined output is generated from the programmed truth table of the lookup table according to a logic value input to the lookup table. The combined output is then latched or buffered into a register or flip-flop before the end of the clock cycle.

In one embodiment, the control unit 110 includes a multi-boot module 120(MBC module) having a backup default configuration. It should be noted that multiple boot modules 120 having a backup default configuration may be placed anywhere within a programmable integrated circuit or programmable semiconductor device to perform a multiple boot process having a backup default configuration. The function of the multiple boot module 120 with the backup Default Configuration is to use user-defined Configuration Data or Default Configuration Data (DCD) to control the Configuration process or restart the process. The benefit of using multiple boot processes with backup default configurations is to recover or restore the programmable integrated circuit or programmable semiconductor device from corrupted or erroneous configuration data.

Fig. 2 is a block diagram illustrating a routing logic or routing fabric 200 containing a programmable interconnect array capable of routing Backup Default (BD) bit streams, according to one embodiment of the invention. The routing logic or routing fabric 200 includes control logic 206, programmable interconnect array 202, input/output pins 230, and clock unit 232. Control logic 206 is similar to the control unit shown in FIG. 1B, providing various control functions including channel allocation, different input/output standards, and clock management. The control logic 206 includes volatile memory, non-volatile memory, and/or a combination of volatile and non-volatile memory devices for storing information such as configuration data. In one embodiment, the control logic 206 is integrated into the programmable interconnect array 202. It should be noted that the basic concepts of the exemplary embodiments of this invention may be altered by the addition or removal of one or more modules (circuits or elements) from the routing logic or routing structure 200.

An input/output pin 230, connected to the programmable interconnect array 202 by a bus 231, includes a plurality of programmable input/output pins configured to receive and/or transmit signals to external devices. For example, each programmable input/output pin may be configured as an input pin, an output pin, and/or a bi-directional pin. Depending on the application, the input/output pins 230 may be integrated in the control logic 206.

In one example, a clock unit 232 coupled to the programmable interconnect array 202 via a bus 233 receives various clock signals from other components, such as a clock tree circuit or a global clock oscillator. In one example, the clock unit 232 generates clock signals in response to a system clock and a reference clock to enable input/output communications. Depending on the application, for example, clock unit 232 provides a clock signal, including a reference clock, to programmable interconnect array 202.

In one aspect, the programmable interconnect array 202 is organized into an array architecture including sets of channels 210 and 220, bus 204, and input/ output buses 114, 124, 134, 144. The lane groups 210, 220 process routing information between logic blocks based on the configuration of the programmable interconnect array. The channel groups may also communicate with each other through an internal bus or connection such as bus 204. The channel group 210 also includes an Interconnect Array Decoder (IAD) 212 and 218. Channel group 220 includes four interconnect array decoders 222-228. The function of the interconnect array decoder is to provide configurable routing resources for data transmission.

The interconnect array decoder, such as interconnect array decoder 212, includes routing multiplexers or selectors to route signals between input/output pins, feedback outputs, and/or logic array block inputs to their destinations. For example, an interconnect array decoder may include up to 36 multiplexers, which may be placed in four blocks, where each block contains nine multiplexers. It should be noted that the number of interconnected array decoders within each lane group is a function of the number of logic elements within the logic array block.

In one embodiment, interconnect array 202 is programmable to specify a particular interconnect array decoder, such as interconnect array decoder 218, to facilitate routing of configuration data. For example, interconnect array decoder 218 is designated to handle connection and/or routing configuration information during bitstream transmission. It should be noted that additional interconnected array decoders may be allocated to handle the transmission of configuration data, including the backup default bit stream.

The benefit of using interconnect array decoder 218 as a designated bit stream routing within a programmable interconnect array is that the transfer of configuration bit streams between storage and configuration memories within a programmable integrated circuit or field programmable gate array is determined.

FIG. 3A is a block diagram illustrating a Programmable Semiconductor System (PSS) 300 including a memory device and a Programmable integrated circuit for executing multiple boot processes with backup default configurations in accordance with one embodiment of the present invention. Programmable semiconductor system 300 includes a memory device 306, a programmable integrated circuit (or field programmable gate array) 302, and a bus 308. Bus 308 may be an internal bus between chips fabricated on a module. Alternatively, bus 308 may be a separate bus, such as Joint Test Action Group (JTAG), that operates between devices. It should be noted that the basic concepts of the exemplary embodiments of the present invention do not change as one or more modules (circuits or elements) are added or removed from the programmable semiconductor system 300.

Programmable semiconductor systems may also be referred to as configurable semiconductor modules, which comprise a plurality of chips and/or Integrated Circuits (ICs). For example, the programmable semiconductor system is a semiconductor module or semiconductor card that can house a programmable integrated circuit 302 and a memory device 306 connected or connected by an internal bus 308. Alternatively, the programmable semiconductor System may be a System-On-Chip (SOC) that includes an embedded programmable integrated circuit 302 and a memory device 306 connected by an On-Chip bus 308. With embedded wireless functionality, programmable semiconductor systems may be used to perform a variety of applications including, but not limited to, Information Appliance (IA) systems, autopilots, drones, boats, security monitoring, industrial operations, robotic operations, household appliances, and the like.

In one aspect, a programmable integrated circuit or programmable semiconductor device includes a programmable logic array 330, a Configuration memory 322, a verification component 328, an Address of Configuration Data (ACD) unit 326, and a multiplexer 324. The programmable logic array also includes a plurality of configurable logic blocks 332, the configurable logic blocks 332 capable of being programmed to perform a set of user-specific functions. In one aspect, the programmable integrated circuit further includes an array of configurable routing connections that connect the various logic blocks to help perform the functions desired by the user. In one embodiment, Configuration memory 322 is used to store Configuration Data (CD) used to program configurable logic block 332 to perform user-defined logic functions. For example, each configurable logic block includes one or more look-up tables to provide one or more output signals based on a set of input signals and configuration data in configuration memory 322.

In one embodiment, the configuration Memory 322 may be a volatile Memory or a non-volatile Memory (NVM). For example, volatile Memory includes Random-Access Memory (RAM) or Static Random-Access Memory (SRAM). Non-volatile Memory includes flash Memory, magnetic Random Access Memory, phase change Memory, and/or Ferroelectric Random Access Memory (FeRAM). In one aspect, configuration memory 322 is organized to store a data bit stream representing configuration data to configure various configurable elements, such as logic blocks and/or look-up tables and arrays of configurable routing connections. The function of the configuration memory 322 is to store a user-provided or user-defined configuration bitstream to facilitate the implementation of user-defined logic functions. In one embodiment, the configuration memory 322 may be organized into multiple sections or portions capable of storing multiple versions of configuration data.

In one embodiment, the verification component 328 is used to verify that the configuration data or bit stream in the configuration storage 322 is working properly. For example, a verification component 328 coupled to the logic block can verify and validate the authenticity and integrity of the recently loaded configuration data. For example, validation component 328 can validate and verify using a set of predefined verification codes. It should be noted that the verification code may be provided by the user. Alternatively, the verification code may be provided by the manufacturer of the programmable integrated circuit or the field programmable gate array. If the verification component 328 detects erroneous or corrupted configuration data, a Backup Default (BD) initiator is activated. Erroneous configuration data means that the configuration data is generated incorrectly or that the configuration data is for other logical functions. Corrupted configuration data indicates that the configuration data may be corrupted during transmission through wired or wireless communication.

Upon detection of erroneous or corrupted configuration data, a backup default initiator is activated to issue a backup default signal indicating that new configuration data is needed or required. The backup default initiator, not shown in fig. 3A, may be part of the verification component 328 or a separate element. In one embodiment, the backup default signal is fed to the next configuration data multiplexer 324 to load or reload new configuration data from the storage device 306 according to the memory location addressed by the configuration data address location 326.

The configuration data address unit 326 retrieves or retrieves the storage location of the next configuration data pointed to by the memory address. In one embodiment, the memory address of the next configuration data is extracted from the current configuration data stored in configuration memory 322. Alternatively, if the Default Configuration Data (DCD) is the next restart code or reconfiguration code, the storage address of the next Configuration Data may be obtained from the backup Default address stored in the embedded memory.

The storage device 306 includes user memory 304 and a Backup Default Page (BDP) 318. The user memory 304 includes a plurality of memory segments M1-Mn 310-316 capable of storing multiple copies or versions of user-defined configuration data. For example, a user may generate and provide primary configuration data, secondary configuration data, and golden configuration data, which may be loaded into memory segments M1310, M2312, and Mn 316, respectively. Alternatively, the user memory 304 is configured to store at least one user configuration data to provide at least a portion of the configuration data in the configuration memory 322. It should be noted that the storage 306 may be volatile memory, non-volatile memory, or a combination of volatile and non-volatile memory.

In one aspect, backup default page 318 is configured to store default configuration data provided or supplied by the manufacturer of the programmable integrated circuit or field programmable gate array. Default configuration data is encoded by the manufacturer for rebooting the programmable integrated circuit 302 to manufacturing settings when all user-defined configuration data fails to configure or reboot the programmable integrated circuit 302. For example, default configuration data may be provided by the manufacturer or company that produces programmable integrated circuit 302. In one embodiment, backup default page 318 is configured to be hidden from the user to prevent its content or default configuration data from being accidentally overwritten by the user. In one example, backup default page 318 is a flash memory for storing default configuration data. In one aspect, the user configuration data or the previous user configuration data comprises an address of a storage location of the next configuration data or the default configuration data.

In one example, the bus 308 is a direct communication channel or connection between the storage device 304 and the programmable integrated circuit 302 to facilitate the passage or transfer of user configuration data and/or default configuration data from the storage device 304 to a configuration memory 322 of the programmable integrated circuit 302. In an application, the bus 308 may use a bus protocol to transfer bit streams and/or data. Bus protocols include, but are not limited to, Serial Peripheral Interface (SPI), Inter-Integrated Circuit (I2C), I3C (sense Wire), Universal Asynchronous Receiver-Transmitter (UART), Integer (Int), Two-Wire Interface (TWI), timer, and the like. In one aspect, the bus 308 may be configured to be bi-directional. Alternatively, the bus 308 may be configured to be unidirectional.

In one example, I2C includes multi-master, multi-slave, single-ended, and serial computer buses. A typical application of I2C is that it can be used to attach low speed peripherals for short range and on-board communication. The serial peripheral interface bus is a synchronous serial communication interface specification for short-range communications, such as in embedded systems. In one example, the serial peripheral interface device communicates in full duplex mode, employing a master-slave architecture with only a single master device. The master initiates the reading and writing of frames. It should be noted that the serial peripheral interface may also be referred to as a four-wire serial bus, rather than a three-wire serial bus, a two-wire serial bus, and a one-wire serial bus. A universal asynchronous receiver transmitter is a computer hardware device for asynchronous serial communication in which the data format and transmission speed can be configured. In one example, some electrical signal levels and methods are processed by driver circuitry external to the universal asynchronous receiver/transmitter. I3C, also known as sense leads, provide connections between chips using signal patterns. For example, I3C employs two lines, one line (SCL) serving as a clock to define the sampling time and the other line (SDA) serving as a data line.

In operation, upon receiving an initial configuration trigger, a bit stream of configuration data is transmitted from storage device 306 to configuration memory 322 over bus 308. The initial configuration trigger includes an internal trigger and an external trigger. The internal trigger is due to its programmed logic function. The external trigger is due to the reception of an external signal from another chip or device. The initial configuration trigger may also include a combination of internal and external triggers. If the newly loaded configuration data is validated, the configuration process performed by validation component 328 ends. However, if the newly loaded configuration data is not validated, then a reload operation of the configuration data from storage device 306 to configuration memory 322 is activated. If the maximum number of retries has not been reached, the same configuration data is reloaded or retransmitted. The user may define the total number of retries and a counter is used to count or record the total number of retries occurring. When the user configuration data stored in storage device 306 is exhausted, configuration data address unit 326 retrieves the address of backup default page 318 and selects default configuration data from backup default page 319 via selector 320, as indicated by reference numeral 350. After default configuration data is loaded into configuration memory 322, programmable integrated circuit 302 will be enabled or configured to its manufacturing settings.

The benefit of using a multiple boot process with a backup default configuration to restart the field programmable gate array is that it allows the programmable gate array to be restarted to a manufacturing setting when user-defined configuration data fails to boot or configure the programmable gate array, thereby enhancing the overall reliability of the programmable gate array.

FIG. 3B is a logical block diagram illustrating a logical process 360 implemented by the verification component 328 for verifying configuration data according to one embodiment of the invention. The verification component 328 includes a test code component 380, a test module 362, a counter 364, a comparator 368, and a verification results unit 370. In one aspect, the test code component 380 also includes a verification code unit 372 and a backup default verification code unit 376. For example, verification code element 372 contains verification data provided by the user for testing and verifying the user's configuration data. Backup default verification code unit 376 contains verification data provided by the manufacturer for testing and verifying the default configuration data. It should be noted that the basic concepts of the exemplary embodiments of this invention may be altered without changing the basic concepts of the invention by adding or removing one or more modules (circuits or elements) from the logic process 360.

Upon receipt of newly arrived configuration data, the test module 362 retrieves validation data from the test code component 380. Depending on the source of the configuration data, the test module 362 obtains verification data from either the verification code unit 372 or the backup default verification code unit 376. It should be noted that the test code component 380 may be a local memory, an embedded memory, and/or an on-chip memory. If the configuration data is user supplied, the test module 362 selects the verification data from the verification code element 372 via the selector 374. Alternatively, if the configuration data is default configuration data, the test module 362 selects verification data from the backup default verification code unit 376 via the selector 374. The test module 362 then executes a verification program to verify the integrity and operability of the newly arrived configuration data based on the verification data from the test code components 380.

Counter 364 is used to count the total number of reloads of the same configuration data from the memory device to the programmable integrated circuit according to predefined verification conditions. For example, the predefined verification condition may be the number of verification procedures performed by the test module 362. Alternatively, the predefined validation condition may be the loading or reloading of configuration data from the storage device to the configuration memory. In one aspect, the user may set or predefine the number of reloads that should be performed.

After executing the newly arrived configuration data in response to the verification data, test results are generated by the test module 362 and then fed to the comparator 368. Upon selection of a predefined known value from the test code component 380, the comparator 368 generates a comparison output. It should be noted that the predefined known value may be selected by the multiplexer 366 from either the captcha unit 372 or the backup default captcha unit 376 depending on the source of the configuration data (or default configuration data). For example, if the configuration data is provided by a user, a predefined known value is retrieved from the captcha element 372. However, if the configuration data is default configuration data, then the predefined known values are retrieved from the backup default passcode unit 376.

Upon receipt of the comparison output, verification result unit 370 determines whether the newly arrived configuration data passes verification or whether it is necessary to reload the configuration data. In one aspect, the verification result unit 370 includes a backup default initiator for deciding whether default configuration data or another user-defined configuration data should be reloaded upon detection of a failure and/or corruption of the current configuration data in the configuration memory.

The benefit of employing the verification component 328 is that the reliability of the programmable semiconductor system and/or the field programmable gate array is enhanced even if the user-defined configuration data is corrupted or erroneous.

Figure 4A is a block diagram illustrating a programmable semiconductor system or processing system 400 incorporating a memory device and a field programmable gate array to perform a multiple boot process with a backup default configuration according to one embodiment of the invention. The programmable semiconductor system or processing system 400 includes a memory device 406, a programmable integrated circuit (or field programmable gate array) 402, and a bus 308. The bus 308 may be an inter-chip bus on the module, or may be a Joint Test Action Group (JTAG) bus running between devices. The programmable semiconductor system or processing system 400 is similar to the programmable semiconductor system 300 shown in fig. 3A except that the back-up default pages 418 are moved from the memory device (as shown in fig. 3A) into the field programmable gate array or programmable integrated circuit 402 as embedded memory in the programmable integrated circuit 402. In one aspect, backup default pages 418 are located in flash memory internal to programmable integrated circuit 402. Alternatively, the backup default pages 418 may be placed in embedded random access memory or static random access memory.

In one embodiment, the initial configuration data or first configuration data used to restart or configure the programmable integrated circuit 402 is preferably located in an external storage device, such as storage device 406, via bus 308. Initial configuration data or first configuration data, which may also be referred to as primary configuration data or primary configuration bitstream, is prepared and provided by a user for performing user-defined logic functions. A benefit of loading the configuration data from an external device is that it may allow a user to control and/or modify the source of the configuration data in real time through the operation of user-defined or programmed logic in the field programmable gate array.

Fig. 4B is a block diagram illustrating a programmable semiconductor system or processing system 450 located within a field programmable gate array 452 to perform a multiple boot process with a backup default configuration according to one embodiment of the invention. The programmable semiconductor system or processing system 450 illustrates a field programmable gate array 452, the field programmable gate array 452 including the storage device 406, connections 408, configuration memory 422, verification unit 328, and configurable logic block 330. The programmable semiconductor system or processing system 450 is similar to the programmable semiconductor system or processing system 400 shown in FIG. 3A, except that the memory device 406 and the connection (bus) 408 are embedded within a field programmable gate array or programmable integrated circuit 452. In one aspect, the storage device 406 may be non-volatile memory, and/or a combination of volatile and non-volatile memory.

It should be noted that the field programmable gate array or programmable integrated circuit 302 shown in fig. 3A is generally classified as a volatile field programmable gate array. The programmable integrated circuit 402 may be categorized as a non-volatile field programmable gate array or a programmable integrated circuit because it includes embedded non-volatile memory that stores a copy of the configuration data. For example, user-defined logical configuration information may persist when power is lost.

A benefit of embedding storage into a programmable integrated circuit is that it allows for System-On-Chip (SOC) designs suitable for multiple applications, including but not limited to remote security monitoring systems, drones, automobiles, ships, and the like.

Figure 5A is a block diagram illustrating a programmable semiconductor system 500 including a programmable integrated circuit capable of performing multiple boot or dual boot operations according to one embodiment of the invention. Programmable semiconductor system 500 includes a memory device 502, a programmable integrated circuit (or field programmable gate array) 506, and a selector 508. In one aspect, the output of the selector 508 is fed to the programmable integrated circuit 506 through a connection or bus 308. It should be noted that the basic concepts of the exemplary embodiments of the present invention may not be changed by adding or removing one or more modules (circuits or elements) from the programmable semiconductor system 500.

The storage device 502 is organized to store multiple sets or versions of configuration data 510 and 516, where each configuration data is referenced or addressed by an address, such as address 520, that points to the configuration data 510. For example, configuration data 510 and 516 may be loaded, referenced, and/or addressed via addresses 520 and 526. In one embodiment, each configuration data contains a specific predefined address location for addressing the location of the next configuration data or default configuration data. In one aspect, a particular predefined address location may be assigned or specified by a user. For example, the last 4 bytes of the configuration data bitstream are designated for storing the address of the storage location containing the next configuration data. For example, the last portion of the configuration data 510 contains an address 522 that points to a storage location containing the next configuration data 512. In one embodiment, the last user-defined configuration data includes the memory address of the backup default page. For example, the user configuration data 512 includes a storage address 526 that points to or addresses a storage location where the default configuration data 516 is stored. In one embodiment, storage device 502 includes a communication port 528 for receiving user and/or manufacturing defined configuration data.

In one aspect, the programming integrated circuit 506 includes a configuration memory 322, a verification unit 328, a start and count unit 530, a maximum number unit 532, and a next load unit 536. Upon detection of corrupted configuration data, a counter is incremented to represent the total number of loads of the current configuration data. If the maximum number of loads has not been reached, the initiator initiates a reload of the configuration data from storage 502. If the maximum number of loads has been reached, the initiator begins to identify and retrieve addresses of storage locations containing new configuration data, including default configuration data. After retrieving the address from the current configuration data in configuration memory 322, the next load unit 536 selects the storage location to store the next configuration data via selector 508 to reload the configuration data.

In one embodiment, the programmable integrated circuit 506 includes a port 529 for communicating with a user that is geographically remote from the programmable semiconductor system. Port 529 may be arranged to receive certain types of information, data or input from external devices via a communications network. Upon receiving input through port 529, the input data may be forwarded to storage device 502, as shown by reference numeral 509. It should be noted that the input data may be any type of data, including but not limited to user data and configuration data.

A programmable semiconductor system is a configurable semiconductor device that includes a programmable integrated circuit 506 and a memory device 502. In one example, programmable integrated circuit 506 includes a set of configurable logic blocks, a routing connection array, and configuration memory 322 for performing programmed logic functions. Each configurable logic block includes a plurality of look-up tables configured to provide one or more output signals based on a set of input signals and configuration data in configuration memory 322.

The storage device 502 stores at least one configuration data containing user function data in a storage location addressed by an address, e.g., configuration data 1 is directed by address 520. In this embodiment, the storage device 502 also stores second configuration data containing second user function data in a second storage location, e.g., configuration data 2 is directed by the address 522. In one aspect, configuration data 1 includes a memory address 522 that points to memory location 512 where configuration data 2 is stored.

The benefit of the configuration data comprising the address of the next configuration data is that it allows the programmable integrated circuit to be automatically restarted or configured using the next configuration data or default configuration data without significant external intervention. External intervention includes, but is not limited to, control signals from external devices and/or systems.

Figure 5B is a block diagram illustrating a programmable semiconductor system 550 including a programmable integrated circuit capable of performing dual boot operations, in accordance with one embodiment of the present invention. Similar to the programmable semiconductor system 500 shown in fig. 5A, the programmable semiconductor system 550 includes a memory device 552, a programmable integrated circuit (or field programmable gate array) 506, and a selector 508. In one aspect, storage 552 contains primary configuration data 510 and secondary or backup configuration data 516. In the event that the primary configuration data 510 fails due to a coding error or corruption of the bit stream due to a transmission error, the secondary or backup configuration data 516 is downloaded to restart or configure the programmable integrated circuit 506. It should be noted that the basic concepts of the exemplary embodiments of the present invention may be altered without changing the basic concepts of the exemplary embodiments of the present invention by adding or removing one or more modules (circuits or elements) from the programmable semiconductor system 550.

Figure 6A is a block diagram illustrating a programmable semiconductor system 600 incorporating a programmable integrated circuit capable of performing multiple boot or dual boot operations according to one embodiment of the invention. The programmable semiconductor system 600 includes a memory device 602, a programmable integrated circuit (or field programmable gate array) 606, and a selector 508. In one aspect, the output of the selector 508 is fed to the programmable integrated circuit 506 through a connection or bus. The storage device 602 is organized to store multiple sets or versions of configuration data 510, 512, 614, which may be loaded, referenced, and/or addressed via addresses 520, 522, 624. It should be noted that the basic concepts of the exemplary embodiments of the present invention may be altered without changing the basic concepts of the exemplary embodiments of the present invention by adding or removing one or more modules (circuits or elements) from the programmable semiconductor system 600.

The programmable semiconductor system 600 is similar to the programmable semiconductor system 500 shown in fig. 5A except that the back-up default pages 616 are moved from the memory device (as shown in fig. 5A) into the field programmable gate array or programmable integrated circuit 606 as embedded memory in the programmable integrated circuit 606. In one aspect, backup default pages 616 containing default configuration data are located in flash memory embedded in programmable integrated circuit 606. Alternatively, the backup default pages 616 may be placed in random access memory or static random access memory embedded in the programmable integrated circuit 606. During operation, upon detecting an error, corruption, and/or corruption of configuration data in configuration store 322, network loading unit 612 identifies a new storage location containing the next user configuration data when the next user configuration data is available in storage device 602, as indicated by reference numeral 650.

Alternatively, after detecting defective configuration data, network loading unit 612 selects default configuration data from backup default page 616 through multiplexer 610 when the user-defined configuration data is exhausted. It should be noted that the exhaustion of the user-defined configuration data means that neither the user-defined configuration data in the storage device can restart the field programmable gate array or the programmable integrated circuit. Depending on the application, the configuration data in configuration memory 322 may be configured to contain an address pointing to the storage location where backup default page 616 is stored. Alternatively, the programmable integrated circuit 606 is configured to store the address of the backup default page 616 internally.

FIG. 6B is a block diagram illustrating a programmable semiconductor system 650 including a Dual-Mode Port (DMP) 652 for providing Dual use in accordance with one embodiment of the present invention. Similar to programmable semiconductor system 600 shown in fig. 6A, programmable semiconductor system 650 includes a configurable semiconductor device or a programmable semiconductor system that includes a memory device 602, a programmable integrated circuit (or field programmable gate array) 656, and a selector 508. In one aspect, the programmable integrated circuit 656 includes a dual mode port 652 capable of facilitating communication between the selector 508 and the configuration memory 322. It should be noted that the dual mode port 652 may also be referred to as a dual mode pin, dual port, or dual pin. To simplify the foregoing discussion, dual mode ports are used to refer to either dual mode pins, dual port or dual pin. It should be noted that the basic concepts of the exemplary embodiments of this invention may be altered without changing the basic concepts of the exemplary embodiments of this invention by adding or removing one or more modules (circuits or elements) from the programmable semiconductor system 650.

In this example, the memory device 602 is used to store configuration data representing various versions of user-defined logic functions and the bus is used to couple the memory device 602 to the dual mode port 652 through the selector 508 for data transfer. In one embodiment, the programmable integrated circuit 656 includes a dual mode port 652 to transfer configuration data during configuration. After the programmable integrated circuit 656 is programmed or configured, the dual mode port 652 is switched to process user data. In one example, programmable integrated circuit 656 includes one or more dual mode ports, configurable logic blocks, routing connection arrays, and configuration memory 322, verification unit 328, enable and count unit 530, maximum number unit 532, and next load unit 612. When the configuration memory 322 stores the current version of the configuration data, each configurable logic block includes a look-up table configured to provide an output signal based on a set of input signals and the configuration data.

In one embodiment, the programmable integrated circuit 656 also includes a dual mode port switch, not shown in fig. 6B, that is configured to identify and/or arrange when the dual mode port 652 switches between a configuration mode and a logical operating mode. The dual mode port switch, also referred to as a pin controller, may be a stand-alone module or part of a field programmable gate array controller. The function of the dual mode port switch is to determine that the dual mode port can resume or continue operation even after a defect in the current configuration data in the configuration memory 322 is discovered.

The dual mode port 652 is capable of processing configuration data during a configuration mode and is capable of processing user data during a logical operational mode. In one embodiment, the dual mode port 652 is set (or switched) to the configuration mode when the dual mode port is used to load or transfer configuration data from memory over the bus. After the configuration phase, the dual mode port 652 is switched or reset to a logical mode of operation so that the dual mode port is used to process or transfer user data.

The storage device 602 includes a storage section to store at least one user-provided configuration data, such as configuration data 522, to provide at least a portion of the configuration data. In one embodiment, the configuration data includes command signals that are used to instruct or assist the dual mode port 652 to switch between two modes of processing configuration data and user data. These two modes are referred to as a configuration mode and a logical operation mode. In one embodiment, the backup default page 666 contains default configuration data that also contains a signal instructing the dual mode port 652 to switch between the two modes to facilitate processing of the configuration data and user data.

Fig. 7 is a block diagram illustrating a system or computer 700 having a programmable semiconductor system and/or programmable integrated circuit capable of providing multiple boot processes with backup default configurations to enhance programmability of the programmable integrated circuit, according to one embodiment of the present invention. Computer system 700 includes a processing unit 701, an interface bus 712, and an Input/Output (IO) unit 720. The processing unit 701 includes a processor 702, a main memory 704, a system bus 711, a static storage device 706, a bus control unit 705, input/output elements 730, and a field programmable gate array 785. It should be noted that the basic concept of the exemplary embodiments of the present invention does not change with the addition or removal of one or more modules (circuits or elements) in fig. 7.

The bus 711 is used to transfer information between the various components and the processor 702 for data processing. The processor 702 may be any of a variety of general purpose processors, embedded processors, or microprocessors, for example

An embedded processor,

Core^TM Duo、Core^TM Quad、

Pentium^TMMicroprocessor, Motorola^TM 68040、

Serial processors or Power PCs^TMA microprocessor.

Main memory 704, which may include multiple levels of cache memory, stores frequently used data and instructions. The main Memory 704 may be a Random Access Memory (RAM), a Magnetic Random Access Memory (MRAM), or a flash Memory. Static Memory 706, which may be a Read Only Memory (ROM), is coupled to bus 711 for storing static information and/or instructions. Bus control unit 705 is coupled to bus 711 and 712 and controls which elements, such as main memory 704 or processor 702, can use the bus. The bus control unit 705 manages communication between the bus 711 and the bus 712. Mass storage memory or Solid State Disk (Solid State Disk), such as a magnetic Disk, optical Disk, hard drive, floppy Disk, compact Disk read only memory, and/or flash memory, for storing large amounts of data.

In one embodiment, the input/output unit 720 includes a display 721, a keyboard 722, a cursor control device 723, and a low power programmable logic device 725. The display device 721 may be a liquid crystal device, a Cathode Ray Tube (CRT), a touch screen display, or other suitable display device. The display device 721 projects or displays an image of the graphic reticle. The keyboard 722 may be a conventional alphanumeric input device for communicating information between the computer system 700 and a computer operator. Another type of user input device is cursor control device 723, such as a conventional mouse, touch mouse, trackball, or other type of cursor for communicating information between system 700 and the user.

Programmable logic device 725 is coupled to bus 712 to provide configurable logic functions to local and remote computers or servers over a wide area network. The programmable logic device 725 and/or the field programmable gate array 785 are configured to perform operations of multiple boot processes with backup default configurations to enhance reliability of the field programmable gate array and/or the programmable logic device. In one example, the programmable logic device 725 may be used in a modem or network interface device to perform communications between the computer 700 and a network. Computer system 700 may be coupled to a server through a network infrastructure as discussed below.

Fig. 8 is a block diagram illustrating various applications 800 of a programmable semiconductor system or programmable semiconductor device containing field programmable gate arrays or programmable logic devices capable of performing multiple boot operations with backup default configurations to enhance overall reliability, according to one embodiment of the invention. Application 800 illustrates an artificial intelligence server 808, a communications network 802, a switching network 804, the internet 850, and a portable electronic device 813 and 819. In one aspect, a programmable semiconductor device capable of performing multiple boot operations with a backup default configuration is used in an artificial intelligence server, a portable electronic device, and/or a switching network. The Network or cloud Network 802 may be a wide Area Network, a Metropolitan Area Network (MAN), a Local Area Network (LAN), a satellite/terrestrial Network, or a combination of wide Area, Metropolitan Area, and Local Area networks. It should be noted that the basic concepts of the exemplary embodiments of this invention do not change as one or more modules (or networks) are added or removed from the application 800.

The Network 802 includes a plurality of Network nodes, not shown in fig. 8, where each node may include a Mobility Management Entity (MME), a Radio Network Controller (RNC), a Serving Gateway (S-GW), a Packet Data Network Gateway (P-GW), or a home agent to provide various Network functions. Network 802 couples to internet 850, artificial intelligence server 808, base station 812, and switching network 804. In one embodiment, the server 808 includes a Machine Learning Computer (MLC) 806.

The switching network 804, also referred to as a packet core network, includes cell sites 822 through 826 capable of providing wireless access communications, such as third generation (3rd generation 3G), fourth generation, or fifth generation cellular networks. In one example, the Switching network 804 includes an Internet Protocol (IP) and/or a Multiprotocol Label Switching (MPLS) based network capable of operating at the Open Systems Interconnection (Open) Basic Reference Model (OSI) Model) layer for information transfer between clients and network servers. In one embodiment, the switching network 804 is logically coupled 820 to a plurality of users and/or handsets 816 through a cellular and/or wireless network across a geographic area. It should be noted that a geographic region may refer to a campus, a city, a metropolitan area, a country, a continent, etc.

The base station 812, also referred to as a cell site, node B, or eNodeB, includes a radio tower that can be coupled to various User Equipments (UEs) and/or Electrical User equipments (eus). The terms "user device" and "appliance user device" refer to similar portable devices, which are used interchangeably. For example, the user device or Portable Electronic Device (PED) may be a cellular phone 815, a laptop 817, a laptop via wireless communication,

Tablet computer and/or

The handheld device may also be a smart phone, for example

And the like. In one example, the base station 812 enables network communications between mobile devices, such as the portable handheld device 813 and 819 through wired and wireless communication networks. It should be noted that the base station 812 may include additional radio towers and other land-based switching circuitry.

Internet 850 is a computing network that uses Transmission Control Protocol/Internet Protocol (TCL/IP) to provide communication between geographically separated devices. In one example, the internet 850 is coupled to a provider server 838 and a satellite network 830 through a satellite receiver 832. In one example, satellite network 830 may provide a number of functions, such as wireless communications and global positioning system ("GPS"). It should be noted that multiple boot operations with backup default configurations that enhance the reliability of field programmable gate arrays are beneficial for many applications such as, but not limited to, smart phones 813-819, satellite networks 830, automobiles 813, artificial intelligence servers 808, businesses 807, and homes 820.

Exemplary embodiments of the present invention include various processing steps, which will be described below. The steps of this embodiment may be embodied in machine or computer executable instructions. The instructions may be used to cause a general-purpose or special-purpose system that is programmed with the instructions to perform the steps of an exemplary embodiment of the present invention. Alternatively, the steps of the exemplary embodiments of the present invention might be performed by specific hardware components that contain hardwired logic for performing the steps, or by any combination of programmed computer components and custom hardware components.

FIG. 9 is a flow diagram illustrating a configuration process 900 for a programmable integrated circuit that performs a multiple boot process with a backup default configuration according to one embodiment of the invention. At block 902, a process for configuring a field programmable gate array includes: a first bit stream stored in a first memory is identified over a communication channel, the first bit stream containing user-defined configuration data.

At block 904, a first bitstream of configuration data is loaded or transferred from a first memory to a configuration memory in a field programmable gate array. It should be noted that the first memory may be a chip or an Integrated Circuit (IC) on the module. Alternatively, the first memory may be a flash memory embedded in a field programmable gate array.

At block 906, the process can verify the integrity and function of the first bit stream of configuration data according to a set of predefined verification conditions to determine that the first bit stream of configuration data is defect-free.

At block 908, when a corrupted or corrupted first bit stream is detected, an address of a storage location containing a second bit stream is extracted from the first bit stream of configuration data. In one embodiment, the second bitstream of second configuration data is loaded from a storage location addressed by an address of the storage location where the second bitstream is stored. For example, the process identifies the address of the memory location containing the second bit stream in a predetermined location of the first bit stream.

In one embodiment, the process verifies the integrity and functionality of the second bitstream based on a second set of predefined verification conditions or verification codes to determine that the programmable integrated circuit will function properly with the second bitstream of configuration data. The process is also capable of identifying an address of a backup default page containing manufacturing default configuration settings at a predefined location of the second bitstream when the second bitstream is detected as corrupted or defective. In one aspect, the field programmable gate array restarts or configures to the manufacturing default settings by extracting the address of the backup default page from the bit location or bit position of the second bitstream.

FIG. 10 is a logic flow diagram illustrating a process 1000 for configuring a programmable integrated circuit through a multiple boot process with a backup default configuration in accordance with one embodiment of the present invention. At block 1002, configuration data, such as D1, is loaded into the configuration memory at block 1006. After configuration data verification at block 1008, the verification results are checked at block 1010 to determine if the configuration data in the configuration memory is intact and a functional check is performed. If the configuration data is intact and not defective, the process terminates at block 1012. If the configuration data is corrupted, the process increments a counter at block 1016 and proceeds to the next block 1018.

At block 1018, the process determines whether a maximum number of configuration data loads has been reached. If the maximum number has not been reached, the process continues to retry at block 1026 and begins reloading, as indicated at reference numeral 1032. If the maximum number has been reached, the process continues by checking whether the data in the configuration store is default configuration data or backup default. If it is default configuration data, the process continues to block 1022 and a fault signal is issued indicating that the programmable integrated circuit is defective. If the data in the configuration memory is not the default configuration data, the process continues at block 1028 with retrieving the address containing the storage location of the next configuration data. At block 1030, the process continues with reloading the next configuration data from memory, as indicated by reference numeral 1032.

FIG. 11 is a logic flow diagram illustrating a process 1100 for configuration or data processing through a dual mode port in accordance with one embodiment of the present invention. At block 1102, a process capable of configuring a field programmable gate array with configuration data or loaded configuration information identifies a first bit stream stored in a first memory through a communication channel, the first bit stream containing configuration data representing a user-defined logic function. The first bit stream is the main configuration data generated and provided by the user.

At block 1104, upon identifying the first bit stream, a dual mode port coupled to the bus or communication channel is set (or switched) to a configuration mode. The configuration mode is a setting for processing a bitstream containing configuration data. In one embodiment, the dual mode port is managed by a pin controller in a field programmable gate array.

At block 1106, the process downloads or transfers the first bit stream from the first memory to a configuration memory in the field programmable gate array through the dual mode port. In one embodiment, the first memory is an external storage device located outside the field programmable gate array. A benefit of loading the configuration data from an external device is that it allows a user to control and/or manage the source of the configuration data in real time through user configuration logic in the field programmable gate array.

When the basic function implemented by the first bitstream is verified, the dual mode port is then reset to a logical mode of operation capable of processing user data, block 1108. Alternatively, the process can maintain or maintain the current setting of the dual mode port in the configuration mode when the first bit stream is corrupted. For example, after verifying the integrity and/or functionality of the first bit stream based on a set of predefined verification conditions, when the first bit stream is corrupted, the address of the second bit stream is extracted from the first bit stream. In one aspect, a second bitstream is loaded through the dual mode port from a storage location addressed by an address of the second bitstream. The process is also capable of identifying the address of the backup default page containing default configuration data in order to restart the field programmable gate array to the manufacturing default settings.

Alternatively, after verifying the integrity and/or functionality of the first bit stream according to a set of predefined verification conditions, the dual mode port is switched to a logical mode of operation capable of processing user data when the first bit stream passes verification or is defect-free. For example, after a logic block configured in a programmable logic device or a field programmable gate array generates a second bitstream representing a second set of configuration data, the second bitstream is forwarded or sent to an external memory through the dual mode port. Depending on the application, the first bit stream may also be updated by a logic block configured in the programmable logic device to form a new bit stream representing the updated configuration data. The new bit stream is then sent to external storage through the dual mode port. In one aspect, after generating a data stream representing user data provided by the programmable logic device, the data stream may be sent to an external memory through the dual mode port to store the user data. It should be noted that the external memory may be volatile memory, non-volatile memory, or a combination of volatile and non-volatile memory devices.

In one embodiment, the process enables a user to receive a new bit stream through a communication port of the programmable logic device via a communication channel of a remote user, the bit stream representing an update to the configuration data. After switching the dual mode port to a logical operation mode set to process user data, a new bit stream is written into the external memory through the dual mode port. During operation, a user generates a new or updated bit stream representing configuration data for the field programmable gate array. The updated bit stream is transmitted to the field programmable gate array through a port coupled to the communication channel, and when the dual mode port is set to a logical operation mode, the updated bit stream is stored in the external flash memory through the dual mode port. It is noted that the communication channel is connected to the field programmable gate array by at least one wire, cable or connection to a user at a remote site.

While particular embodiments of the present invention have been shown and described, it will be obvious to those skilled in the art that, based upon the teachings herein, that changes and modifications may be made without departing from this exemplary embodiment of the invention and its broader aspects. Therefore, the appended claims are intended to encompass within their scope all such changes and modifications as are within the true spirit and scope of this exemplary embodiment of the invention.

Claims (28)

1. A configurable semiconductor device capable of processing information, comprising:

a programmable integrated circuit, comprising: a configurable logic block, a routing connection array, and a configuration memory to perform programmable logic functions; each of the programmable logic blocks includes one or more look-up tables configured to provide one or more output signals based on a set of input signals and configuration data in a configuration memory;

a first memory coupled to the programmable integrated circuit and configured to store configuration data providing at least a portion of a user definition;

wherein the configuration memory of the programmable integrated circuit is configured to load the configuration data to cause the programmable integrated circuit to perform a user-defined logic function, and the configuration memory reloads the configuration data when the loaded current configuration data is defective.

2. The device of claim 1, wherein the reloaded configuration data is the same configuration data as the current configuration data; or

The reloaded configuration data is the next configuration data of the current configuration data; or

The reloaded configuration data is default configuration data, wherein the default configuration data is encoded and provided by a manufacturer that produced the programmable integrated circuit for resetting the programmable integrated circuit to a manufacturing setting.

3. The device of claim 2, further comprising:

a second memory for storing backup default pages, the backup default pages including the default configuration data.

4. The device of claim 3, wherein the second memory is integrated in the first memory or the programmable integrated circuit.

5. The device of claim 1, further comprising: a communication channel between the first memory and the programmable integrated circuit to facilitate transfer of the configuration data from the first memory to the configuration memory.

6. The device of claim 3, wherein the second memory is hidden from the user to prevent the contents of the second memory from being accidentally overwritten by the user.

7. The device of claim 1, wherein the first memory is a flash memory for storing multiple bitstreams of multiple user configuration data sets.

8. The device of claim 3, wherein the second memory is a flash memory for storing the backup default pages.

9. The device of claim 1, wherein the programmable integrated circuit further comprises a verification component to verify the functionality and integrity of the loaded current configuration data.

10. The device of claim 1, wherein any of the configuration data stored by the first memory includes an address of a next configuration data, the address pointing to a storage location where the next configuration data is stored.

11. The device of claim 1, wherein the programmable integrated circuit further comprises an initiator to reload configuration data when the configuration data corruption is detected.

12. The device of claim 3, wherein the programmable integrated circuit further comprises a dual mode port, wherein the dual mode port processes the configuration data during a configuration mode and processes user data during a logical operating mode.

13. The device of claim 12, wherein the dual mode port of the programmable integrated circuit is coupled to the first memory via a bus,

the dual mode port coupled to the bus is configured to switch to the configuration mode when the dual mode port is used to load the configuration data from memory over the bus; when the programmable integrated circuit is configured, the dual mode port is used to process user data, switching to the logical mode of operation.

14. The device of claim 13, wherein the configuration data includes a signal to enable the dual mode port to switch between modes to process the configuration data and the user data; and/or

The default configuration data includes signals to enable the dual mode port to switch between modes to process the configuration data and the user data.

15. A system capable of performing various digital processing functions and network communication functions, said system comprising the device of claims 1-14.

16. A method of configuring a field programmable gate array with configuration data stored in a configuration memory, comprising:

identifying a first bitstream over a communication channel, the bitstream containing user-defined configuration data stored in a first memory;

loading the first bit stream from a first memory into a configuration memory in the programmable gate array;

verifying the integrity of the first bitstream based on a set of predefined verification data to determine a functionality of the field programmable gate array from the first bitstream; and

loading a second bitstream to the configuration memory when it is determined that the first bitstream is corrupted, wherein the second bitstream contains reloaded configuration data.

17. The method of claim 16, wherein the reloaded configuration data included in the second bitstream is the same configuration data as the configuration data included in the first bitstream; or

The reloaded configuration data contained in the second bit stream is the configuration data next to the configuration data contained in the first bit stream; or

The second bit stream contains reloaded configuration data as default configuration data, wherein the default configuration data is encoded and provided by a manufacturer that produces the programmable integrated circuit for resetting the programmable integrated circuit to a manufacturing setting.

18. The method of claim 17, further comprising:

and loading the second bit stream when the loading times do not reach the maximum retry times, wherein the reloaded configuration data contained in the second bit stream and the configuration data contained in the first bit stream are the same configuration data.

19. The method of claim 17, further comprising: when the loading times reach the maximum retry times and the configuration data defined by the user is not exhausted, identifying the address of the storage position for storing the second bit stream in the predetermined position of the first bit stream, and loading the second bit stream from the storage position addressed by the address of the second bit stream to the configuration memory, wherein the reloaded configuration data contained in the second bit stream is the next configuration data of the configuration data contained in the first bit stream.

20. The method of claim 17, further comprising:

identifying a storage location address where the second bitstream is stored in a predetermined location of the first bitstream when the user-defined configuration data is exhausted, wherein the storage location address of the second bitstream is an address of a backup default page that includes manufactured default configuration settings;

restarting the field programmable gate array to a manufacturing default setting by default configuration data in the backup default page.

21. The method of claim 20, further comprising: verifying the integrity of the second bitstream based on a second set of predefined verification conditions to determine the functionality of the field programmable gate array from the second bitstream.

22. The method of claim 16, wherein after identifying the first bit stream over the communication channel, the method further comprises:

setting a dual mode port coupled to the communication channel to a configuration mode capable of processing configuration data;

loading the first bitstream from the first memory to a configuration memory in the field programmable gate array through the dual mode port; and

when the first bit stream is corrupted, maintaining the dual mode port in the configuration mode capable of transmitting the configuration data to load the second bit stream into the configuration memory.

23. The method of claim 22, further comprising:

resetting the dual mode port to a logical mode of operation capable of processing user data when the basic function implemented by the first bit stream is verified.

24. The method of claim 22, further comprising:

receiving a new bit stream representing the configuration data update from a remote user over a communication channel using a communication port; and

storing the new bit stream into the configuration memory of the programmable logic device.

25. The method of claim 24, further comprising:

switching the dual mode port to a logical mode of operation capable of processing user data; and

writing the new bit stream into the first memory through the dual mode port.

26. The method of claim 23, further comprising:

generating, by a plurality of configuration logic blocks in the programmable logic device, a second bitstream representing a second set of configuration data; and

forwarding the second bitstream to the first memory through the dual mode port.

27. The method of claim 23, further comprising:

updating the first bit stream by a plurality of configuration logic blocks in the programmable logic device to form a new bit stream representing updated configuration data; and

forwarding the new bitstream to the first memory through the dual mode port.

28. The method of claim 23, further comprising:

generating a data stream representing user data updated by a plurality of configuration logic blocks in the programmable logic device; and

sending the data stream to the first memory through the dual mode port to store the user data.

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