CN105930201A - Functional simulator for reconfigurable dedicated processor core - Google Patents
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Abstract
The invention relates to a functional simulator for a reconfigurable dedicated processor core. The functional simulator comprises an external interface module, a control module and a calculation realization module, wherein the external interface module simulates functions of an internal register set and an internal SRAM of the reconfigurable dedicated processor core, receives a configuration instruction required to be simulated, analyzes obtained task information according to the configuration instruction, and writes the task information into a global task queue; the control module simulates a function of an internal main controller of the reconfigurable dedicated processor core, transmits the task information among modules according to the task queue, obtains a calculation task required to be executed currently and a calculation task that is about to be executed from the task queue, and calls the calculation realization module to execute the calculation tasks; and the calculation realization module executes a plurality of algorithms to output calculation result data and calculation states, and executes the transportation of the task information and the calculation result data. The functional simulator has the beneficial effects of higher simulation speed, convenience for system-level debugging and optimization, and favorability for improving the efficiency and reducing the cost.
Description
Technical field
The present invention relates to the functional simulator of a kind of restructural application specific processor core, it is adaptable to restructural application specific processor core
Software system development design.
Technical background
In tradition SoC system development, software design have to wait until that whole hardware can be carried out after completing, and this makes
The whole construction cycle must become the longest.In order to solve this problem, the software and hardware cooperating design method being currently based on SystemC becomes
Obtain increasingly popular.Even if so, once needing the emulation carrying out whole system (to include operating system, driving, API and application
Program), simulator long time to be consumed based on SystemC, especially cycle-accurate simulator.This is great
Affect the progress of software development.
It it is widely used computer simulator and a software virtual machine of increasing income.It can be to the process of various frameworks
Device, and the subsystem of necessity, as the equipment such as network interface card are simulated emulation, aboundresources, simulation velocity are fast.QEMU is divided into user
Mode simulation (user mode emulation) and two kinds of operational modes of full-system simulation (full system emulation):
Under user model emulates, QEMU can start those programs for different central processing unit compilings；Under full-system simulation, QEMU
User can be allowed to whole system, and including central processing unit, peripheral hardware and operating system etc., whole holonomic system emulates, pole
System source code is tested and the work of error correction by big facilitating.
Summary of the invention
In place of it is an object of the invention to overcome above the deficiencies in the prior art, carry out whole for restructural application specific processor core
The emulation of individual system provides a quick simulator, also opens before hardware development plate is in place for API and software application
Send out and test provides a platform the most available.Techniques below scheme is specifically had to realize:
The functional simulator of described restructural application specific processor core, described restructural application specific processor core include Parasites Fauna,
SRAM, master controller and reconfigurable controller, the functional simulator of described restructural application specific processor core includes:
External interface module, simulation restructural application specific processor core internal register group and the function of internal SRAM, receive and need
The configuration-direct of simulation, resolves the mission bit stream obtained, and described mission bit stream writes one entirely according to described configuration-direct
The task queue of office；
Control module, the function of the internal master controller of simulation restructural application specific processor core, according to described task queue at each mould
Transmit described mission bit stream between block, obtain from described task queue and be currently needed for the processor active task performed and the fortune that will carry out
Calculation task, scheduling computation realizes module and performs processor active task；
Computing realizes module, the merit of simulation reconfigurable controller, DMA and reconfigurable arrays within restructural application specific processor core
Can, perform several algorithm output operation result data and computing state, and perform mission bit stream, the removing of operation result data
Fortune；
The design further of the functional simulator of described restructural dedicated processes core is, described control module includes operation control
Unit and status unit, Operations Analysis completes the scheduling of algorithm and the pipe of mode of operation according to described mission bit stream
Reason, described mode of operation includes holotype, from pattern and debugging mode；Status control module realizes the fortune of module according to computing
Calculation state updates the external state of simulator, and described external state includes idle condition, busy condition, completion status, and according to right
The external state answered sends interruption
The design further of the functional simulator of described restructural dedicated processes core is, external interface module includes storage inside
Unit and register cell, respectively correspondingly simulation SRAM and Parasites Fauna；Internal storage unit is under debugging mode, outside support
The access of SRAM in bound pair restructural application specific processor core, it is provided that computing realizes the computing memory headroom of module；Parasites Fauna mould
The Parasites Fauna of block simulation restructural application specific processor core, resolves configuration-direct simultaneously and exports, adding the task of algorithm computing
Information.
The further design of the functional simulator of described restructural dedicated processes core is, computing realizes that module includes can be real
The computing consolidation function block of existing 17 kinds of algorithm units, described algorithm unit is respectively as follows: FFT/IFFT computing, vector auto-correlation fortune
Calculation, computing cross-correlation, signed magnitude arithmetic(al), multiplying, matrix inversion operation, signed magnitude arithmetic(al), multiplying, point multiplication operation,
Covariance computing, the computing of real/complex FIR, real/complex Doppler's FIR computing, surely float translation operation and plural number modulus fortune
Calculate.
The design further of the functional simulator of described restructural dedicated processes core is, described computing consolidation function block
In, each algorithm unit individually contains computing realization and the data carrying of this algorithm；During computing realizes, each algorithm unit
All according to complexity and the data scale of corresponding algorithm, the carrying out of computing breakpoint under the step of algorithm and debugging mode is drawn
Point, control module carries out the computing of each step and realizes by calling concrete algorithm steps.
The further design of the functional simulator of described restructural dedicated processes core is, it is each that computing realizes in module
Algorithm unit uses the SRAM of internal storage unit simulation as computing internal memory when calculating, and internal storage unit is that computing realizes
Module provides the pointer directly accessing its internal memory, for walking around the read/write function of internal storage region module to its direct memory access.
The design further of the functional simulator of described restructural dedicated processes core is, the operation control list of control module
Unit scheduling by step divide the computing of algorithm unit performed realize time, carry out periodic Timing Processing by intervalometer:
Send interruption when intervalometer arrives setting value every time, operation control module according to described interruption by external interface module schedules
After computing consolidation function block completes the given step of assignment algorithm, enter the wait of described idle condition and interrupt, the most next time
Disconnected circulation, until whole computing completes.
Advantages of the present invention is as follows:
1, the present invention uses the mentality of designing of functional simulator, has simplified restructural application specific processor core outside sightless carefully
Joint, improves analog rate；
2, present invention accomplishes the demand of restructural application specific processor core whole system emulation, it is possible in place at hardware development plate
Before, provide an available development platform to software engineer；
3, the present invention realizes based on the virtual machine QEMU that increases income, and having rich in natural resources can be with the use of, builds the simplest.
Accompanying drawing explanation
Fig. 1 is the hardware structure figure of restructural application specific processor core.
Fig. 2 is the mapping relations figure of simulator and restructural application specific processor core internal module.
Fig. 3 is simulator internal module level schematic diagram.
Fig. 4 is running status schematic diagram before algorithm unit operand divides.
Fig. 5 is simulator functional test results.
Fig. 6 is identical PC Imitating device the performance test results comparison.
Specific embodiments
Below in conjunction with the accompanying drawings the present invention program is described in detail.
The simulated target of the functional simulator of the restructural application specific processor core that the present embodiment provides is the special place of restructural
Reason device core, its hardware structure is as shown in Figure 1.This processor core is mainly by Parasites Fauna, SRAM, master controller and reconfigurable control
Device forms, and uses Dynamic Reconfigurable Technique when running, and utilizes its internal reconfigurable cell, and it can realize algorithm and draw to calculating
The space held up maps, and improves motility and the resource utilization of whole processor.Restructural application specific processor achieves conventional letter
Number Processing Algorithm hardware-accelerated, such as FIR algorithm, related algorithm, FFT/IFFT, matrix class computing etc..Weighing of its coarseness
Structure designs, and can be changed topological structure and the interconnecting relation of its internal arithmetic unit by the static configuration mode of coarseness, real
The multiplexing of each algorithm arithmetic hardware resource existing, meets the requirement of signal processing algorithm real-time with this.
The functional simulator of the restructural application specific processor core that the present embodiment provides, realizes based on QEMU, according to accessing, transporting
The three zones feature calculated and control, rejects the outside sightless operation details of this processor core, by abstract for simulator be external
Interface module, computing realize module, three parts of control module.External interface module is depositor and inside in hardware configuration
The mapping of SRAM, is the part that can be accessed by the external world of simulator, receives the configuration-direct needing simulation, according to configuration-direct solution
The mission bit stream that analysis obtains, and described mission bit stream is write an overall task queue.It is reconstruct control that computing realizes module
The mapping of device processed, DMA and reconfigurable arrays, be algorithm computing realize part, perform several algorithm output operation result number
According to computing state, and perform mission bit stream, the carrying of operation result data.Control module is the mapping of master controller, is whole
The control of the internal process of individual simulator and the control part of state, transmit described between modules according to described task queue
Mission bit stream, obtains from described task queue and is currently needed for the processor active task performed and the processor active task that will carry out, scheduling fortune
Calculation realizes module and performs processor active task, sees Fig. 2.
Further, such as Fig. 3, external interface module is divided into register group unit and two parts of internal storage unit.Post
Storage group unit is responsible for simulation Parasites Fauna within restructural application specific processor.Depositor within restructural application specific processor
Group includes that device configuration register, computing configuration register, status register, aborted depositor and holotype base address are posted
Storage.These depositors simulated be written and read by outside bus of can passing through, it is achieved state reads and instructs the operations such as write.
Meanwhile, this module is responsible for resolving the instruction that configuration is come in, and the computing that will be performed by processor active task queue increase simulator is appointed
Business.
Computing realizes module, is its main operational part of whole simulator, by computing consolidation function block cal_family structure
Becoming, inside is divided into 17 algorithm units, including FFT/IFFT computing, vector auto-correlation computation, computing cross-correlation, addition and subtraction fortune
Calculation, multiplying, matrix inversion operation, signed magnitude arithmetic(al), multiplying, point multiplication operation, covariance computing, real/complex FIR
Computing, real/complex Doppler's FIR computing, surely float translation operation and plural number modulus computing.In computing consolidation function block, often
Individual algorithm unit the most individually contains computing realization and the data carrying of this algorithm；Computing realizes in cal_family, each calculation
Method unit is all according to complexity and the data scale of corresponding algorithm, by computing breakpoint under the step of algorithm and debugging mode
Dividing, control module carries out the computing of each step and realizes by calling concrete algorithm steps, it is achieved to debugging mode
Support, and prevent large-scale data computing from causing QEMU seemingly-dead or card.
Computing realizes each algorithm unit in module and uses when calculating the SRAM of internal storage unit simulation as fortune
Calculating internal memory, internal storage unit is that computing realizes module and provides the pointer directly accessing its internal memory, is used for walking around storage inside
The read/write function of district's module, to its direct memory access, improves the execution speed of algorithm arithmetic element with this.
Control module is subdivided into Operations Analysis and two parts of status unit in simulator.Operation control
Module carries out computing according to the processor active task in processor active task queue, the algorithm unit in scheduling cal_family, and support can weigh
The holotype of structure application specific processor core, from the dispatching simulation of pattern and debugging mode.Status control module is according to cal_family
Running status, the simulation change of external status register of restructural application specific processor and dishing out of aborted.
Wherein, under pattern simulation state, after each processor active task terminates, corresponding mode bit can be set, as in
Disconnected flag bit, complement mark position etc..After outside main equipment confirms this subtask, corresponding state position empties again, operation control
Device can according to the task in processor active task queue and continue executing with next processor active task or enter idle condition.
Under holotype emulation mode, simulator can be inquired about automatically in the address space that holotype base register points to
The configuration of computing configuration register, reads and resolves task and add processor active task queue；In such a mode, simulator can be according to criticizing
Process flag bit and determine it is response external equipment or after all tasks of task queue are done after each task completes
Just response external equipment.
Under debugging mode emulation mode, simulator can be simulated in the reconfigurable controller within restructural application specific processor core
The response of breakpoint, when the algorithm unit computing in cal_family is to breakpoint location, computing can be interrupted, open internal simulation
SRAM, i.e. the access of internal storage region module limits, and now outside can access the intermediate results of operations in internal storage region.
In computing realizes the cal_family of module, due to the algorithm of algorithm unit support have time complexity high,
The feature that data volume is big, therefore the algorithm of each algorithm unit is when realizing, all according to the concrete feature of each algorithm, by its according to
Total operand is divided into the step of N number of operand approximation equivalent, and the most each step only comprises about the 1/N of total operand, and N's is big
The little operand that must assure that each step is not result in that system card pauses.Controlled each step interval by control module to perform
Become the computing of whole algorithm.With reference to Fig. 4, system code and algorithm operation part are quickly alternately performed.Utilize the QEMU-in QEMU
Timer intervalometer carries out periodic Timing Processing.Trigger when intervalometer arrives setting value every time and interrupt, operation control module
Completed the given step of assignment algorithm by interface scheduling cal_family, enter the wait of described idle condition and interrupt next time,
The most constantly circulate, until whole computing completes.So, although integral operation amount cannot be reduced, but pass through operand division side
Case becomes the computing of multi-step, and other codes can perform in the gap of two steps of algorithm, is not result in that whole system is all blocked
Pause and perform at the algorithm of restructural application specific processor simulator, thereby ensure that whole system is run continuous and smooth.
The functional simulator of the restructural application specific processor core that the embodiment of the present invention provides is in simulation functionally, logical
Having crossed correctness, depositor read-write and the test of three aspects of internal storage region access that algorithm runs, test result is with reference to figure
5.In the test of performance, and cycle accurate simulator based on SystemC contrasts.Both are in the most identical environment
Under, test and carry out in the case of not tape operation system and other peripheral hardwares, by api function placement algorithm and parameter, carry out speed
The comparison of degree, test result is with reference to Fig. 6, it can be seen that this simulator is in performance, especially in the case of operand is big, performance
It is much better than cycle accurate simulator.
Such as Fig. 5,6 it can be seen that the present invention is restructural application specific processor core carries out the emulation of whole system and provide one
Individual quick simulator, also develops and tests offer one for API and software application high before hardware development plate is in place
The platform that effect is available.
Claims (7)
1. a functional simulator for restructural application specific processor core, described restructural application specific processor core include Parasites Fauna,
SRAM, master controller and reconfigurable controller, it is characterised in that the functional simulator of described restructural application specific processor core includes:
External interface module, simulation restructural application specific processor core internal register group and the function of internal SRAM, receive and need
The configuration-direct of simulation, resolves the mission bit stream obtained, and described mission bit stream writes one entirely according to described configuration-direct
The task queue of office；
Control module, the function of the internal master controller of simulation restructural application specific processor core, according to described task queue at each mould
Transmit described mission bit stream between block, obtain from described task queue and be currently needed for the processor active task performed and the fortune that will carry out
Calculation task, scheduling computation realizes module and performs processor active task；
Computing realizes module, the merit of simulation reconfigurable controller, DMA and reconfigurable arrays within restructural application specific processor core
Can, perform several algorithm output operation result data and computing state, and perform mission bit stream, the removing of operation result data
Fortune.
The functional simulator of restructural dedicated processes core the most according to claim 1, it is characterised in that: described control module
Including Operations Analysis and status unit, Operations Analysis completes scheduling and the work of algorithm according to described mission bit stream
The management of operation mode, described mode of operation includes holotype, from pattern and debugging mode；Status control module is real according to computing
The computing state of existing module updates the external state of simulator, and described external state includes idle condition, busy condition, completes shape
State, and send interruption according to corresponding external state.
The functional simulator of restructural dedicated processes core the most according to claim 1, it is characterised in that: external interface module
Including internal storage unit and register cell, respectively correspondingly simulation SRAM and Parasites Fauna；Internal storage unit is in debugging
Under pattern, support the access of SRAM in outer bound pair restructural application specific processor core, it is provided that the computing internal memory that computing realizes module is empty
Between；The Parasites Fauna of Parasites Fauna module simulation restructural application specific processor core, resolves configuration-direct simultaneously and exports, adding and calculate
The mission bit stream of method computing.
The functional simulator of restructural dedicated processes core the most according to claim 1, it is characterised in that: computing realizes module
Including realizing the computing consolidation function block of 17 kinds of algorithm units, described algorithm unit is respectively as follows: FFT/IFFT computing, vector
Auto-correlation computation, computing cross-correlation, signed magnitude arithmetic(al), multiplying, matrix inversion operation, signed magnitude arithmetic(al), multiplying, point
Multiplication, covariance computing, the computing of real/complex FIR, real/complex Doppler's FIR computing, surely float translation operation and multiple
Number modulus computing.
The functional simulator of restructural application specific processor core the most according to claim 4, it is characterised in that: described computing collection
Closing in functional device, each algorithm unit individually contains computing realization and the data carrying of this algorithm；During computing realizes, each
Algorithm unit is all according to complexity and the data scale of corresponding algorithm, by computing breakpoint under the step of algorithm and debugging mode
Carrying out divide, control module by call concrete algorithm steps carry out each step computing realize.
The functional simulator of restructural application specific processor core the most according to claim 5, it is characterised in that computing realizes mould
Each algorithm unit in block uses the SRAM of internal storage unit simulation as computing internal memory, internal storage unit when calculating
Realize module for computing and provide the pointer of directly its internal memory of access, for walking around the read/write function of internal storage region module to it
Directly memory access.
The functional simulator of restructural application specific processor core the most according to claim 6, it is characterised in that: control module
Operations Analysis, when the computing of the algorithm unit that scheduling divides execution by step realizes, is carried out periodically by intervalometer
Timing Processing: send interruption when intervalometer arrives setting value every time, operation control module according to described interruption by external
After mouth die block dispatching computing consolidation function block completes the given step of assignment algorithm, enter in the wait next time of described idle condition
Disconnected, the most constantly circulate, until whole computing completes.
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| CN107608234A (en) * | 2017-09-20 | 2018-01-19 | 东南大学 | The dynamic accuracy emulation controller and method of a kind of reconfigurable system |
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| CN112381220B (en) * | 2020-12-08 | 2024-05-24 | 厦门壹普智慧科技有限公司 | Neural network tensor processor |
| CN112540888A (en) * | 2020-12-18 | 2021-03-23 | 清华大学 | Debugging method and device for large-scale reconfigurable processing unit array |
| CN112540888B (en) * | 2020-12-18 | 2022-08-12 | 清华大学 | Debugging method and device for large-scale reconfigurable processing unit array |
| CN116070565A (en) * | 2023-03-01 | 2023-05-05 | 摩尔线程智能科技(北京)有限责任公司 | Method and device for simulating multi-core processor, electronic equipment and storage medium |
| CN116070565B (en) * | 2023-03-01 | 2023-06-13 | 摩尔线程智能科技(北京)有限责任公司 | Method and device for simulating multi-core processor, electronic equipment and storage medium |
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