CN101196828A - Simulator and method - Google Patents
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- CN101196828A CN101196828A CNA2007103085726A CN200710308572A CN101196828A CN 101196828 A CN101196828 A CN 101196828A CN A2007103085726 A CNA2007103085726 A CN A2007103085726A CN 200710308572 A CN200710308572 A CN 200710308572A CN 101196828 A CN101196828 A CN 101196828A
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Abstract
The invention relates to the computer field, which discloses a simulator and the related method. The simulator internally comprises an instruction level CUP analog unit, a clock level CPU analog unit, a full CPU analog unit, a Trace data introduction tool and an executable script interpreter, an outer communication data processing unit, a user DLL interface, a serial switching processing unit and a parallel cooperative processing unit. By adopting the simulator and method, the invention can facilitate the system simulation with a great improvement in the aspects of performance, precision and expansibility, etc.
Description
Technical field
The present invention relates to computer realm, particularly a kind of simulator and method.
Background technology
Simulator is scientific research personnel's needed important tool in the process of research Computer Architecture, the system simulator that carry out to drive has all obtained using widely aspect a lot of owing to have the simulation precision height, can develop and characteristics such as debug system software.It is fast that desirable simulator should possess analog rate, the accuracy of simulation height, and be easy to configuration and modification, however therefore the relation of the person's of existence mutual restriction between the speed of simulator, precision and the dirigibility is difficult to get both.At present, uniprocessor becomes multinuclear by monokaryon, the supercomputer interstitial content becomes several ten thousand even hundreds of thousands by several thousand, simulate such Large Scale Computer System or following more massive computer system, and it is more outstanding that the speed of simulator, precision and flexibility problem just become.
In the monokaryon epoch in early days, in order to be adapted to needed characteristics in the practical application, the CPU element of Computer Systems Simulator also is a monokaryon.Wherein, because the focus difference of research, can there be certain difference in the simulation precision of CPU element and simulation emphasis, and for example SimOS comprises three kinds of CPU simulators, is respectively Embra, Mipsy and MXS, strengthens successively on simulation precision; SimpleScalar comprises analogue units such as sim-fast, sim-cache, sim-bpred and sim-outorder, has nothing in common with each other on the simulation emphasis.Then, along with the arriving in multinuclear epoch, the CPU element of simulator is also being expanded to the multinuclear direction by original monokaryon one after another.Before monokaryon simulator is after having increased the on-chip interconnect unit, having shared L2 cache and relevant arbitration and consistency protocol, make original C PU unit can dispose a plurality of nuclears, thereby simulate the needed polycaryon processor of academia and business circles, for example the M5 simulator.Along with further developing of multi-core technology, the large-scale parallel demands of applications is urgent day by day, thereby more and more higher to the simulator performance demands.
Simulator ubiquity simulation precision, system performance and configuration flexibility three contradiction are difficult to unified.If simulate too in detail to functional part, the real implementation status of response function parts has improved accuracy of simulation more accurately, but the performance that the system that can have influence on like this carries out, make analog rate slowly unacceptable.Simplify the performance that the simulation of functional part can the raising system be carried out, but can't obtain the effective information that system carries out, make simulation system lose reliability.If guaranteeing to carry out special optimization at specific simulator under the situation of certain simulation precision, the performance of equally can the raising system carrying out, however hindered the dirigibility of system configuration again, make simulation system become and be difficult to use.
These problems are along with the further expansion of simulation scale becomes more serious.Particularly in the high-performance computer field, system is made up of thousands of processor, memory unit and complicated network interconnection structure often.At this system in large scale, it almost is impossible using traditional full details mode to simulate.For example, traditional approach is in order to reach the unification of speed and precision, often adopt plurality of operating modes such as clock level and function level simulation are provided simultaneously, and the mode of dynamically switching between the support various modes, but during system operation arbitrary in the etching system simulation of all nodes all be positioned at identical execution pattern, and all nodes simulations all adopt the fine granularity simulation will cause analog rate can't make us accepting in the extensive goal systems.In addition, between the plurality of operating modes of traditional approach behavior still more close, especially the demand side for internal memory is more or less the same, the host memory requirements that the simulation of the internal memory of so extensive goal systems is brought will become new restraining factors again.
Therefore need the new like this characteristics of special basis to come the analysis mode emphasis, thereby choose suitable analog form, so that satisfy the expectation that the user uses simulator.So how under the prerequisite that possesses the local detail analog capability, improve the overall performance of simulator, the details carried out of reactive system to a certain extent again, and further enlarge the scale of simulation, become the new demand for development of simulator.The solution that the present invention proposes according to these needs just.
Summary of the invention
The objective of the invention is to, a kind of simulator and method are provided, to solve existing simulator and method deficiency at aspects such as simulation precision, system performance and configuration flexibilitys.
To achieve these goals, the invention provides a kind of simulator, comprise analogue unit and operational mode unit, described analogue unit is in order to simulate the CPU analogue unit of multiple different shape, and described operational mode unit is carried out in order to the switching between the CPU analogue unit of realizing described multiple different shape and collaborative the execution.
Preferable, in described simulator, in the described analogue unit, comprise that instruction-level CPU analogue unit, clock level CPU analogue unit, full CPU analogue unit, Trace data importing instrument maybe can carry out at least two kinds in script interpreter, PERCOM peripheral communication data processing unit and the user's dynamic chanining bank interface;
Described instruction-level CPU analogue unit is in order to realize instruction-level CPU analog functuion;
Described clock level CPU analogue unit is in order to realize clock level CPU analog functuion;
Described full CPU analogue unit, in order to reference to certain real CPU to simulate corresponding system;
Described Trace data importing instrument maybe can be carried out script interpreter, in order to realize the function of instruction process unit;
Described PERCOM peripheral communication data processing unit in order to receiving the director data that transmits by network, and carries out respective handling to these director datas;
Described user's dynamic chanining bank interface, in order to a group interface to be provided, its instruction process part is on the given dynamic link library of user.
Preferable, in described simulator, in the described operational mode unit, comprise serial switching treatmenting unit and concurrent collaborative processing unit;
Described serial switching treatmenting unit switches in order to the serial of the CPU analogue unit of realizing variform;
Described concurrent collaborative processing unit is in order to the concurrent collaborative of the CPU analogue unit of realizing variform;
Preferable, in described simulator, when described serial switching treatmenting unit switched in the serial of the CPU analogue unit of realizing variform, the analog form to unconcerned operational process use coarseness used fine-grained analog form to the operational process of being concerned about.
Preferable, in described simulator, in the described concurrent collaborative processing unit, comprise isomorphism synergetic unit and isomery synergetic unit;
Described isomorphism synergetic unit is used to simulate the execution of isomorphism polycaryon processor, and described isomery synergetic unit is used to simulate the execution of heterogeneous multi-nucleus processor.
To achieve these goals, the present invention also provides a kind of method of simulation, may further comprise the steps:
Step 100 is provided with analogue unit;
Step 200 is provided with the operational mode unit.
Preferable, in the method for described simulation, in the described step 100, in may further comprise the steps at least two, and its order can be arranged arbitrarily:
Step 110 is provided with instruction-level CPU analogue unit;
Step 120 is provided with clock level CPU analogue unit;
Step 130 is provided with full CPU analogue unit;
Step 140 is provided with Trace data importing instrument and maybe can carries out script interpreter;
Step 150 is provided with the PERCOM peripheral communication data processing unit;
Step 160 is provided with user's dynamic chanining bank interface.
Preferable, in the method for described simulation, in the described step 200, may further comprise the steps:
Step 210 is provided with the serial switching treatmenting unit;
Step 220 is provided with the concurrent collaborative processing unit.
Preferable, in the method for described simulation, in the described step 220, may further comprise the steps:
Step 221 is provided with the isomorphism synergetic unit;
Step 222 is provided with the isomery synergetic unit.
Preferable, in the method for described simulation:
Described instruction-level CPU analogue unit is in order to realize instruction-level CPU analog functuion;
Described clock level CPU analogue unit is in order to realize clock level CPU analog functuion;
Described full CPU analogue unit, in order to reference to certain real CPU to simulate corresponding system;
Described Trace data importing instrument maybe can be carried out script interpreter, in order to realize the function of instruction process unit;
Described PERCOM peripheral communication data processing unit in order to receiving the director data that transmits by network, and carries out respective handling to these director datas;
Described user's dynamic chanining bank interface, in order to a group interface to be provided, its instruction process part is on the given dynamic link library of user.
Preferable, in the method for described simulation, in the described operational mode unit, comprise serial switching treatmenting unit and concurrent collaborative processing unit;
Described serial switching treatmenting unit switches in order to the serial of the CPU analogue unit of realizing variform;
Described concurrent collaborative processing unit is in order to the concurrent collaborative of the CPU analogue unit of realizing variform;
Preferable, in the method for described simulation, when described serial switching treatmenting unit switched in the serial of the CPU analogue unit of realizing variform, the analog form to unconcerned operational process use coarseness used fine-grained analog form to the operational process of being concerned about.
Preferable, in the method for described simulation, in the described concurrent collaborative processing unit, comprise isomorphism synergetic unit and isomery synergetic unit;
Described isomorphism synergetic unit is used to simulate the execution of isomorphism polycaryon processor, and described isomery synergetic unit is used to simulate the execution of heterogeneous multi-nucleus processor.
The invention has the beneficial effects as follows: take a kind of simulator and method among the present invention, aspects such as system simulation, precision are greatly enhanced; Simultaneously, because the adding of the more polymorphic CPU analogue unit of simulator support of the present invention can be carried out switching, thereby guarantee the advantage of simulator in overall performance and local accuracy simultaneously between the different CPU form; Moreover, the configurability of CPU form in the simulator, make simulator can not only finish the evaluation work that traditional isomorphism and heterogeneous computer system can be born, the more important thing is, because the generalization of CPU notion, this simulator can also be simulated more extensive more specialized calculation task, thereby has improved system's extensibility in a wider context.
Description of drawings
Fig. 1 is the frame diagram of simulator of the present invention;
Fig. 2 is the whole structure figure of simulator of the present invention;
Fig. 3 is the synoptic diagram that the serial of the CPU analogue unit of variform is switched;
Fig. 4 is the synoptic diagram of concurrent collaborative of the CPU analogue unit of variform;
Fig. 5 is the process flow diagram of a kind of analogy method among the present invention.
Embodiment
In order to make purpose of the present invention, technical scheme and advantage clearer,, a kind of simulator of the present invention and method are further elaborated below in conjunction with drawings and Examples.Should be appreciated that specific embodiment described herein only in order to explanation the present invention, and be not used in qualification the present invention.
The simulator that is proposed among the present invention is the polymorphic multinuclear simulator of a kind of isomery, and the configuration of its configuration according to system architecture, single nuclear type and the configuration of operational mode decide the implementation status of simulator.Wherein,,, dispose M north bridge as disposing N CPU altogether to the configuration of system architecture, to Ci nuclear of each CPU configuration, the memory size of configuration Mi, Li CPU interconnects with it to each north bridge configuration.Configuration to single nuclear type mainly is single caryogamy to be set to different analogue units such as memory access Trace (trace) script interpreter, network interface and User Defined chained library.The operational mode of system has two kinds, and promptly single nuclear switches in the serial under dissimilar to be carried out and the execution of a plurality of dissimilar nuclear concurrent collaborative.Simulator among the present invention and method thereof make the CPU analogue unit of variform to work simultaneously, the collaborative simulation task of finishing.
Please refer to Fig. 1 and Fig. 2, Figure 1 shows that the frame diagram of simulator of the present invention, Figure 2 shows that the whole structure figure of simulator of the present invention.In the simulator 10 of the present invention, comprise that instruction-level CPU analogue unit 11, clock level CPU analogue unit 12, full CPU analogue unit 13, Trace data importing instrument maybe can carry out script interpreter 14, PERCOM peripheral communication data processing unit 15, user's dynamic chanining bank interface 16, serial switching treatmenting unit 17 and concurrent collaborative processing unit 18.
Described instruction-level CPU analogue unit 11, the mode of its execution command is, get a binary command in order, decipher, if the L/S instruction, the addressing mode according to instruction obtains the data virtual address earlier, converts the virtual address to physical address by the MMU/TLB analogue unit again, obtain data from physical address at last, perhaps deposit data in physical address; Otherwise, according to instruction semantic perform mathematical calculations, the operation of aspect such as logical operation or redirect, and correspondingly change the value of register and PC.Described instruction-level CPU analogue unit 11 once can only be carried out an instruction, and every instruction only executes just can take off an instruction, and this process constantly repeats, and just can the promotion program move forward.
Described clock level CPU analogue unit 12, it is more detailed than instruction-level CPU analogue unit 11, the simulation that has wherein added streamline, the simulation of multiple instruction emission, the simulation of bus contention, the time sequence information of the simulation of buffer consistency and instruction execution cycle and memory access delay aspect, the more effectively act of execution of analysis application.
For single Core, in order to describe the execution sequential of instruction, memory access postpones, and the information of the aspects such as conflict that cause of competition bus, need make detailed simulation to the performance element of Core, for example pipeline depth how, how many cycles, different instruction was normally carried out needed, when taking place, streamline stall needs how many cycles, how many cycles instruction or data one-level Cache need when hitting, and one-level Cache does not hit second-level cache and hits and need how many cycles, and second-level cache does not hit and carries out memory access and two-stage Cache and heavily fill out and need how many cycles, how many cycles a plurality of Core memory access need when clashing, and how many cycles reorder needs during out of order execution.
Described full CPU analogue unit 13, it is more detailed than clock level CPU analogue unit 12, except the analog information with clock level CPU analogue unit 11, also has instruction prefetch, pre decoding, register renaming, dynamic dispatching, the simulation of aspects such as branch prediction.It is the system of simulating out with reference to a real CPU, thereby can be accurately and reflect the ruuning situation of this CPU all sidedly, and Godson simulator is for example drawn up the system that comes according to the Godson processor die exactly fully.
Described Trace data importing instrument maybe can be carried out script interpreter 14, and it is in fact the instruction processing unit.Trace data importing instrument is meant that the Trace information of the program that will move imports in the simulator, and every Trace produces necessary influence to some analogue unit of simulator, changes corresponding state or data in other words conj.or perhaps.Obtaining analog result in this way, is the ultimate principle of Trace-driven simulator.Can carry out script interpreter also is an instruction process unit, and what only it received is script command, by the explanation to these orders, comes the execution of dummy instruction.Therefore it also can change the data of some analogue unit, thereby obtain final analog result.
Described PERCOM peripheral communication data processing unit 15 its essence is a group communication interface, in order to receiving the director data that transmits by network, and these director datas is carried out respective handling.It is a kind of simple expansion to existing simulator, by simplifying the simulation of CPU, conveniently is absorbed in test and the analytical work of carrying out network performance.Particularly at high-performance computing sector, big many of the system overhead that the system overhead that communication brings brings than calculating, in this case, the PERCOM peripheral communication data processing unit has been ignored the computing cost of system, helps the communication influence of the system of studying.
Described user's dynamic chanining bank interface 16 is used to provide a group interface, and its instruction process part is on the given dynamic link library of user.When simulator started, described user's dynamic chanining bank interface 16 dynamically loaded the dynamic link library of appointment, according to user's demand processing instruction.It also is a kind of expansion of existing simulator, for instruction process provides good dirigibility.
Described serial switching treatmenting unit 17 switches in order to the serial of the CPU analogue unit of realizing variform, and its synoptic diagram as shown in Figure 3.Wherein, described serial is switched: generally be the technology that adopts in order to quicken simulation process.Unconcerned operational process is used the analog form of coarseness, start-up course as operating system, initialization procedures of data base management system (DBMS) etc., and the operational process of being concerned about is used fine-grained analog form are as the memory access of application program section execution and communication behavior etc.So both can improve the speed of simulation, and can reach the purpose of simulation again.
Described concurrent collaborative processing unit 18, in order to the concurrent collaborative of the CPU analogue unit of realizing variform, its synoptic diagram in the described concurrent collaborative processing unit 18, comprises isomorphism synergetic unit 181 and isomery synergetic unit 182 as shown in Figure 4.Wherein, isomorphism synergetic unit 181 can be simulated the execution of isomorphism polycaryon processor, and isomery synergetic unit 182 can be simulated the execution of isomery with the instruction set polycaryon processor, is the operating system on this basis, the analysis of compiler and application program, the research and development service.The more important thing is that different calculating is carried out in the collaborative execution of the polymorphic multinuclear of isomery respectively, handle different data, the mode by the message transmission communicates, and therefore can simulate larger, more special application.
Please refer to Fig. 5, this is the process flow diagram of a kind of analogy method among the present invention.The process of a kind of analogy method among the present invention may further comprise the steps:
Step S100 is provided with instruction-level CPU analogue unit;
Step S200, clock level CPU analogue unit;
Step S300 is provided with full CPU analogue unit;
Step S400 is provided with Trace data importing instrument and maybe can carries out script interpreter;
Step S500 is provided with the PERCOM peripheral communication data processing unit;
Step S600 is provided with user's dynamic chanining bank interface;
Step S700 is provided with the serial switching treatmenting unit;
Step S800 is provided with the concurrent collaborative processing unit.
Wherein, the effect of each set unit does not repeat them here as previously mentioned in above-mentioned steps.
Certainly; the present invention also can have other various embodiments; under the situation that does not deviate from spirit of the present invention and essence thereof; those of ordinary skill in the art work as can make various corresponding changes and distortion according to the present invention, but these corresponding changes and distortion all should belong to the protection domain of the appended claim of the present invention.
Claims (13)
1. simulator, it is characterized in that, comprise analogue unit and operational mode unit, described analogue unit is in order to simulate the CPU analogue unit of multiple different shape, and described operational mode unit is carried out in order to the switching between the CPU analogue unit of realizing described multiple different shape and collaborative the execution.
2. a kind of simulator according to claim 1, it is characterized in that, in the described analogue unit, comprise that instruction-level CPU analogue unit, clock level CPU analogue unit, full CPU analogue unit, Trace data importing instrument maybe can carry out at least two kinds in script interpreter, PERCOM peripheral communication data processing unit and the user's dynamic chanining bank interface;
Described instruction-level CPU analogue unit is in order to realize instruction-level CPU analog functuion;
Described clock level CPU analogue unit is in order to realize clock level CPU analog functuion;
Described full CPU analogue unit, in order to reference to certain real CPU to simulate corresponding system;
Described Trace data importing instrument maybe can be carried out script interpreter, in order to realize the function of instruction process unit;
Described PERCOM peripheral communication data processing unit in order to receiving the director data that transmits by network, and carries out respective handling to these director datas;
Described user's dynamic chanining bank interface, in order to a group interface to be provided, its instruction process part is on the given dynamic link library of user.
3. a kind of simulator according to claim 1 is characterized in that, in the described operational mode unit, comprises serial switching treatmenting unit and concurrent collaborative processing unit;
Described serial switching treatmenting unit switches in order to the serial of the CPU analogue unit of realizing variform;
Described concurrent collaborative processing unit is in order to the concurrent collaborative of the CPU analogue unit of realizing variform.
4. a kind of simulator according to claim 3, it is characterized in that, when described serial switching treatmenting unit switches in the serial of the CPU analogue unit of realizing variform, analog form to unconcerned operational process use coarseness uses fine-grained analog form to the operational process of being concerned about.
5. a kind of simulator according to claim 3 is characterized in that, in the described concurrent collaborative processing unit, comprises isomorphism synergetic unit and isomery synergetic unit;
Described isomorphism synergetic unit is used to simulate the execution of isomorphism polycaryon processor, and described isomery synergetic unit is used to simulate the execution of heterogeneous multi-nucleus processor.
6. the method for a simulation is characterized in that, may further comprise the steps:
Step 100 is provided with analogue unit;
Step 200 is provided with the operational mode unit.
7. the method for a kind of simulation according to claim 6 is characterized in that, in the described step 100, and in may further comprise the steps at least two, and its order can be arranged arbitrarily:
Step 110 is provided with instruction-level CPU analogue unit;
Step 120 is provided with clock level CPU analogue unit;
Step 130 is provided with full CPU analogue unit;
Step 140 is provided with Trace data importing instrument and maybe can carries out script interpreter;
Step 150 is provided with the PERCOM peripheral communication data processing unit;
Step 160 is provided with user's dynamic chanining bank interface.
8. the method for a kind of simulation according to claim 6 is characterized in that, in the described step 200, may further comprise the steps:
Step 210 is provided with the serial switching treatmenting unit;
Step 220 is provided with the concurrent collaborative processing unit.
9. the method for a kind of simulation according to claim 8 is characterized in that, in the described step 220, may further comprise the steps:
Step 221 is provided with the isomorphism synergetic unit;
Step 222 is provided with the isomery synergetic unit.
10. the method for a kind of simulation according to claim 7 is characterized in that:
Described instruction-level CPU analogue unit is in order to realize instruction-level CPU analog functuion;
Described clock level CPU analogue unit is in order to realize clock level CPU analog functuion;
Described full CPU analogue unit, in order to reference to certain real CPU to simulate corresponding system;
Described Trace data importing instrument maybe can be carried out script interpreter, in order to realize the function of instruction process unit;
Described PERCOM peripheral communication data processing unit in order to receiving the director data that transmits by network, and carries out respective handling to these director datas;
Described user's dynamic chanining bank interface, in order to a group interface to be provided, its instruction process part is on the given dynamic link library of user.
11. the method for a kind of simulation according to claim 6 is characterized in that, in the described operational mode unit, comprises serial switching treatmenting unit and concurrent collaborative processing unit;
Described serial switching treatmenting unit switches in order to the serial of the CPU analogue unit of realizing variform;
Described concurrent collaborative processing unit is in order to the concurrent collaborative of the CPU analogue unit of realizing variform.
12. the method for a kind of simulation according to claim 11, it is characterized in that, when described serial switching treatmenting unit switches in the serial of the CPU analogue unit of realizing variform, analog form to unconcerned operational process use coarseness uses fine-grained analog form to the operational process of being concerned about.
13. the method according to claim 11 described a kind of simulation is characterized in that, in the described concurrent collaborative processing unit, comprises isomorphism synergetic unit and isomery synergetic unit;
Described isomorphism synergetic unit is used to simulate the execution of isomorphism polycaryon processor, and described isomery synergetic unit is used to simulate the execution of heterogeneous multi-nucleus processor.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101799767A (en) * | 2010-03-05 | 2010-08-11 | 中国人民解放军国防科学技术大学 | Method for carrying out parallel simulation by repeatedly switching a plurality of operation modes of simulator |
| CN101873338A (en) * | 2009-04-27 | 2010-10-27 | 华为技术有限公司 | Event synchronizing method for parallel simulation and simulators |
| CN101694628B (en) * | 2009-10-21 | 2012-07-04 | 中国人民解放军国防科学技术大学 | Parallel computer system performance simulation method by combining serial simulation and parallel simulation |
| CN105739482A (en) * | 2016-01-29 | 2016-07-06 | 大连楼兰科技股份有限公司 | Multi-vehicle-model simulation system based on Linux dynamic link library and working method thereof |
| CN107589960A (en) * | 2017-08-30 | 2018-01-16 | 北京轩宇信息技术有限公司 | A kind of DSP instruction simulation methods based on register access collision detection |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CA2412816C (en) * | 2000-06-19 | 2012-01-17 | P.C. Krause And Associates, Inc. | Distributed simulation |
| CN1780290A (en) * | 2004-11-23 | 2006-05-31 | 北京航空航天大学 | Method for realizing distributed simulated interactive running system with peer structure |
| CN1825285A (en) * | 2004-12-31 | 2006-08-30 | 钟巨航 | Data processing system with multiple sub-system and method thereof |
| JP2006215781A (en) * | 2005-02-03 | 2006-08-17 | Matsushita Electric Ind Co Ltd | Simulation device and simulation method |
| CN100336033C (en) * | 2005-02-25 | 2007-09-05 | 清华大学 | Single-chip analog system with multi-processor structure |
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2007
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101873338A (en) * | 2009-04-27 | 2010-10-27 | 华为技术有限公司 | Event synchronizing method for parallel simulation and simulators |
| CN101694628B (en) * | 2009-10-21 | 2012-07-04 | 中国人民解放军国防科学技术大学 | Parallel computer system performance simulation method by combining serial simulation and parallel simulation |
| CN101799767A (en) * | 2010-03-05 | 2010-08-11 | 中国人民解放军国防科学技术大学 | Method for carrying out parallel simulation by repeatedly switching a plurality of operation modes of simulator |
| CN101799767B (en) * | 2010-03-05 | 2013-03-06 | 中国人民解放军国防科学技术大学 | Method for carrying out parallel simulation by repeatedly switching a plurality of operation modes of simulator |
| CN105739482A (en) * | 2016-01-29 | 2016-07-06 | 大连楼兰科技股份有限公司 | Multi-vehicle-model simulation system based on Linux dynamic link library and working method thereof |
| CN107589960A (en) * | 2017-08-30 | 2018-01-16 | 北京轩宇信息技术有限公司 | A kind of DSP instruction simulation methods based on register access collision detection |
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Granted publication date: 20090819 Termination date: 20191229 |