JP2006215781A - Simulation device and simulation method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To increase the development efficiency and thus development speed of a system comprising a plurality of processors and hardware by enabling a simulation, whether synchronous or asynchronous, and enabling a fast simulation. <P>SOLUTION: A model switching part 105, when receiving an execution stop flag or processing completion flag from any processing execution control part 106, outputs an execution stop instruction to the processing execution control part 106 of a corresponding simulation model. The model switching part 105 then compares simulation times of respective simulation models to select the simulation model that has the shortest elapsed time, and outputs an execution start instruction to the processing execution control part 106 of the model. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a simulation apparatus and a simulation method, and more particularly, to a simulation apparatus and a simulation method that increase the processing time.

  2. Description of the Related Art Conventionally, when developing hardware, a processor, and software that runs on the processor, a simulation apparatus that models each hardware or processor and executes it in a simulated manner is generally used. In the simulation apparatus, each hardware or processor model is operated and an instruction is executed for each operation clock that is a processing unit. However, it is necessary to switch each model of the simulation apparatus every clock, and there is a problem that the overhead for that is increased and simulation time is required.

Therefore, in order to shorten the simulation time, a simulation apparatus as shown in Patent Document 1 is known. Referring to an example of execution of a program by a processor as shown in FIG. 9, instructions 1 # 10 and 2 # 11 for a plurality of clocks are executed in the processor without switching models until an exchange with an external peripheral circuit occurs. And count the number of clocks executed. When the communication with the peripheral circuit occurs, the instruction 3 # 12 is executed by executing the peripheral circuit by the number of clocks executed in the processor. With such a configuration, the switching amount of each model can be reduced, and the simulation time can be shortened.
JP-A-8-328905

  However, in the conventional apparatus, the simulation speed can be increased with a single processor. However, since it cannot be applied when a plurality of processors and hardware operate in parallel, the simulation speed of such a model is high. There is a problem that it cannot be converted. Further, the conventional apparatus has a problem that it cannot be applied when asynchronously communicating between a plurality of processors and hardware.

  The present invention has been made in view of the above points, and can perform simulation regardless of whether it is synchronous or asynchronous, and can perform high-speed simulation, and the development efficiency of a system composed of a plurality of processors and hardware. An object of the present invention is to provide a simulation apparatus and a simulation method capable of improving the development speed and improving the development speed.

  The simulation apparatus according to the present invention executes a plurality of simulation model means for performing a simulation of each of a plurality of systems and the simulation model means being executed based on switching information that is information for switching the simulation model means. A model switching unit that switches to stop and start execution of the other simulation model unit is adopted.

  According to the simulation method of the present invention, the simulation model being executed is stopped based on the step of performing simulation of each of a plurality of simulation models, and switching information that is information for switching execution of the simulation model. Switching to start execution of the simulation model.

  According to the present invention, simulation is possible regardless of whether it is synchronous or asynchronous, high-speed simulation can be performed, the development efficiency of a system composed of a plurality of processors and hardware is improved, and the development speed is improved. be able to.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(Embodiment 1)
FIG. 1 is a block diagram showing a configuration of a simulation apparatus 100 according to Embodiment 1 of the present invention.

  As shown in FIG. 1, the simulation apparatus 100 includes a simulation model unit (hereinafter referred to as “simulation model”) 101 to 103 simulating a plurality of processors and hardware, an output information storage unit 104, and a model switching unit. 105.

  Each of the simulation models 101 to 103 includes a process execution control unit 106, a time measurement unit 107, an input information storage unit 108, and an internal state storage unit 109.

  The output information storage unit 104 stores the output information output from the process execution control unit 106. If there is a request for obtaining output information from the input information storage unit 108, the corresponding output information is output to the input information storage unit 108.

  When the execution stop flag or the process completion flag is input from the process execution control unit 106, the model switching unit 105 outputs an execution stop instruction to the process execution control unit 106 of the simulation model. At this time, the simulation time of each simulation model is compared, the simulation model having the shortest elapsed time is selected, and an execution start command is output to the process execution control unit 106 of the model.

  When a process execution start command is input from the model switching unit 105, the process execution control unit 106 outputs an input information acquisition command to the input information storage unit 108, and changes the internal state of the model from the internal state storage unit 109. Read and set internal state. Thereafter, until a process execution stop command is received from the model switching unit 105, the process of the simulation model is executed every clock and an execution completion flag is output to the time measurement unit 107. If there is an input value corresponding to the input information acquisition command from the input information storage unit 108, the processing is executed using it. When all the processes of the simulation model are completed, a process completion flag is output to the model switching unit 105.

  In addition, in the process of the simulation model, the process execution control unit 106 stores the simulation time, the output value, and its address input from the time measurement unit 107 as output information storage when outputting to another simulation model. Output to the unit 104.

  In addition, the process execution control unit 106, when processing of the simulation model requires input of output information that is information output from another simulation model, The address is output to the input information storage unit 108, the internal state of the simulation model is stored in the internal state storage unit 109, the processing stop flag (switching information) is output to the model switching unit 105, and the next instruction is executed. Prepare.

  Each time the execution completion flag is input from the process execution control unit 106, the time measurement unit 107 increments the simulation time of the simulation model by one clock. The current time of the simulation model is output to the process execution control unit 106 and the model switching unit 105 each time.

  The input information storage unit 108 stores the simulation time and address input from the process execution control unit 106 as input information to the simulation model. When the input information acquisition command is input from the process execution control unit 106 and the input information of the simulation model is stored in the output information storage unit 104, the corresponding input value is output from the output information storage unit 104. Is output to the process execution control unit 106.

  Next, the operation of the simulation apparatus 100 will be described in detail using the flowchart shown in FIG.

  First, in ST201, the model switching unit 105 selects any one simulation model 101 and outputs an execution start command to the selected simulation model 101. Upon receiving this execution start command, the process execution control unit 106 of the simulation model 101 outputs an input information acquisition command to the input information storage unit 108. Also, the internal state is read from the internal state storage unit 109 and the internal state is set.

  In ST202, the input information storage unit 108 checks whether there is input information. If there is, the output information stored in the output information storage unit 104 based on the address information output by the other simulation models 102 and 103 in ST203. Is read out, the corresponding value is obtained from the output information storage unit 104, and is output to the process execution control unit 106.

  Next, the process execution control unit 106 performs processing for one clock in ST204. When an input value is obtained in ST203, processing is performed using the input value. When there is an output in this process (ST205), the current time obtained from the time measuring unit 107 in ST206, the output information address and the output value are output to the output information storage unit 104. When the processing is completed, an execution completion flag is output to the time measuring unit 107.

  Next, when the time measurement unit 107 obtains an execution completion flag from the process execution control unit 106 in ST207, the time measurement unit 107 increments the current time by one clock, and outputs the incremented value to the process execution control unit 106 and the model switching unit 105. If the process of the simulation model 101 is completed in ST208, the process execution control unit 106 outputs a process completion flag to the model switching unit 105, and proceeds to ST212. If not completed, the process proceeds to ST209.

  In ST209, the process execution control unit 106 checks whether or not there is an input in the next process. If there is no input, the process execution control unit 106 returns to ST204 and executes the next instruction. On the other hand, if there is an input, the current time and the address and output value of the input information obtained from time measuring section 107 in ST210 are stored in input information storage section 108. Further, the execution stop flag is output to the model switching unit 105. When the model switching unit 105 receives the execution stop flag, the model switching unit 105 outputs a process execution stop command to the simulation model 101 being executed. Next, in ST211, the model switching unit 105 compares the simulation time of each model obtained from the time measurement unit 107 of each simulation model 102, 103, selects the simulation model 102 with the least elapsed time, A process execution start instruction is output to the simulation model 102, the simulation model is switched, and the process returns to ST202.

  In ST211, the process execution control unit 106 of the switched simulation model 101 stores the state in the simulation model 101 in the internal state storage unit 109 when a process execution stop command is input. In some cases, the same simulation model 101 may be selected continuously. In this case, it is not necessary to store the state in the simulation model 101. Therefore, when the process execution control unit 106 receives a process execution stop instruction and a process execution start instruction simultaneously in ST211, the state in the simulation model 101 is not stored, and the process returns to ST202.

  Further, when the processing completion flag is input to the model switching unit 105 in ST212, the model switching unit 105 confirms whether the processing of all the simulation models 101 to 103 is completed. If there is a simulation model that has not been completed, the process proceeds to ST211. In addition, when all the simulation models 101 to 103 have been processed, the simulation is ended.

  Next, the execution sequence by the simulation apparatus 100 will be described using FIG. 3 as an example of processing when the three processors 301 to 303 share one memory 401 as shown in FIG. In the following description, it is assumed that each processor executes one instruction in one clock.

  First, when the processor 301 is selected as a simulation model, instructions 1 to 12 are not input from the outside, and therefore processing is continuously executed on the processor 301. In the middle, instructions 2 and 6 are output to the outside, and the time, address, and output value are stored in the output information storage unit 104. In this figure, an arrow on the outside from each of the processors 301 to 303 indicates an output, and an arrow on the inside indicates an input. Ver1 [2] indicates that the value of the address Ver1 at time 2 is output.

  Next, since there was an input at time 12 of the processor 301, the processor 301 stops immediately before execution of the instruction 12, stores the input information and internal state, and the processing shifts to the other processors 302 and 303. Since neither the processor 302 nor the processor 303 has been executed yet, either one may be selected. Here, the processor 302 is selected. In the processor 302, instructions 1 to 7 are executed, and output information is stored in the instructions 3 and 5 on the way. After the input information and internal information at time 7 of the processor 302 are stored, the processing shifts to the processor 303 and instructions 1 to 4 are executed.

  Here, the output information of each of the processors 301 to 303 includes a time, an address, and an output value, and it is necessary to store information having different times even if they are the same address. This is because the processing of each of the processors 301 to 303 is asynchronous in the simulation time, and even if it is obvious that the same address is overwritten, the state before overwriting may be required. is there.

  After the instruction 303 is executed by the processor 303, the model switching unit 105 compares the elapsed times of the processors 301 to 303, and selects the processor 303 having the shortest elapsed time. Therefore, the processor 303 is continuously executed. The processor 303 acquires the input information that is to be obtained by the instruction 4 from the output information storage unit 104. In the figure, Ver [4], that is, Ver4 information at time 4 is required, but this is because Ver4 output information at time 3 output by instruction 3 of processor 302 is also maintained at time 4. Therefore, this corresponds to the input information at the time of instruction 4 of the processor 303. Using this input information, the instruction 4 of the processor 303 is processed, and the processes from the instruction 5 to the instruction 12 are subsequently performed.

  Similarly, the processing shifts to the processor 302, and the value of Ver2 output by the instruction 6 of the processor 301 is acquired as input information in the instruction 7, and the instruction 7 is processed. Subsequently, the processes from the instruction 8 to the instruction 16 are performed. Since all processing is completed for the processor 30 by the instruction 16, the processing is transferred to the processor 301 by the model switching unit 105. The processor 301 performs the processing from the instruction 12 to the instruction 16, and finally the processor 303 performs the processing from the instruction 12 to the instruction 16 to finish the simulation.

  As shown in the example of FIG. 3, the present invention uses the fact that the execution result of the output model without any input can be executed independently of other simulation models, and when the simulation model is switched. It is characterized in that the switching overhead can be reduced by using only.

  Also, by storing all output information at different times from each simulation model, a plurality of processors and hardware are compatible with a simulation model that operates asynchronously.

  When past output information is no longer needed, the amount of information to be stored in the output information storage unit 104 can be reduced by deleting it. The case where the past output information is no longer needed is when there are two or more pieces of information with the same address that are older than the elapsed time of all models. At this time, only the latest information is left and the subsequent information is deleted. be able to.

  As described above, according to the first embodiment, when input of output information from another simulation model is required, the execution is stopped and the simulation model having the shortest execution time is switched. Even when the processor and hardware operate in parallel and communicate asynchronously, simulation can be executed at high speed. Further, according to the first embodiment, the development efficiency of a system composed of a plurality of processors and hardware can be improved and the development speed can be improved.

(Embodiment 2)
FIG. 5 is a block diagram showing a configuration of simulation apparatus 500 according to Embodiment 2 of the present invention.

  The simulation apparatus 500 according to the second embodiment is different from the simulation apparatus 100 according to the first embodiment shown in FIG. 1 in that a processing stop time setting unit 501 is added as shown in FIG. Has a model switching unit 502. 5, parts having the same configuration as in FIG. 1 are denoted by the same reference numerals and description thereof is omitted.

  The process stop time setting unit 501 specifies a simulation stop time. The designation method includes a certain absolute time on the simulation and a relative time from the current simulation time.

  The model switching unit 502 compares the simulation stop time information (switching information) input from the process stop time setting unit 501 with the current time of the simulation model input from the time measurement unit 107, and the time when they match. Then, an execution stop command is output to the process execution control unit 106 of the simulation model being executed, and control is transferred to another simulation model. In addition, the model switching unit 502 compares the simulation time of each simulation model, selects the simulation model having the shortest elapsed time, and outputs an execution start command to the process execution control unit 106 of the model. Similarly, other simulation models are executed until the simulation stop time, and the execution is stopped.

  With such a configuration, all models on the simulation apparatus are executed up to a designated arbitrary simulation time, and all model states at this time can be observed. Further, since all the information stored in the output information storage unit 104 at this time can be deleted except for the latest information for each address, the storage amount of the output information can be reduced.

  As described above, according to the second embodiment, when the preset simulation stop time and the time measured by the time measurement unit 107 coincide with each other, the execution is stopped and the simulation model with the shortest execution time is obtained. Since switching is performed, a plurality of processors and hardware operate in parallel, and simulation can be executed at high speed even when communicating asynchronously. Further, according to the second embodiment, the development efficiency of a system composed of a plurality of processors and hardware can be improved and the development speed can be improved. Further, according to the second embodiment, it is possible to obtain information on all processors and peripheral circuits at an arbitrary simulation time while performing a high-speed simulation. Further, according to the second embodiment, by setting the time appropriately, simulation can be executed at high speed even in an environment where the storage amount of the output information storage unit 104 is limited.

  In addition, you may comprise so that this Embodiment 2 and Embodiment 1 may be combined suitably.

(Embodiment 3)
FIG. 6 is a block diagram showing a configuration of simulation apparatus 600 according to Embodiment 3 of the present invention.

  The simulation apparatus 600 according to the third embodiment adds an output information storage amount monitoring unit 602 as shown in FIG. 6 to the output information storage unit 104 in the simulation apparatus 100 according to the first embodiment shown in FIG. And an output information storage unit 601, and a model switching unit 603 instead of the model switching unit 105. In FIG. 6, parts having the same configuration as in FIG.

  The output information storage unit 601 stores the output information from the process execution control unit 106 and outputs the information (switching information) of the current stored information amount of the output information storage unit 601 to the output information storage amount monitoring unit 602. The output information storage amount monitoring unit 602 compares a preset threshold value with the stored information amount at each time point, and if the stored information amount exceeds the threshold value, the model switching unit 603 sets a storage information amount excess flag. Output.

  When the storage information amount excess flag is input from the output information storage amount monitoring unit 602, the model switching unit 603 outputs an execution stop instruction to the process execution control unit 106 of the simulation model being executed, and another simulation model Transfer control to. At this time, all the information stored in the output information storage unit 601 can be deleted except for the latest information for each address, and the amount of output information stored can be reduced. Further, the model switching unit 603 compares the simulation time of each simulation model, selects a simulation model having the shortest elapsed time, and outputs an execution start command to the process execution control unit 106 of the model.

  In addition, the optimum threshold value to be compared with the stored information amount varies depending on the execution form of the simulation. it can. In particular, the amount of stored information can be kept low by combining with the designation of the processing stop time as shown in the second embodiment.

  As described above, according to the third embodiment, when the amount of stored information is equal to or greater than the threshold value, the execution is stopped and the simulation model with the shortest execution time is switched, so that a plurality of processors and hardware are parallel. Even when asynchronously communicating, simulation can be executed at high speed. Further, according to the third embodiment, the development efficiency of a system composed of a plurality of processors and hardware can be improved and the development speed can be improved. Further, according to the third embodiment, by appropriately setting the threshold value of the stored information amount, the simulation can be executed at high speed even if the stored information amount of the output information storage unit 601 is limited.

  In addition, you may comprise so that this Embodiment 3 and Embodiment 1 or Embodiment 2 may be combined.

(Embodiment 4)
FIG. 7 is a block diagram showing a configuration of a simulation apparatus 700 according to Embodiment 4 of the present invention.

  The simulation apparatus 700 according to the fourth embodiment adds a processing stop position setting unit 701 to the simulation apparatus 100 according to the first embodiment illustrated in FIG. 1 and replaces the model switching unit 105 as illustrated in FIG. And a process execution control unit 703 instead of the process execution control unit 106. In FIG. 7, parts having the same configuration as in FIG.

  The process stop position setting unit 701 specifies a stop position on the simulation model. For example, the stop position is an arbitrary instruction address executed by the processor.

  The model switching unit 702 sets the stop position information (switching information) input from the process stop position setting unit 701 in the process execution control unit 703 of the corresponding simulation model. The simulation model process execution control unit 703 in which the stop position is designated outputs an execution stop flag to the model switching unit 702 when the process reaches the stop position. When the execution stop flag is input, the model switching unit 702 outputs a process execution stop instruction to the simulation model, and transfers control to another simulation model. At this time, the model switching unit 702 compares the simulation time of each simulation model, selects the simulation model having the shortest elapsed time, and outputs an execution start command to the process execution control unit 703 of the model. To do.

  As described above, according to the fourth embodiment, when the execution in the simulation model reaches the execution stop position set in advance, the execution is stopped and switched to the simulation model having the shortest execution time. Even when the processor and hardware operate in parallel and communicate asynchronously, simulation can be executed at high speed. Further, according to the fourth embodiment, the development efficiency of a system composed of a plurality of processors and hardware can be improved and the development speed can be improved. Further, according to the fourth embodiment, it is possible to obtain information on all processors and peripheral circuits at the time when an arbitrary position on the model is reached while performing high-speed simulation. As a specific example, the effect of high-speed simulation can be obtained while corresponding to the simulation stop setting by the breakpoint.

  In addition, you may comprise so that this Embodiment 4 and Embodiment 1-3 may be combined suitably.

(Embodiment 5)
FIG. 8 is a block diagram showing a configuration of simulation apparatus 800 according to Embodiment 5 of the present invention.

  The simulation apparatus 800 according to the fifth embodiment adds an execution format instruction unit 801 as shown in FIG. 8 to the simulation apparatus 100 according to the first embodiment shown in FIG. A model switching unit 802 is included. In FIG. 8, parts having the same configuration as in FIG.

  The execution format instruction unit 801 is an arbitrary execution format from among a high-speed simulation execution format in which switching of simulation models is suppressed as much as in Embodiment 1 and a simulation execution format in which simulation models are switched for each processing unit. The selected execution format information (switching information) is output to the model switching unit 802.

  The model switching unit 802 performs control according to the execution format information input from the execution format instruction unit 801. That is, when a high-speed simulation execution format is selected, the model switching unit 802 performs the same control as in the first embodiment, and selects a simulation execution format for switching simulation models for each processing unit. In this case, each time one process is performed, the simulation model is switched and the simulation is executed. In addition, when switching to another simulation model, the model switching unit 802 compares the simulation time of each of the other simulation models, selects the simulation model having the shortest elapsed time, and controls processing execution of the model An execution start instruction is output to the unit 106.

  As described above, according to the fifth embodiment, since the simulation model of the execution format that requires a high execution speed reduces the number of times of switching, a plurality of processors and hardware operate in parallel. In addition, even when communicating asynchronously, simulation can be executed at high speed. Further, according to the fifth embodiment, the development efficiency of a system composed of a plurality of processors and hardware can be improved and the development speed can be improved. Further, according to the fifth embodiment, verification combining high-speed simulation and execution for each processing time unit can be performed. As a specific example, simulation execution by step execution and high-speed simulation can be used in combination.

  In the fifth embodiment, the execution mode is selected from two execution formats: a high-speed simulation execution format and a simulation execution format for switching the simulation model for each processing unit. The execution format may be arbitrarily selected from three or more execution formats having different speeds. At that time, the model switching unit 802 causes the number of switching times in a predetermined time to decrease as the requested execution format has a higher execution speed. Moreover, you may comprise so that this Embodiment 5 and Embodiment 1-4 may be combined suitably.

  In the first to fifth embodiments, it is decided to switch to start execution of another simulation model having the shortest execution time. However, the present invention is not limited to this, and execution of any simulation model is started. It may be switched as follows. Moreover, in the said Embodiment 1-Embodiment 5, the number of simulation models can be made arbitrary.

  The simulation apparatus and the simulation method according to the present invention are suitable for a simulation apparatus with a high processing time, and particularly suitable for simulation when a plurality of processors and hardware operate in parallel and communicate asynchronously. is there.

The block diagram which shows the structure of the simulation apparatus which concerns on Embodiment 1 of this invention. The flowchart which shows operation | movement of the simulation apparatus which concerns on Embodiment 1 of this invention. The figure explaining the execution order of the simulation apparatus which concerns on Embodiment 1 of this invention The figure which shows the model structure of the example of execution of the simulation apparatus which concerns on Embodiment 1 of this invention. The block diagram which shows the structure of the simulation apparatus which concerns on Embodiment 2 of this invention. The block diagram which shows the structure of the simulation apparatus which concerns on Embodiment 3 of this invention. Block diagram showing a configuration of a simulation apparatus according to Embodiment 4 of the present invention Block diagram showing a configuration of a simulation apparatus according to Embodiment 5 of the present invention The figure explaining operation of the conventional simulation device

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Simulation apparatus 101,102,103 Simulation model 104 Output information storage part 105 Model switching part 106 Process execution control part 107 Time measurement part 108 Input information storage part 109 Internal information storage part

Claims (8)

A plurality of simulation model means for simulating each of a plurality of systems;
Based on switching information which is information for switching the simulation model means, model switching means for switching to stop execution of the simulation model means being executed and to start execution of the other simulation model means;
A simulation apparatus comprising:   When the switching information indicating that it is necessary to input output information, which is information output from the other simulation model means, is input to the simulation model means being executed. 2. The simulation apparatus according to claim 1, wherein switching is performed so as to start execution of the other simulation model means. The simulation model means measures time on simulation,
The model switching means switches so as to start execution of the other simulation model means when the simulation stop time as the switching information set in advance coincides with the time measured by the simulation model means. The simulation apparatus according to claim 1, wherein: Output information storage means for storing output information from the simulation model means;
Comprising output information storage amount monitoring means for comparing the storage information amount of the predetermined simulation model means in the output information storage means with a threshold;
When the output information storage amount monitoring unit detects that the stored information amount as the switching information is equal to or greater than the threshold, the model switching unit determines whether the simulation model unit being executed is another The simulation apparatus according to claim 1, wherein the simulation apparatus is switched to the simulation model unit.   The model switching means switches to start execution of the other simulation model means when execution in the simulation model means reaches an execution stop position that is the preset switching information. The simulation apparatus according to any one of claims 1 to 4. Comprising execution format instruction means for selecting any of the execution formats from among a plurality of execution formats of simulation models having different required execution speeds,
The model switching unit is configured so that the number of times of switching in a predetermined time is reduced as the execution format has a higher execution speed than the execution format information that is the switching information selected by the execution format instruction unit. 6. The simulation apparatus according to claim 1, wherein switching is performed so as to start execution of the other simulation model means.   The simulation apparatus according to claim 1, wherein the model switching unit performs switching so as to start execution of another simulation model unit having the shortest execution time. Performing each simulation of a plurality of simulation models;
Based on switching information that is information for switching the execution of the simulation model, the step of switching to stop the simulation model being executed and start the execution of another simulation model;
A simulation method comprising:

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