CN112379370A - SAR system based on full silicon-based chip - Google Patents
SAR system based on full silicon-based chip Download PDFInfo
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- G—PHYSICS
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- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S13/00—Systems using the reflection or reradiation of radio waves, e.g. radar systems; Analogous systems using reflection or reradiation of waves whose nature or wavelength is irrelevant or unspecified
- G01S13/88—Radar or analogous systems specially adapted for specific applications
- G01S13/89—Radar or analogous systems specially adapted for specific applications for mapping or imaging
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
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Abstract
The present disclosure provides an SAR system based on full silicon-based chip, including: the phase-locked loop chip is used for generating frequency-modulated continuous wave signals; the input end of the phased array transceiving front-end chip is connected with the phase-locked loop chip and is used for carrying out multichannel amplitude-phase modulation on the input frequency modulation continuous wave signal and then outputting the frequency modulation continuous wave signal to a phased array antenna for transmitting, receiving the phased array antenna signal at the same time, completing multichannel amplitude-phase modulation, and carrying out down-conversion after combining to obtain an intermediate-frequency signal; and the intermediate frequency amplification chip is connected with the phased array transceiving front end chip and is used for amplifying and controlling the gain of the input intermediate frequency signal, providing a sufficient dynamic range, tuning band-pass filtering and outputting the intermediate frequency signal to the digital sampling unit.
Description
Technical Field
The disclosure relates to the technical field of radars, in particular to an SAR system based on a full-silicon-based chip.
Background
With the development of Unmanned Aerial Vehicle (UAV) technology, miniaturization and generalization are the development trend of UAVs, and light and small UAVs have become powerful means for fast response and short-range detection in complex environments due to their advantages of good maneuvering performance, no risk of casualties, and the like.
At present, light and small unmanned aerial vehicles carrying micro optical and infrared sensing systems are widely applied, but are easily affected by light radiation sources such as cloud, rain and natural light, so that small microwave loads with all-weather sensing capability become research hotspots in recent years, and have wide application requirements in the aspects of high-resolution imaging, detection, target detection, environment monitoring, moving-eye tracking and the like. The miniaturized SAR reduces the system complexity by introducing an FMCW system, and can reduce the volume, weight, power consumption and cost compared with the traditional pulse system radar, but the light and small unmanned aerial vehicle puts forward more strict requirements on the volume, weight, power consumption and the like of a microwave load; a conventional micro SAR design scheme is shown in fig. 1, and includes units such as digital-to-analog conversion (DAC) or direct frequency synthesis (DDS), up-conversion, clock, etc., and has the disadvantages of complex structure, high manufacturing cost, large power consumption, easy signal leakage, severe loss, single function, and severe index deterioration when chip integration is adopted.
Disclosure of Invention
Technical problem to be solved
Based on the above problems, the present disclosure provides an all-silicon-based chip-based SAR system to alleviate technical problems in the prior art, such as complex SAR structure, high manufacturing cost, large power consumption, easy signal leakage, serious loss, single function, and serious index deterioration when chip integration is adopted.
(II) technical scheme
In one aspect of the present disclosure, a full silicon-based chip-based SAR system is provided, including: the phase-locked loop chip is used for generating frequency-modulated continuous wave signals; the input end of the phased array transceiving front-end chip is connected with the phase-locked loop chip and is used for carrying out multichannel amplitude-phase modulation on the input frequency modulation continuous wave signal and then outputting the frequency modulation continuous wave signal to a phased array antenna for transmitting, receiving the phased array antenna signal at the same time, completing multichannel amplitude-phase modulation, and carrying out down-conversion after combining to obtain an intermediate-frequency signal; and the intermediate frequency amplification chip is connected with the phased array transceiving front end chip and is used for amplifying and controlling the gain of the input intermediate frequency signal, providing a sufficient dynamic range, tuning band-pass filtering and outputting the intermediate frequency signal to the digital sampling unit.
According to an embodiment of the present disclosure, the phase-locked loop chip includes: the phase frequency detector is connected with an external crystal oscillator and inputs the external crystal oscillator as a reference signal of the phase frequency detector; one end of the voltage-controlled oscillator is connected with the phase frequency detector through a loop filter, and the other end of the voltage-controlled oscillator is connected with the phase frequency detector through a frequency divider; the frequency division of a feedback signal output by the voltage-controlled oscillator is compared with the reference signal in the phase frequency detector, and the generated phase detection error is filtered and adjusted by the loop filter and then is used as a control signal of the voltage-controlled oscillator, so that a negative feedback system is formed to control the output of the frequency-modulated continuous wave signal of the voltage-controlled oscillator.
According to the embodiment of the disclosure, the frequency divider is a fast modulation fractional frequency divider, and the phase-locked loop chip realizes generation of a chirp continuous wave signal by fast modulating the fractional frequency divider.
According to the embodiment of the present disclosure, the phased array transceiver front end chip includes: the device comprises a plurality of paths of transmitting units and receiving units connected with a phased array antenna, and a power synthesis unit; wherein the power combining unit includes: the transmitting power divider is used for distributing the frequency modulation continuous wave signals to the multi-path transmitting units for processing and then inputting the processed signals into the phased array antenna; and the receiving combiner is used for combining the phased array antenna receiving signals processed by the multipath receiving unit.
According to the embodiment of the disclosure, each path of the transmitting unit comprises: the drive amplifier, the coupler, the numerical control attenuator, the phase shifter and the power amplifier are connected in sequence; the method for distributing the frequency-modulated continuous wave signals to the multiple transmitting units for processing comprises the following steps: and completing the amplification and amplitude-phase control of the frequency modulation continuous wave signals, and coupling a part of signals as a local oscillator of the receiving unit.
According to the embodiment of the present disclosure, each of the receiving units includes: the low noise amplifier, the phase shifter, the numerical control attenuator and the frequency mixer are connected in sequence; and the processing by the multipath receiving unit comprises the steps of finishing low-noise amplification and amplitude-phase control of the phased array antenna receiving signal and carrying out down-conversion to intermediate frequency.
According to the embodiment of the disclosure, the intermediate frequency amplification chip comprises a bandwidth tunable band-pass filter and a multi-stage variable gain amplifier which are sequentially connected; the left band of the band-pass filter with the tunable bandwidth mainly aims at the direct wave suppression requirement of an SAR system, a higher suppression degree is required at the low frequency of kHz, and a pass band is required to be formed after the level of hundred kHz; meanwhile, the right side band position can be adjusted in the intermediate frequency passband range to adapt to different acting distances of the SAR system.
According to the embodiment of the disclosure, the multistage variable gain amplifier provides sufficient gain for the SAR system on one hand, and additionally has an automatic gain control function to provide a larger dynamic range.
According to the embodiment of the disclosure, the phase-locked loop chip, the phased array transceiving front-end chip and the intermediate frequency amplification chip are all fully integrated by adopting a CMOS (complementary metal oxide semiconductor) process.
(III) advantageous effects
According to the technical scheme, the SAR system based on the all-silicon-based chip has at least one or part of the following beneficial effects:
(1) the defects of complex system and high volume power consumption of the traditional DAC and other schemes are effectively overcome, and system transmission signals have the advantages of good spurious suppression characteristics and low far-end noise.
(2) A plurality of receiving and transmitting channels are integrated on the chip, and each channel can independently realize amplitude and phase control, so that the capacity of forming beam scanning by matching with a phased array antenna can be applied to a wider application range, and meanwhile, the volume and the power consumption of the chip are relatively low, and higher transmitting power can be synthesized compared with a traditional single-transmitting single-receiving front-end chip.
(3) The device has the characteristics of small volume and low power consumption, is suitable for integration of miniaturized FMCW-SAR, can automatically tune the dynamic range, and is suitable for imaging observation of different distances and different targets.
(4) The digital chip integration which also adopts the CMOS process with the back end is convenient, and the volume weight and the power consumption of the system can be effectively reduced; meanwhile, the silicon-based process has low cost and good process maturity and consistency, and is convenient for large-scale production in the later period.
Drawings
Fig. 1 is a schematic diagram of a component architecture of a typical small SAR system in the prior art.
Fig. 2 is a schematic diagram of a composition architecture of an all-silicon-based chip-based SAR system according to an embodiment of the present disclosure.
[ description of main reference numerals in the drawings ] of the embodiments of the present disclosure
1. A phase frequency detector; 2. a loop filter; 3. a voltage controlled oscillator; 4. a frequency divider; 5. a driver amplifier; 6. a coupler; 7. a numerical control attenuator; 8. a phase shifter; 9. a power amplifier; 10. a low noise amplifier; 11. a mixer; 12. a band-pass filter with tunable bandwidth; 13. a multi-stage variable gain amplifier.
Detailed Description
The SAR system based on the all-silicon-based chip effectively reduces the volume and the weight of the load by means of radar system chip, and can break through a miniature SAR system of ten gram order to meet the application requirements of the light and small unmanned aerial vehicle; the core module is based on a full silicon-based chip, and the defects of low integration level and large volume power consumption of the traditional synthetic aperture radar system are overcome.
The inventor finds that the traditional SAR radar signal generation scheme is complex, the power consumption volume is large, and chip integration is not used in the process of realizing the SAR radar signal generation method. The high-frequency DAC in the traditional radar signal generation scheme consumes power, frequency multiplication loss, mixing loss, filtering loss and other factors, which cause higher system power consumption, brings design difficulties of small volume and high heat consumption, and the heat dissipation is one of the technical bottlenecks of the scheme for realizing the chip SAR system; secondly, a new intermodulation signal can be generated by a frequency mixing and frequency doubling method, and the chip implementation of the scheme can cause the serious deterioration of the stray index of the transmitted signal and greatly influence the performance index of the system; meanwhile, the system needs to generate signals such as an ADC clock, a DAC clock, and a local oscillator clock, and the system clock unit is relatively complex, which is not favorable for realizing the system on chip. The traditional SAR radar transceiver module is complex in system, serious in high-frequency signal leakage and loss and single in function. The traditional radar transceiver module is often composed of separate elements, including a driving amplifier, a coupler, a power amplifier, a filter, a low-noise amplifier, a mixer and the like, and a signal link is long, so that the loss of signal energy is serious, and high-frequency signals are leaked; meanwhile, the transmitting power of the traditional single-transmitting single-receiving front end is mainly pushed by a final-stage power amplifier, and the traditional single-transmitting single-receiving front end has a single function and cannot support advanced phased array system radars. The intermediate frequency channel link of the traditional SAR radar is long, and the volume power consumption is large. The radar receiving unit needs to provide enough gain and a larger dynamic range, and because the gain provided by the receiving front section is limited, an intermediate frequency receiving unit needs to be added after down-conversion to provide gain and attenuation control, a multi-stage intermediate frequency amplifier and a numerical control attenuator are needed, and the volume power consumption is larger. Meanwhile, the frequency modulated continuous wave SAR needs to suppress direct waves of kHz level, and the high-pass filter with low frequency occupies a large space. The compound semiconductor is difficult to integrate with a back-end silicon-based digital chip, and the manufacturing cost is high. The radar system is generally divided into a radio frequency part and a digital part, wherein the digital part adopts a relatively mature silicon-based chip at present, the radio frequency part widely adopts compound chips with relatively excellent performance such as GaAs, GaN and the like at present, but the two parts are difficult to integrate into a whole due to process differences, so that the radar system has a larger volume; meanwhile, the compound process cost is high, and different process procedures are required to be adopted for different types of chips, so that the consistency is not high.
The present disclosure provides a technical solution of a Frequency Modulated Continuous Wave (FMCW) SAR system based on an all-silicon-based chip, and the SAR system based on the all-silicon-based chip mainly includes three aspects: 1. phase-locked linear frequency modulation source based on CMOS technology: the CMOS technology is adopted to realize the fully integrated phase-locked loop chip, and the generation of high-linearity frequency modulation continuous wave signals is realized. 2. Phased array transmit-receive front end chip based on CMOS technique: the CMOS technology is adopted to realize the fully integrated phased array transceiving front end chip, and the wide scanning range and the larger power output are realized. 3. An intermediate frequency receiving unit chip based on CMOS technology: the CMOS technology is adopted to realize the integrated integration of the multistage variable gain intermediate frequency amplifier, the bandwidth tunable filter and the like, and the system volume is greatly reduced.
For the purpose of promoting a better understanding of the objects, aspects and advantages of the present disclosure, reference is made to the following detailed description taken in conjunction with the accompanying drawings.
In an embodiment of the present disclosure, an all-silicon-based chip-based SAR system is provided, as shown in fig. 2, the all-silicon-based chip-based SAR system includes:
the phase-locked loop chip is used for generating a high-linearity frequency-modulated continuous wave signal;
the input end of the phased array transceiving front-end chip is connected with the phase-locked loop chip and is used for distributing the frequency modulation continuous wave signals generated by the phase-locked loop chip to the multi-channel transmitting unit, and outputting the signals to the phased array antenna for transmission after amplitude-phase modulation; simultaneously receiving phased array antenna signals, completing multi-channel received amplitude-phase modulation, and performing down-conversion by using a transmitting coupling signal as a local oscillator after combining to obtain an intermediate frequency signal; the wide scanning range and the larger power output are realized;
and the intermediate frequency amplification chip is connected with the output end of the phased array transceiving front end chip and used for amplifying and controlling gain of the intermediate frequency receiving signal input by the phased array transceiving front end chip, providing a sufficient dynamic range, tuning band-pass filtering and outputting the intermediate frequency receiving signal to a digital sampling unit (ADC).
The working principle of the SAR system disclosed by the invention is as follows: excitation signals generated by the phase-locked loop chip enter the phased array transceiving front-end chip, and are radiated by the phased array antenna after amplitude and phase modulation, so that the signals are transmitted; meanwhile, the phased array antenna receives echo signals, the echo signals are received by a phased array transceiving front end chip in a low noise mode and controlled by a radiation phase, mixed down to an intermediate frequency, and then output to a digital sampling unit (ADC) through an intermediate frequency amplification chip.
The phase-locked loop chip adopts CMOS technology for full integration, and the process is determined by the performance index required to be reached by the chip. The chip directly generates high-frequency broadband linear frequency modulation signals by using a phase-locked loop technology, and can realize that system transmission signals have the advantages of good spurious suppression characteristics and far-end low noise by using the low noise characteristics of a voltage-controlled oscillator and the narrow-band filtering characteristics of the phase-locked loop.
The phase-locked loop chip comprises a phase frequency detector 1, a loop filter 2, a voltage-controlled oscillator 3 and a frequency divider 4;
the phase frequency detector 1 is connected with an external crystal oscillator and inputs the external crystal oscillator as a reference signal of the phase frequency detector;
one end of the voltage-controlled oscillator 3 is connected with the phase frequency detector 1 through the loop filter 2, and the other end of the voltage-controlled oscillator is connected with the phase frequency detector 1 through the frequency divider 4;
one feedback signal output by the voltage-controlled oscillator 3 is compared with the reference signal in the phase frequency detector 1 after frequency division, and the generated phase detection error is filtered and adjusted by the loop filter 2 and then is used as a control signal of the voltage-controlled oscillator 3, so that a negative feedback system is formed to accurately control the frequency modulation continuous wave signal output of the voltage-controlled oscillator 3.
In the traditional method, a loop filter circuit is generally built by adopting lumped elements outside a chip, and a voltage-controlled oscillator chip is additionally used, so that larger volume and power consumption are occupied;
the phase-locked loop chip of the present disclosure adopts a full digital technology to integrate a loop filter and a voltage-controlled oscillator on a chip, wherein: the loop filter 2 is a digital loop filter and can be freely configured in a chip, so that the problem that the bandwidth of a traditional analog frequency modulation signal source cannot be adaptively adjusted is solved; the voltage-controlled oscillator 3 is a digital oscillation source based on variable inductance, and can effectively improve frequency control precision.
The traditional phase-locked loop can only generate dot frequency or frequency stepping signals, the DAC or DDS and the like are needed to be utilized for generating linear frequency modulation signals, the system complexity is high, the power consumption is large,
the frequency divider 4 is a fast modulation fractional frequency divider, and the phase-locked loop chip of the present disclosure realizes generation of a chirp signal by fast modulating the fractional frequency divider.
The phased array transceiver front-end chip (millimeter wave level) adopts a CMOS process, and the process is determined by performance indexes required to be reached by the chip. The chip is mainly used for receiving and transmitting radar signals, a plurality of receiving and transmitting channels are integrated on the chip, and amplitude and phase control can be independently realized in each channel, so that the chip is matched with a phased array antenna to form beam scanning capability.
The phased array transceiver front end chip includes: the device comprises a transmitting unit, a receiving unit and a power combining unit.
The transmitting unit includes: the drive amplifier 5, the coupler 6, the numerical control attenuator 7, the phase shifter 8 and the power amplifier 9 are used for completing the amplification and amplitude-phase control of the frequency modulation continuous wave signals and coupling a part of signals as a local oscillator of a receiving unit;
the receiving unit includes: the low-noise amplifier 10, the phase shifter, the numerical control attenuator and the mixer 11 are used for completing low-noise amplification and amplitude-phase control of signals received by the phased array antenna and performing down-conversion to intermediate frequency;
the power combining unit includes:
the transmitting power divider is used for carrying out multi-channel power distribution on the transmitting signals; and
and the receiving power combiner is used for carrying out multi-channel power combination on the received signals.
The phased array transceiving front end chip is different from the traditional transceiving chip in that: firstly, a plurality of transceiving channels with amplitude and phase control functions are integrated on a single chip, a beam scanning function required by a phased array radar is supported, and meanwhile, beam synthesis can be carried out in space to increase transmitting power and improve radar action distance; and secondly, the CMOS process is adopted for manufacturing, so that the cost advantage and the process maturity are higher, and the integrated integration with a back-end silicon-based chip is facilitated.
The fully integrated intermediate frequency amplification chip adopts a CMOS process, and the process is determined by the performance index required by the chip. The chip is mainly used for amplifying and filtering intermediate frequency signals received by the SAR and adjusting the dynamic range.
The fully integrated intermediate frequency amplification chip comprises:
a band-pass filter 12 that is bandwidth-tunable,
a multi-stage variable gain amplifier 13.
The left band of the band-pass filter with the tunable bandwidth mainly aims at the requirement of FMCW-SAR direct wave suppression, a high suppression degree is required at the low frequency of kHz, but a pass band needs to be formed after a hundred kHz level, so that an extremely high rectangular coefficient is required; meanwhile, the right side band position can be adjusted in the intermediate frequency passband range to adapt to different action distances of FMCW-SAR; on the one hand, the multi-stage variable gain amplifier needs to provide enough gain for the system, and in addition, the multi-stage variable gain amplifier is provided with an automatic gain control function so as to provide a larger dynamic range.
The fully integrated intermediate frequency amplification chip is different from the traditional intermediate frequency chip in that: firstly, the traditional band-pass filter is usually built only by lumped elements at low frequency, the size is large, the traditional band-pass filter has no tuning function, and the on-chip bandwidth tunable BPF can better adapt to the requirements of miniaturized FMCW-SAR; and secondly, in the traditional method, an adjustable amplification link is formed by adopting an intermediate frequency amplifier in a multi-stage DC-block form and a numerical control attenuator, the volume power consumption is high, the gain cannot be adjusted in real time according to the size of an input signal, the dynamic range adjustment is inflexible, and the problem can be effectively solved by integrating a multi-stage variable gain amplifier on a chip.
So far, the embodiments of the present disclosure have been described in detail with reference to the accompanying drawings. It is to be noted that, in the attached drawings or in the description, the implementation modes not shown or described are all the modes known by the ordinary skilled person in the field of technology, and are not described in detail. Further, the above definitions of the various elements and methods are not limited to the various specific structures, shapes or arrangements of parts mentioned in the examples, which may be easily modified or substituted by those of ordinary skill in the art.
From the above description, those skilled in the art should have clear recognition of the full silicon-based chip-based SAR system of the present disclosure.
In summary, the present disclosure provides an SAR system based on an all-silicon-based chip, which adopts an all-silicon-based integrated phase-locked loop chip technical scheme, and the scheme directly generates a high-frequency broadband chirp signal by using an all-digital phase-locked loop technology, thereby effectively solving the defects of complex system and high volume power consumption of the conventional DAC and other schemes, and realizing that a system transmission signal has the advantages of good spurious suppression characteristic and far-end low noise by using the low noise characteristic of a VCO and the narrow-band filtering characteristic of the phase-locked loop. The technical scheme of the full silicon-based integrated intermediate frequency amplification chip is adopted, a plurality of transceiving channels are integrated on the chip, and each channel can independently realize amplitude and phase control, so that the capacity of forming beam scanning by matching a phased array antenna is realized, the full silicon-based integrated intermediate frequency amplification chip is suitable for a wider application range, the size and the power consumption are relatively low, and higher transmitting power can be synthesized compared with the traditional single-transmitting single-receiving front-end chip. The technical scheme of the phased array transceiving front-end chip integrated on a silicon substrate is adopted, the bandwidth tunable BPF and the multi-stage variable gain amplifier are integrated on the chip, the scheme has the characteristics of small size and low power consumption, is suitable for integration of a miniaturized FMCW-SAR, can automatically tune the dynamic range, and is suitable for imaging observation of different distances and different targets. The FMCW-SAR technical scheme of adopting the full silicon-based integration, the front-end radio frequency part of the FMCW-SAR technical scheme is composed of a frequency modulation source, a transmitting and receiving front end and a middle-frequency amplification chip which all adopt CMOS technology, traditional compound process chips such as GaAs, GaN and the like are replaced, the digital chip integration which also adopts the CMOS technology with the back end is convenient, and the volume weight and the power consumption of the system can be effectively reduced; meanwhile, the silicon-based process has low cost and good process maturity and consistency, and is convenient for large-scale production in the later period.
It should also be noted that directional terms, such as "upper", "lower", "front", "rear", "left", "right", and the like, used in the embodiments are only directions referring to the drawings, and are not intended to limit the scope of the present disclosure. Throughout the drawings, like elements are represented by like or similar reference numerals. Conventional structures or constructions will be omitted when they may obscure the understanding of the present disclosure.
And the shapes and sizes of the respective components in the drawings do not reflect actual sizes and proportions, but merely illustrate the contents of the embodiments of the present disclosure. Furthermore, in the claims, any reference signs placed between parentheses shall not be construed as limiting the claim.
Unless otherwise indicated, the numerical parameters set forth in the specification and attached claims are approximations that can vary depending upon the desired properties sought to be obtained by the present disclosure. In particular, all numbers expressing quantities of ingredients, reaction conditions, and so forth used in the specification and claims are to be understood as being modified in all instances by the term "about". Generally, the expression is meant to encompass variations of ± 10% in some embodiments, 5% in some embodiments, 1% in some embodiments, 0.5% in some embodiments by the specified amount.
Furthermore, the word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements.
The use of ordinal numbers such as "first," "second," "third," etc., in the specification and claims to modify a corresponding element does not by itself connote any ordinal number of the element or any ordering of one element from another or the order of manufacture, and the use of the ordinal numbers is only used to distinguish one element having a certain name from another element having a same name.
In addition, unless steps are specifically described or must occur in sequence, the order of the steps is not limited to that listed above and may be changed or rearranged as desired by the desired design. The embodiments described above may be mixed and matched with each other or with other embodiments based on design and reliability considerations, i.e., technical features in different embodiments may be freely combined to form further embodiments.
Those skilled in the art will appreciate that the modules in the device in an embodiment may be adaptively changed and disposed in one or more devices different from the embodiment. The modules or units or components of the embodiments may be combined into one module or unit or component, and furthermore they may be divided into a plurality of sub-modules or sub-units or sub-components. All of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and all of the processes or elements of any method or apparatus so disclosed, may be combined in any combination, except combinations where at least some of such features and/or processes or elements are mutually exclusive. Each feature disclosed in this specification (including any accompanying claims, abstract and drawings) may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise. Also in the unit claims enumerating several means, several of these means may be embodied by one and the same item of hardware.
The above-mentioned embodiments are intended to illustrate the objects, aspects and advantages of the present disclosure in further detail, and it should be understood that the above-mentioned embodiments are only illustrative of the present disclosure and are not intended to limit the present disclosure, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present disclosure should be included in the scope of the present disclosure.
Claims (9)
1. An all-silicon-based chip-based SAR system, comprising:
the phase-locked loop chip is used for generating frequency-modulated continuous wave signals;
the input end of the phased array transceiving front-end chip is connected with the phase-locked loop chip and is used for carrying out multichannel amplitude-phase modulation on the input frequency modulation continuous wave signal and then outputting the frequency modulation continuous wave signal to a phased array antenna for transmitting, receiving the phased array antenna signal at the same time, completing multichannel amplitude-phase modulation, and carrying out down-conversion after combining to obtain an intermediate-frequency signal;
and the intermediate frequency amplification chip is connected with the phased array transceiving front end chip and is used for amplifying and controlling the gain of the input intermediate frequency signal, providing a sufficient dynamic range, tuning band-pass filtering and outputting the intermediate frequency signal to the digital sampling unit.
2. The all-silicon-based chip SAR system of claim 1, the phase locked loop chip, comprising:
the phase frequency detector is connected with an external crystal oscillator and inputs the external crystal oscillator as a reference signal of the phase frequency detector;
one end of the voltage-controlled oscillator is connected with the phase frequency detector through a loop filter, and the other end of the voltage-controlled oscillator is connected with the phase frequency detector through a frequency divider;
the frequency division of a feedback signal output by the voltage-controlled oscillator is compared with the reference signal in the phase frequency detector, and the generated phase detection error is filtered and adjusted by the loop filter and then is used as a control signal of the voltage-controlled oscillator, so that a negative feedback system is formed to control the output of the frequency-modulated continuous wave signal of the voltage-controlled oscillator.
3. The all-silicon-based chip SAR-based system of claim 3, wherein the frequency divider is a fast modulation fractional frequency divider, and the phase-locked loop chip implements generation of a chirp continuous wave signal by fast modulation fractional frequency divider.
4. The full silicon-based chip based SAR system of claim 1, the phased array transceiver front end chip comprising: the device comprises a plurality of paths of transmitting units and receiving units connected with a phased array antenna, and a power synthesis unit;
wherein the power combining unit includes:
the transmitting power divider is used for distributing the frequency modulation continuous wave signals to the multi-path transmitting units for processing and then inputting the processed signals into the phased array antenna; and
and the receiving combiner is used for combining the phased array antenna receiving signals processed by the multipath receiving units.
5. The full silicon-based chip SAR system of claim 4, each of said transmitting units comprises: the drive amplifier, the coupler, the numerical control attenuator, the phase shifter and the power amplifier are connected in sequence; the method for distributing the frequency-modulated continuous wave signals to the multiple transmitting units for processing comprises the following steps: and completing the amplification and amplitude-phase control of the frequency modulation continuous wave signals, and coupling a part of signals as a local oscillator of the receiving unit.
6. The full silicon-based chip-based SAR system of claim 4, each of said receiving units comprising: the low noise amplifier, the phase shifter, the numerical control attenuator and the frequency mixer are connected in sequence; and the processing by the multipath receiving unit comprises the steps of finishing low-noise amplification and amplitude-phase control of the phased array antenna receiving signal and carrying out down-conversion to intermediate frequency.
7. The SAR system based on full silicon-based chip of claim 1, wherein the intermediate frequency amplification chip comprises a bandwidth tunable band-pass filter and a multi-stage variable gain amplifier which are connected in sequence;
the left band of the band-pass filter with the tunable bandwidth mainly aims at the direct wave suppression requirement of an SAR system, a higher suppression degree is required at the low frequency of kHz, and a pass band is required to be formed after the level of hundred kHz; meanwhile, the right side band position can be adjusted in the intermediate frequency passband range to adapt to different acting distances of the SAR system.
8. The all-silicon-based chip SAR system of claim 7, wherein the multi-stage variable gain amplifier provides sufficient gain for the SAR system and further has an automatic gain control function to provide a larger dynamic range.
9. The SAR system based on full silicon-based chip of claim 7, wherein the phase-locked loop chip, the phased array transceiver front end chip, and the intermediate frequency amplification chip are all fully integrated by CMOS technology.
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