CN112366259A - Light emitting diode epitaxial wafer and preparation method thereof - Google Patents

Light emitting diode epitaxial wafer and preparation method thereof Download PDF

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Publication number
CN112366259A
CN112366259A CN202011061541.7A CN202011061541A CN112366259A CN 112366259 A CN112366259 A CN 112366259A CN 202011061541 A CN202011061541 A CN 202011061541A CN 112366259 A CN112366259 A CN 112366259A
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sublayer
ingan
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CN112366259B (en
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姚振
从颖
董彬忠
李鹏
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HC Semitek Zhejiang Co Ltd
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HC Semitek Zhejiang Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H01L33/06—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds

Abstract

The disclosure provides a light emitting diode epitaxial wafer and a preparation method thereof, and belongs to the technical field of light emitting diodes. In the barrier layer of the multiple quantum well layer, the first InGaN sub-layer can realize good transition with the InGaN well layer, the growth foundation of the barrier layer on the InGaN well layer is guaranteed, the first InN sub-layer serves as a transition layer, good transition and growth from the first InGaN sub-layer to the SiN sub-layer are realized, and the crystal quality of the SiN sub-layer is improved. The SiN sub-layer can play a role in blocking dislocation extension, dislocation extension is avoided, and crystal quality of an epitaxial structure grown on the SiN sub-layer is further improved. And the finally grown non-doped GaN sub-layer plays a role of a conventional GaN barrier layer, and the multiple quantum well layer can normally emit light. The crystal quality of the multi-quantum well layer can be greatly improved, and the luminous efficiency of the finally obtained light-emitting diode is also improved.

Description

Light emitting diode epitaxial wafer and preparation method thereof
Technical Field
The disclosure relates to the technical field of light emitting diodes, and particularly relates to a light emitting diode epitaxial wafer and a preparation method thereof.
Background
The light emitting diode is a light emitting device with wide application, and is commonly used for communication signal lamps, automobile interior and exterior lamps, urban illumination, landscape illumination and the like, and the light emitting diode epitaxial wafer is a basic structure for preparing the light emitting diode. The light emitting diode epitaxial wafer generally includes a substrate, and an n-type GaN layer, a multiple quantum well layer, and a p-type GaN layer sequentially stacked on the substrate.
In the related art, the multiple quantum well layer generally includes InGaN well layers and GaN barrier layers alternately stacked. However, larger lattice mismatch and piezoelectric polarization effect exist between the InGaN well layer and the GaN barrier layer originally, so that more defects and leakage channels exist in the multiple quantum well layer, and the light emitting efficiency of the finally obtained light emitting diode epitaxial wafer is lower.
Disclosure of Invention
The embodiment of the disclosure provides a light emitting diode epitaxial wafer and a preparation method thereof, which can improve the crystal quality of a multi-quantum well layer so as to improve the light emitting efficiency of a finally obtained light emitting diode. The technical scheme is as follows:
the disclosed embodiment provides an LED epitaxial wafer, which comprises a substrate, and an n-type GaN layer, a multi-quantum well layer and a p-type GaN layer which are sequentially laminated on the substrate, wherein the multi-quantum well layer further comprises InGaN well layers and barrier layers which are alternately laminated,
the barrier layer comprises a first InGaN sub-layer, a first InN sub-layer, a SiN sub-layer and a non-doped GaN sub-layer which are sequentially stacked.
Optionally, the thickness of the first InGaN sublayer is 0.4-1.2 nm, the thickness of the first InN sublayer is 0.8-1.5 nm, the thickness of the SiN sublayer is 1-1.5 nm, and the thickness of the undoped GaN sublayer is 2-3.5 nm.
Optionally, the barrier layer further comprises a first GaN sublayer doped with In and a second GaN sublayer doped with Si, which are sequentially stacked on the undoped GaN sublayer, wherein the doping concentration of In the first GaN sublayer is 1-6E 2C/S, and the doping concentration of Si In the second GaN sublayer is 2E 17-6E 17/cm3。
Optionally, the ratio of the content of Si in the second GaN sublayer to the composition of Ga is 0.0003-0.001.
Optionally, the thickness of the first GaN sublayer is 0.3-1 nm, and the thickness of the second GaN sublayer is 1-2.5 nm.
Optionally, the barrier layer further includes a second InN sublayer and a second InGaN sublayer doped with Si, which are sequentially stacked on the second GaN sublayer.
Optionally, the doping concentration of Si in the second InN sublayer is 1E 17-4E 17.
Optionally, the thickness of the second InN sublayer is 1-2.3 nm, and the thickness of the second InGaN sublayer is 0.5-1 nm.
The embodiment of the disclosure provides a preparation method of a light-emitting diode epitaxial wafer, which comprises the following steps:
providing a substrate;
growing an n-type GaN layer on the substrate;
growing a multi-quantum well layer on the n-type GaN layer, wherein the multi-quantum well layer further comprises an InGaN well layer and a barrier layer which are alternately laminated, and the barrier layer comprises a first InGaN sub-layer, a first InN sub-layer, an SiN sub-layer and a non-doped GaN sub-layer which are sequentially laminated;
and growing a p-type GaN layer on the multi-quantum well layer.
Optionally, the barrier layer further includes a first GaN sublayer doped with In and a second GaN sublayer doped with Si, which are sequentially stacked on the undoped GaN sublayer, and the growing of the first GaN sublayer includes:
introducing an In source, a Ga source and an N source into the reaction cavity, and growing a GaN film at a growth rate of 0.02-0.05 nm/s;
and closing the In source, continuously introducing the Ga source and the N source, and growing the GaN film at the growth rate of 0.03-0.06 nm/s until the first GaN sublayer is obtained.
The beneficial effects brought by the technical scheme provided by the embodiment of the disclosure include:
the multiple quantum well layer comprises an InGaN well layer and a barrier layer which are alternately stacked, and the barrier layer is arranged to comprise a first InGaN sub-layer, a first InN sub-layer, an SiN sub-layer and a non-doped GaN sub-layer which are sequentially stacked. The first InGaN sublayer can realize good transition with the InGaN well layer, the growth foundation of the barrier layer on the InGaN well layer is guaranteed, the first InN sublayer with the lattice constant close to that of the first InGaN sublayer and the first SiN sublayer can serve as a transition layer, good transition and growth from the first InGaN sublayer to the SiN sublayer are achieved, and the crystal quality of the SiN sublayer is improved. The SiN sub layer can play a role in blocking dislocation extension, dislocation extension is avoided, and crystal quality of an epitaxial structure grown on the SiN sub layer is further improved. And the finally grown non-doped GaN sub-layer plays a role of a conventional GaN barrier layer, and the multiple quantum well layer can normally emit light. The crystal quality of the multi-quantum well layer can be greatly improved, and the luminous efficiency of the finally obtained light-emitting diode is also improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and it is obvious for those skilled in the art to obtain other drawings based on the drawings without creative efforts.
Fig. 1 is a schematic structural diagram of an led epitaxial wafer according to an embodiment of the present disclosure;
fig. 2 is a schematic structural diagram of another light emitting diode epitaxial wafer according to an embodiment of the present disclosure;
fig. 3 is a flowchart of a method for manufacturing an epitaxial wafer of a light emitting diode according to an embodiment of the present disclosure;
fig. 4 is a flowchart of another method for manufacturing an epitaxial wafer of a light emitting diode according to an embodiment of the present disclosure.
Detailed Description
To make the objects, technical solutions and advantages of the present disclosure more apparent, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.
Fig. 1 is a schematic structural diagram of an led epitaxial wafer according to an embodiment of the present disclosure, and as can be seen from fig. 1, an led epitaxial wafer according to an embodiment of the present disclosure includes a substrate 1, and an n-type GaN layer 2, a multi-quantum well layer 3, and a p-type GaN layer 4 sequentially stacked on the substrate 1, where the multi-quantum well layer 3 further includes an InGaN well layer 31 and a barrier layer 32 that are alternately stacked.
The barrier layer 32 includes a first InGaN sublayer, a first InN sublayer, a SiN sublayer, and a non-doped GaN sublayer stacked in sequence.
The multiple quantum well layer 3 includes InGaN well layers 31 and barrier layers 32 alternately stacked, and the barrier layer 32 is configured to include a first InGaN sublayer 321, a first InN sublayer 322, an SiN sublayer 323, and a non-doped GaN sublayer 324 sequentially stacked. The first InGaN sublayer 321 can realize good transition with the InGaN well layer 31, ensure the growth foundation of the barrier layer 32 on the InGaN well layer 31, and the first InN sublayer 322 with a lattice constant closer to that of both the first InGaN sublayer 321 and the SiN sublayer 323 can be used as a transition layer, so as to realize good transition and growth from the first InGaN sublayer 321 to the SiN sublayer 323, and improve the crystal quality of the SiN sublayer 323. The SiN sublayer 323 can play a role in blocking dislocation extension, so that dislocation extension is avoided, and the crystal quality of an epitaxial structure grown on the SiN sublayer 323 is further improved. The finally grown undoped GaN sublayer 324 plays a role of the conventional GaN barrier layer 32, and ensures that the multiple quantum well layer 3 can normally emit light. The crystal quality of the multiple quantum well layer 3 can be greatly improved, and the luminous efficiency of the finally obtained light-emitting diode is also improved.
Optionally, the thickness of the first InGaN sublayer 321 may be 0.4 to 1.2nm, the thickness of the first InN sublayer 322 may be 0.8 to 1.5nm, the thickness of the SiN sublayer 323 may be 1 to 1.5nm, and the thickness of the undoped GaN sublayer 324 may be 2 to 3.5 nm.
When the thickness of each layer is within the range, the multiple quantum well layer 3 with better quality can be obtained, and the luminous efficiency of the final light-emitting diode is ensured.
Referring to fig. 1, the barrier layer 32 may further include a first GaN sublayer 325 doped with In and a second GaN sublayer 326 doped with Si, which are sequentially stacked on the undoped GaN sublayer 324, wherein the doping concentration of In the first GaN sublayer 325 is 1-6E 2C/S, and the doping concentration of Si In the second GaN sublayer 326 is 2E 17-6E 17/cm3。
The barrier layer 32 further comprises a first GaN sublayer 325 doped with In and a second GaN sublayer 326 doped with Si, which are sequentially stacked, the first GaN sublayer 325 doped with In can be well matched with the InGaN well layer 31, and the doping concentration of In the first GaN sublayer 325 is 1-6E 2C ^ or greaterS can also reduce the occurrence of doped In penetrating into the second GaN sublayer 326 while achieving good transition, ensuring the crystal quality of the second GaN sublayer 326. The doping concentration of Si in the second GaN sublayer 326 is 2E 17-6E 17/cm3The second GaN sublayer 326 can provide electrons flowing into the InGaN well layer 31, form band bending in the InGaN well layer 31, and the direction of the band bending in the InGaN well layer 31 is opposite to the bending direction of the polarization field, so that the separation degree of the wave functions of holes and electrons caused by the band bending caused by the polarization field can be reduced, and the recombination probability of the electrons and the holes can be improved to improve the light emitting efficiency of the light emitting diode. And the second GaN sublayer 326 doped with Si can also reduce the high resistance structure brought by the first InGaN sublayer 321 and the first InN sublayer 322, so as to ensure that electrons can flow normally.
Illustratively, the ratio of the Si content to the Ga composition in the second GaN sub-layer 326 is 0.0003 to 0.001. In this case, a well-qualified mqw layer 3 structure can be obtained.
Optionally, the thickness of the first GaN sub-layer 325 is 0.3-1 nm, and the thickness of the second GaN sub-layer 326 is 1-2.5 nm.
The thickness of the first GaN sublayer 325 and the thickness of the second GaN sublayer 326 are within the above ranges, so that the first GaN sublayer 325 and the second GaN sublayer 326 can effectively block electrons, and the effective offset part of the band bending generated between the second GaN sublayer 326 and the InGaN well layer 31 and the band bending generated by the GaN material and the InGaN well layer 31 per se can be ensured, and the crystal quality of the multiple quantum well layer 3 of the light emitting diode is finally improved.
Referring to fig. 1, barrier layer 32 may further include a second InN sublayer 327 doped with Si and a second InGaN sublayer 328 sequentially stacked on second GaN sublayer 326.
The Si-doped second InN sublayer 327 stacked on the second GaN sublayer 326 may function to lower the barrier, so that electrons may be more easily transferred into the InGaN well layer 31, and reduce the resistance of the second InN sublayer 327 itself, so as to facilitate the electrons to move to the InGaN well layer 31 for recombination light emission. The second InGaN sublayer 328 can be matched with the second InN sublayer 327 and well transited to the InGaN well layer 31, and the quality of both the InGaN well layer 31 and the barrier layer 32 in the multiple quantum well layer 3 can be effectively improved.
Optionally, the doping concentration of Si in the second InN sublayer 327 is 1E 17-4E 17.
The doping concentration of Si in the second InN sublayer 327 is in the above range, which can ensure good flow of electrons, and Si is not easily diffused into other layers.
Illustratively, the thickness of the second InN sublayer 327 may be 1-2.3 nm, and the thickness of the second InGaN sublayer 328 may be 0.5-1 nm.
The thickness of the second InN sublayer 327 In the above range can be effectively transited and can accumulate some electrons, so that the number of electrons that can enter the InGaN well layer 31 at the same time is increased, the light emitting efficiency is increased, the thickness of the second InGaN sublayer 328 In the above range can ensure stable transition with the InGaN well layer 31, and excessive diffusion of In element is avoided.
Fig. 2 is a schematic structural diagram of another light emitting diode epitaxial wafer according to an embodiment of the present disclosure, and as can be seen from fig. 2, in another implementation manner provided by the present disclosure, the light emitting diode epitaxial wafer may include a substrate 1, and a buffer layer 5, an undoped GaN layer 6, an n-type GaN layer 2, a multi-quantum well layer 3, an AlGaN electron blocking layer 7, a p-type GaN layer 4, and a p-type contact layer 8 grown on the substrate 1.
Note that the mqw layer 3 shown in fig. 2 has the same structure as the mqw layer 3 shown in fig. 1, and the description thereof is omitted.
Alternatively, the substrate 1 may be a sapphire substrate 1. Easy to manufacture and obtain.
Illustratively, the buffer layer 5 may be an AlN buffer layer 5. The crystal quality of the epitaxial thin film grown on the low-temperature buffer layer 5 can be ensured.
Alternatively, the buffer layer 5 may have a thickness of 10 to 30 nm. The lattice mismatch between the n-type GaN layer 2 and the substrate 1 can be reduced, and the crystal quality of the epitaxial layer is ensured.
Illustratively, the thickness of the undoped GaN layer 6 may be 1 to 3.5 μm. The quality of the obtained light emitting diode epitaxial wafer is good.
In one implementation provided by the present disclosure, the thickness of the undoped GaN layer 6 may also be 1 μm. The present disclosure is not so limited.
Alternatively, the doping element of the n-type GaN layer 2 may be Si, and the doping concentration of the Si element may be 1 × 1018～1×1019cm-3. The overall quality of the n-type GaN layer 2 is good.
Illustratively, the thickness of the n-type GaN layer 2 may be 2 to 3 μm. The obtained n-type GaN layer 2 has good overall quality.
In one implementation provided by the present disclosure, the thickness of the n-type GaN layer 2 may be 2 μm. The present disclosure is not so limited.
Optionally, the Al content of the AlGaN electron blocking layer 7 may be 0.15 to 0.25. The effect of blocking electrons is better.
Alternatively, the p-type GaN layer 4 may be doped with Mg, and the thickness of the p-type GaN layer 4 may be the same as that of the structure shown in fig. 1, which is not described herein again.
Illustratively, the thickness of the p-type contact layer 8 may be 15 nm.
It should be noted that, in the epitaxial wafer structure shown in fig. 2, compared with the epitaxial wafer structure shown in fig. 1, a buffer layer 5 and a non-doped GaN layer 6 for relieving lattice mismatch are added between the buffer layer 5 and the n-type GaN layer 2, and a p-type contact layer 8 is also grown on the p-type GaN layer 4. The obtained epitaxial wafer has better quality and luminous efficiency.
Fig. 3 is a flowchart of a method for manufacturing an led epitaxial wafer according to an embodiment of the present disclosure, and as shown in fig. 3, the method for manufacturing an led epitaxial wafer includes:
s101: a substrate is provided.
S102: an n-type GaN layer is grown on the substrate.
S103: and growing a multi-quantum well layer on the n-type GaN layer, wherein the multi-quantum well layer comprises InGaN well layers and barrier layers which are alternately laminated, and the barrier layers comprise a first InGaN sub-layer, a first InN sub-layer, an SiN sub-layer and a non-doped GaN sub-layer which are sequentially laminated.
S104: and growing a p-type GaN layer on the multi-quantum well layer.
The technical effect of the method for manufacturing the light emitting diode epitaxial wafer shown in fig. 3 can refer to the technical effect corresponding to the light emitting diode epitaxial wafer shown in fig. 1, and therefore, the technical effect of the manufacturing method is not described herein again.
Optionally, in the step S103, when the mqw layer is grown, the pressure of the reaction chamber may be 100 to 300 torr. The multiple quantum well layer can be stably grown.
Illustratively, the growth temperature of the InGaN well layer in the multi-quantum well layer may be 760 to 780 ℃. The growth temperature of the barrier layer in the multi-quantum well layer can be 860-890 ℃.
A more compact barrier layer with better quality can be obtained.
Illustratively, when the first InGaN sublayer is grown, an In source of 50-150 sccm may be introduced into the reaction chamber.
The flow of the introduced In source is 50-150 sccm when the first InGaN sublayer grows, so that the obtained In element doped In the first InGaN sublayer can be ensured to be reasonable, and good matching with the InGaN well layer can be realized.
In another implementation manner provided by the present disclosure, an In source of 50-100 sccm may also be introduced into the reaction chamber when the first InGaN sublayer is grown. The crystal quality of the resulting first InGaN sublayer may be further improved.
Illustratively, when the first InGaN sublayer is grown, 50-150 sccm of In source is introduced into the reaction chamber for 5-30 s.
The doping amount of the obtained first InGaN sublayer In is reasonable, the situation that In is diffused into the first InN sublayer due to overlong growth time is avoided, and the crystal quality of the first InGaN sublayer can be improved.
In another implementation manner provided by the present disclosure, when the first InGaN sublayer is grown, an In source of 50-150 sccm is introduced into the reaction chamber, and the duration is 10-30 s. The crystal quality of the resulting first InGaN sublayer may be further improved.
Illustratively, the growth time of the first InN sublayer can be 5-25 s.
The situation that In diffuses into other layers due to the fact that the growth time is too long is avoided, and the overall crystal quality of the barrier layer can be improved.
In another implementation manner provided by the present disclosure, the growth time of the first InN sublayer may also be 5-20 s. The crystal quality of the resulting first InN sublayer can be further improved.
For example, when growing the SiN sub-layer, a Si source of 0.2-1 sccm may be introduced into the reaction chamber, and an In source of 10-40 sccm may be introduced into the reaction chamber. A SiN sublayer of better quality can be obtained.
In another implementation manner provided by the present disclosure, when the SiN sub-layer is grown, a Si source of 0.3 to 1sccm may be introduced into the reaction chamber, and an In source of 15 to 40sccm may be introduced into the reaction chamber. The crystal quality of the resulting SiN sub-layer may be further improved.
Illustratively, the growth time of the SiN sub-layer may be 10-40 s.
The SiN sub-layer Si obtained at the moment can not cause the situation that In diffuses into other layers due to overlong growth time, and the overall crystal quality of the barrier layer can be improved.
In another implementation manner provided by the present disclosure, the growth time of the SiN sub-layer can also be 15-40 s. The crystal quality of the resulting SiN sub-layer may be further improved.
For example, when the undoped GaN sublayer grows, a Ga source of 600-1000 sccm and an N source of 50-100 sccm can be introduced into the reaction cavity. The undoped GaN sublayer with more uniform growth can be obtained.
Optionally, the growth time of the non-doped GaN sublayer is 1-3 min. The obtained non-doped GaN sublayer has reasonable quality and thickness, and does not generate strong polarization reaction due to overlarge thickness.
In another implementation manner provided by the present disclosure, the growth time of the undoped GaN sublayer can also be 1.5-3 min. The crystal quality of the resulting undoped GaN sublayer can be further improved.
Illustratively, the barrier layer may further include a first In-doped GaN sublayer and a second Si-doped GaN sublayer stacked In sequence on the undoped GaN sublayer, the growing of the first GaN sublayer including:
introducing an In source, a Ga source and an N source into the reaction cavity, and growing a GaN film at a growth rate of 0.02-0.05 nm/s; and closing the In source, continuously introducing the Ga source and the N source, and growing the GaN film at the growth rate of 0.05-1.2 nm/s until a first GaN sublayer is obtained.
By adopting the mode, the part doped with In the first GaN sublayer can be ensured to grow stably, the diffusion of In is reduced, and then the rapid growth and filling are carried out, so that the overall quality of the first GaN sublayer can be ensured.
Optionally, an In source of 10-40 sccm, a Ga source of 600-900 sccm, and an N source of 50-80 sccm may be introduced into the reaction chamber. And obtaining the GaN film with better quality.
In another implementation manner provided by the present disclosure, an In source of 10-30 sccm, a Ga source of 600-800 sccm, and an N source of 50-70 sccm may be introduced into the reaction chamber. The crystal quality of the obtained GaN thin film can be further improved.
Optionally, the growth time of the GaN thin film can be 1-2 min. At this time, the content of In doped In the first GaN sublayer is reasonable, and the situation that the quality of the first GaN sublayer is affected due to the excessive content of In the first GaN sublayer can be avoided.
In another implementation manner provided by the present disclosure, the growth time of the GaN thin film may be 1.5-2 min. The crystal quality of the obtained GaN thin film can be further improved.
Exemplarily, on the basis of the GaN thin film, a Ga source of 600-750 sccm and an N source of 60-75 sccm are added into the reaction chamber. Until the first GaN sublayer with better quality is grown.
Optionally, when the second GaN sublayer grows, a Si source of 0.1-0.6 sccm, a Ga source of 600-700 sccm and an N source of 50-70 sccm can be introduced into the reaction chamber.
The obtained Si source in the second GaN sublayer can provide an effective electronic channel, reduce the problem of high resistance caused by the first InGaN sublayer and the first InN sublayer, and effectively control the band gap.
In another implementation manner provided by the present disclosure, 0.1 to 0.5sccm of Si source, 600to 700sccm of Ga source, and 50 to 65sccm of N source may be introduced into the reaction chamber. The crystal quality of the resulting second GaN sublayer can be further improved.
Illustratively, when the second InN sublayer is grown, the flow rate of Si introduced into the reaction chamber may be 0.1 to 0.4 sccm.
The small amount of Si doped in the second InN sublayer can counteract the negative effect of high resistance brought by the second InN sublayer, and electrons can be guaranteed to stably flow through the second InN sublayer.
In another implementation manner provided by the present disclosure, when the second InN sublayer is grown, the flow rate of Si that can be introduced into the reaction chamber may be 0.1 to 0.3 sccm. The crystal quality of the resulting second InN sublayer can be further improved.
For example, the flow rates of the In source, the Ga source and the N source introduced into the second InGaN sublayer can be 10-30 sccm, 500-800 sccm and 50-60 sccm, respectively. And the growth time of the second InGaN sublayer can be 5-15 s.
The second InGaN sublayer with reasonable quality and thickness can be obtained, and the crystal quality of the finally obtained second InGaN sublayer is guaranteed.
In another implementation manner provided by the present disclosure, the flow rates of the In source, the Ga source, and the N source introduced into the second InGaN sublayer may be 10 to 25sccm, 500to 650sccm, and 50 to 60sccm, respectively. And the growth time of the second InGaN sublayer can be 5-10 s. The crystal quality of the resulting second InN sublayer can be further improved.
Fig. 1 is a view of an epitaxial wafer structure of the light emitting diode after step S104 is performed.
Fig. 4 is a flowchart of another method for manufacturing an led epitaxial wafer according to an embodiment of the present disclosure, and as shown in fig. 4, the method for manufacturing an led epitaxial wafer includes:
s201: a substrate is provided.
Wherein the substrate may be a sapphire substrate. Easy to realize and manufacture.
Optionally, step S201 may further include: and treating the surface of the substrate for growing the epitaxial layer for 5-6 min in a hydrogen atmosphere.
For example, when the substrate is processed for growing the surface of the epitaxial layer, the temperature of the reaction chamber may be 1000-1100 ℃, and the pressure of the reaction chamber may be 200-500 torr.
S202: a buffer layer is grown on a substrate.
The buffer layer may be an AlN buffer layer. The AlN layer may be obtained by magnetron sputtering.
Illustratively, the deposition temperature of the AlN layer may be 400 to 800 ℃, the sputtering power may be 3000 to 5000W, and the pressure may be 2 to 20 mtorr. The obtained AlN layer has good quality.
S203: and growing an undoped GaN layer on the buffer layer.
The thickness of the non-doped GaN layer can be 0.5-3 um.
Illustratively, the growth temperature of the non-doped GaN layer can be 1000-1100 ℃, and the growth pressure is controlled at 100-300 torr. The obtained undoped GaN layer has better quality.
S204: and growing an n-type GaN layer on the undoped GaN layer.
Alternatively, the n-type GaN layer can be an n-type GaN layer, the growth temperature of the n-type GaN layer can be 1000-1100 ℃, and the growth pressure of the n-type GaN layer can be 100-300 Torr.
Optionally, the thickness of the n-type GaN layer can be 0.5-3 um.
S205: and growing a multi-quantum well layer on the n-type GaN layer.
The growth conditions, growth method, and structure of the multiple quantum well layer in step S205 are the same as those of the multiple quantum well layer in step S103 in fig. 3. And will not be described in detail herein.
S206: and growing an AlGaN electronic barrier layer on the multi-quantum well layer.
The growth temperature of the AlGaN electron blocking layer can be 800-1000 ℃, and the growth pressure of the AlGaN electron blocking layer can be 100-300 Torr. The AlGaN electron blocking layer grown under the condition has good quality, and is beneficial to improving the luminous efficiency of the light-emitting diode.
S207: and growing a p-type GaN layer on the AlGaN electron blocking layer.
Alternatively, the growth pressure of the p-type GaN layer may be 200 to 600Torr, and the growth temperature of the p-type GaN layer may be 800 to 1000 ℃.
S208: and growing a p-type contact layer on the p-type GaN layer.
Alternatively, the growth pressure of the p-type contact layer may be 100 to 300Torr, and the growth temperature of the p-type contact layer may be 800 to 1000 ℃.
The method for manufacturing the light emitting diode epitaxial wafer shown in fig. 4 provides a more detailed method for growing the light emitting diode epitaxial wafer compared to the method for manufacturing the light emitting diode shown in fig. 3.
The structure of the led epitaxial wafer after step S208 is completed can be seen in fig. 2.
It should be noted that, in the embodiments of the present disclosure, a VeecoK465iorC4 orrbmcvd (metalorganic chemical vapor deposition) apparatus is used to implement the growth method of the light emitting diode. By using high-purity H2(Hydrogen) or high purity N2(Nitrogen) or high purity H2And high purity N2The mixed gas of (2) is used as a carrier gas, high-purity NH3As an N source, trimethyl gallium (TMGa) and triethyl gallium (TEGa) as gallium sources, trimethyl indium (TMIn) as indium sources, silane (SiH4) as an N-type dopant, trimethyl aluminum (TMAl) as an aluminum source, and magnesium dicylocene (CP)2Mg) as a P-type dopant.
The above description is only exemplary of the present disclosure and is not intended to limit the present disclosure, so that any modification, equivalent replacement, or improvement made within the spirit and principle of the present disclosure should be included in the scope of the present disclosure.

Claims (10)

1. The light emitting diode epitaxial wafer is characterized by comprising a substrate, an n-type GaN layer, a multi-quantum well layer and a p-type GaN layer which are sequentially laminated on the substrate, wherein the multi-quantum well layer further comprises an InGaN well layer and a barrier layer which are alternately laminated,
the barrier layer comprises a first InGaN sub-layer, a first InN sub-layer, a SiN sub-layer and a non-doped GaN sub-layer which are sequentially stacked.
2. The light emitting diode epitaxial wafer of claim 1, wherein the first InGaN sub-layer has a thickness of 0.4-1.2 nm, the first InN sub-layer has a thickness of 0.8-1.5 nm, the SiN sub-layer has a thickness of 1-1.5 nm, and the undoped GaN sub-layer has a thickness of 2-3.5 nm.
3. The light-emitting diode epitaxial wafer as claimed In claim 1 or 2, wherein the barrier layer further comprises a first GaN sub-layer doped with In and a second GaN sub-layer doped with Si, which are sequentially stacked on the undoped GaN sub-layer, the doping concentration of In the first GaN sub-layer is 1-6E 2C/S, and the doping concentration of Si In the second GaN sub-layer is 2E 17-6E 17/cm3。
4. The light-emitting diode epitaxial wafer according to claim 3, wherein the ratio of the content of Si in the second GaN sub-layer to the composition of Ga is 0.0003-0.001.
5. The light-emitting diode epitaxial wafer according to claim 4, wherein the thickness of the first GaN sub-layer is 0.3-1 nm, and the thickness of the second GaN sub-layer is 1-2.5 nm.
6. The light emitting diode epitaxial wafer of claim 3, wherein the barrier layer further comprises a Si-doped second InN sublayer and a second InGaN sublayer sequentially stacked on the second GaN sublayer.
7. The light-emitting diode epitaxial wafer as claimed in claim 6, wherein the doping concentration of Si in the second InN sub-layer is 1E 17-4E 17.
8. The light emitting diode epitaxial wafer of claim 6, wherein the thickness of the second InN sub-layer is 1-2.3 nm, and the thickness of the second InGaN sub-layer is 0.5-1 nm.
9. A preparation method of a light emitting diode epitaxial wafer is characterized by comprising the following steps:
providing a substrate;
growing an n-type GaN layer on the substrate;
growing a multi-quantum well layer on the n-type GaN layer, wherein the multi-quantum well layer further comprises an InGaN well layer and a barrier layer which are alternately laminated, and the barrier layer comprises a first InGaN sub-layer, a first InN sub-layer, an SiN sub-layer and a non-doped GaN sub-layer which are sequentially laminated;
and growing a p-type GaN layer on the multi-quantum well layer.
10. The method for preparing the light-emitting diode epitaxial wafer according to claim 9, wherein the barrier layer further comprises a first In-doped GaN sub-layer and a second Si-doped GaN sub-layer which are sequentially stacked on the undoped GaN sub-layer, and the growing of the first GaN sub-layer comprises:
introducing an In source, a Ga source and an N source into the reaction cavity, and growing a GaN film at a growth rate of 0.02-0.05 nm/s;
and closing the In source, continuously introducing the Ga source and the N source, and growing the GaN film at the growth rate of 0.03-0.06 nm/s until the first GaN sublayer is obtained.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114447170A (en) * 2021-12-21 2022-05-06 华灿光电(苏州）有限公司 Light emitting diode epitaxial wafer capable of improving light emitting uniformity and preparation method thereof

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104409586A (en) * 2014-11-13 2015-03-11 湘能华磊光电股份有限公司 GaN-based III-V compound semiconductor LED (light emitting diode) epitaxial wafer and production method thereof
CN104835887A (en) * 2015-03-30 2015-08-12 华灿光电(苏州）有限公司 Light emitting diode epitaxial wafer and growth method thereof
CN107293619A (en) * 2017-06-30 2017-10-24 华灿光电（浙江）有限公司 A kind of LED epitaxial slice and its manufacture method
CN109449264A (en) * 2018-09-12 2019-03-08 华灿光电(苏州）有限公司 A kind of LED epitaxial slice and its manufacturing method

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104409586A (en) * 2014-11-13 2015-03-11 湘能华磊光电股份有限公司 GaN-based III-V compound semiconductor LED (light emitting diode) epitaxial wafer and production method thereof
CN104835887A (en) * 2015-03-30 2015-08-12 华灿光电(苏州）有限公司 Light emitting diode epitaxial wafer and growth method thereof
CN107293619A (en) * 2017-06-30 2017-10-24 华灿光电（浙江）有限公司 A kind of LED epitaxial slice and its manufacture method
CN109449264A (en) * 2018-09-12 2019-03-08 华灿光电(苏州）有限公司 A kind of LED epitaxial slice and its manufacturing method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114447170A (en) * 2021-12-21 2022-05-06 华灿光电(苏州）有限公司 Light emitting diode epitaxial wafer capable of improving light emitting uniformity and preparation method thereof
CN114447170B (en) * 2021-12-21 2023-09-19 华灿光电(苏州）有限公司 LED epitaxial wafer for improving light emitting uniformity and preparation method thereof

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