CN112366244B - 鳍式光伏型硅基等离激元热载流子红外探测芯片及其制作方法 - Google Patents
鳍式光伏型硅基等离激元热载流子红外探测芯片及其制作方法 Download PDFInfo
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Abstract
本发明属于光电探测技术领域,具体一种鳍式光伏型硅基等离激元热载流子红外探测芯片及其制作方法。本发明红外探测芯片包括SOI衬底、制作于SOI衬底顶层硅之内的像元阵列、制作于SOI衬底的底层硅中的信号读出电路以及制作于中间介质层内的通孔互连结构。每个单像元器件包括:金属电极、硅纳米线列阵、以及集成于纳米线上的鳍式构筑超表面,以此实现对红外辐射的完美吸收,并将吸收的光子转变成表面等离激元热载流子转移至半导体中,产生光伏信号,实现探测功能。本发明探测芯片采用三维集成工艺制造,将红外感知单元和信号处理单元垂直堆叠起来,层间利用通孔填充技术实现Z方向垂直互联,得到高密度、低功耗、超大阵列规模的单片式焦平面阵列探测芯片。
Description
技术领域
本发明属于光电探测技术领域,具体涉及一种鳍式光伏型硅基等离激元热载流子红外探测芯片及其制作方法。
背景技术
目前应用于短波红外(1-3μm)光电探测的材料,几乎全部被III-V/II-VI族材料支配,比如:InGaAs、HgCdTe、InSb等。但这些材料却或多或少存在以下缺陷:材料成本昂贵、富含毒性造成环境污染、材料生长和器件制备工艺极其复杂不稳定、必须低温工作、受单晶材料锭条直径限制下无法实现大面积(目前GaAs最大面积为6英寸)等;其制备的芯片结构基本上包含两部分:MEMS技术制备的红外敏感阵列和CMOS工艺制备的信号读出电路,然后再将两部分集成,如:采用铟柱凸点倒焊技术单片集成InGaAs/InP和Si CMOS读出电路等,其技术复杂程度较高,导致当阵列规模做的比较大时,成本比较高,而且互连铟柱直径也难以持续缩减。另一方面,当前红外焦平面成像技术的发展趋势要求能满足大面积、探测单元面积不断缩小而实现高分辨成像、耐高温、性能稳定、低成本、与硅基CMOS读出电路可集成在同一衬底上形成红外光电芯片。基于此,近年来硅光子学提供了在同一芯片上实现光学和电子功能低成本集成的潜力,在硅基光电探测领域具有重要价值,其典型的技术方案有:采用晶圆键合技术直接集成III-V族材料或者Ge于硅衬底上,或者在硅上直接外延生长Ge等。然而,由于晶格失配,外延生长的Si-Ge界面具有大量缺陷和类位错复合,直接导致器件产生较大的漏电流和较小的分流电阻;为了消减缺点密度,通常会采用两步Ge沉积的方式进行外延生长,但是它涉及到了高温处理过程(>650℃),这就抑制了其与未经修饰的CMOS工艺的直接集成。
基于内部光电发射效应(IPE)的肖特基势垒光电探测器,可结合金属表面等离激元非辐射弛豫形成高效热载流子的机理,制备新型的全硅基短波红外探测器。光照激发在金属结构中产生的热载流子能够越过金属/半导体接触界面肖特基势垒,进入半导体内部,形成光电流,使得材料能够摆脱带隙限制,探测到光子能量小于材料本身禁带宽度的波段。该类型器件典型结构是在三维体硅材料上放置薄层金属,或者特殊排列的金属球或者金属天线,形成肖特基结。普遍问题是现有的光伏型全硅基热载流子器件在近红外波段的响应率都很低,基本上小于10 mA/W,并且量子效率也都小于1%、器件可靠性、可复制性差、无法大面积生产。虽然,我们前期工作已经成功将单像元全硅光电导型等离激元热载流子红外探测器性功能做到探测率高达4.38×1011Jones,同时峰值响应率为95mA/W,达到了可以和传统III-V/II-VI族半导体材料探测器相比拟的水平。但是对于功耗更低、应用更加广泛的高效率光伏型结构仍缺乏研究。甚至,对于能满足实际应用的大规模高效全硅基焦平面光电探测芯片的架构和制备方案仍然是处于空白状态。
发明内容
本发明目的在于提供一种鳍式光伏型硅基等离激元热载流子红外探测芯片及其制作方法,以解决硅材料受带隙限制不能工作与大于1.1µm波段的难题,克服目前光伏型硅基热电子红外器件响应率、量子效率和探测率低及暗电流较高的缺陷,实现全硅基光电探测器的高灵敏度、多频段红外监测能力。
本发明提供的鳍式光伏型硅基等离激元热载流子红外探测芯片,其结构如图1-2所示,包括:
一绝缘体上硅(SOI)衬底,该衬底的底层为普通硅材料,制备有CMOS信号读出电路;
中间层,为介质层,其内部集成有通孔互连结构;
顶层,为一薄层硅,作为红外光敏感层,在其内部分布有若干个对不同波段响应的像元阵列;
以及分布于像元子阵列里的单像元鳍式光伏型器件;
其中,单像元鳍式光伏型器件,其结构如图3所示:其中,所述单像元鳍式光伏型器件由特定周期的硅纳米线阵列、氧化硅介质层、硅衬底、两端连通的金属电极、具备公共连接端且集成于纳米线上的鳍式构筑金属超表面组成;硅纳米线和鳍式构筑超表面之间分布有单层二维材料(参见图4),该单层二维材料可用于增强单像元光伏器件的量子效率。
本发明中,所述芯片底层SiCMOS读出电路可采用65纳米或者更小的节点工艺,以实现信号的高速读取。
本发明中,所述通孔互连结构为through dielectric via工艺,其中填充材料为铜、钌、铑、铱或者钴等,阻挡层/衬垫层为Ta或者TaN等材料。
本发明中,介质层中的通孔互联结构的通孔直径可以做到小于等于0.7 µm的直径,可有效减小器件的RC延迟。
本发明中,所述顶层薄层硅的厚度为小于或者等于200纳米尺度,掺杂为中性、n型低掺杂或者p型低掺杂。
本发明中,所述单像元鳍式光伏型器件,可通过调节内部硅纳米线的线宽、周期、占空比、高度以及集成在纳米线上的超表面的线宽、周期、占空比、厚度等,实现对单波段红外光敏感,如:1.31 µm、1.49 µm、1.55 µm等波长。
本发明中,所述鳍式构筑超表面的材质为铬、金、银、铝、铜、钌、铑、铱、钴和铂金中的一种,或其中几种的组合。
本发明中,所述鳍式构筑超表面的金属厚度要小于该材料内部光激发产生的热载流子的平均自由程,一般小于40 纳米。
本发明中,所述分布于顶部薄层硅的像元阵列的形状为圆形、长方形、正方形或者正六边形,并可通过调节各个阵列内部的子像元,即:鳍式光伏型器件结构,使得单个子阵列仅对单频段红外光敏感,然后将这些对不同波长响应的子阵列集成于一片衬底上,以实现单片多频段探测功能。
本发明中,所述分布于纳米线和超表面之间的单层二维材料,可以是石墨烯、二硫化钼、黑鳞等。
本发明中,所述的两端连通的金属电极材质为铝、铬、金、钨、镍、钛、钯、铜、钌、铑、铱、钴或银中的一种,或其中几种的组合。
本发明中,所述的芯片工作原理如下:
利用芯片顶层红外感知单元结构中鳍式构筑超表面实现入射红外光的完美吸收,并调节光场模式将能量局域在金属和硅半导体交界面的金属层下表面,同时超表面在入射光激发下形成表面等离激元热载流子,并在其非辐射驰豫时间内进入半导体纳米线内,并进行一维量子输运被两端电极所收集形成光伏信号。产生的电学信号,再通过芯片中间介质层内的通孔互连传输到芯片底层Si CMOS读出电路的信号输入端,进行信号的放大、传输、存储等处理,之后输入到电脑或者显示屏进行成像展示。对于添加二维材料作为界面修饰层的结构:其中,金属实现入射光的完美吸收,并将光场局域在二维材料那一层,使得其充分吸收入射光,克服了单层材料吸收薄弱的缺陷;之后利用二维材料可以和硅形成肖特基势垒和较大内建电场,并且单层二维材料具备比三维金属材料更高的态密度特性,以此提升器件的量子效率。
本发明还提供上述鳍式光伏型硅基等离激元热载流子红外探测芯片的制作方法,具体步骤为:
(1)首先,准备1号硅衬底,按照标准RCA清洗:先SPM去除有机物,dHF去除氧化物,SC1 去除颗粒物,SC2 去除金属玷污,然后氮气干燥;之后将样品热氧化形成氧化硅介质层;如图5所示;
(2)然后,在上述生长完氧化硅层的1号衬底上用氢离子注入,注入分层深度为氧化层以下小于等于200纳米;如图6所示;
(3)准备2号硅衬底,在其正面按照标准CMOS制备工艺,完成光电探测芯片底层读出电路的制备;如图7所示;
(4)采用晶圆键合工艺,将上述氢离子注入后的带有氧化硅介质层的1号硅衬底和完成了读出电路制备的2号硅衬底的正面相键合;如图8所示;
(5)将键合后的样品进行退火处理,氢气泡撕裂1号硅衬底,得到:薄层硅-氧化硅介质层-硅衬底(已集成了CMOS读出电路)的SOI衬底;如图9所示;
(6)接着,制备顶层光敏单元:先在上述SOI衬底的顶层硅内采用光刻和干法刻蚀工艺制备若干个分布于不同区域的纳米线阵列,且每个子阵列的子像元具备相同的线条尺寸和周期;然后在上述纳米线阵列两端,采用光刻和金属沉积工艺形成连通的金属电极,并对准到相应位置;接着在上述纳米线区域采用光刻和金属沉积工艺制备具备公共连接端的纳米尺度鳍式构筑超表面;或者,先在纳米线区域转移一层CVD生长的二维材料,如:单层石墨烯,然后采用光刻和金属沉积工艺制备具备公共连接端的纳米尺度鳍式构筑超表面;并采用套刻技术,将该电极与底部相应通孔互连结构对准;如图10所示;
(7)接着在上述硅纳米线附近,采用套刻工艺,在相应电极位置光刻和刻蚀制备穿过氧化硅介质层的通孔互连结构;如图11所示;
(8)在上述通孔中,采用CVD或者PVD生长Ta或者TaN等材料,作为阻挡层/衬垫层;如图12所示;
(9)在上述通孔中,采用CVD、PVD、热蒸发或者电子束蒸发,生长铜、钌、铑、铱、或者钴等材料,实现信号互连,并精确连接到底部Si CMOS读出电路的信号输入端;如图13所示;
(10)最后,完成探测芯片的三维堆叠封装。
本发明中,步骤(7)的介质通孔直径可以做到小于等于0.7 µm的直径,可有效减小器件的RC延迟。
本发明中,步骤(3)的CMOS读出电路,可以采用现有的65纳米或者更小的节点工艺实现,以实现信号的高速读取。
本发明中,所述的鳍式构筑超表面的金属厚度要小于该材料内部光激发产生的热载流子的平均自由程,一般小于40 纳米。
本发明中,步骤(10)所述的三维堆叠封装,可将该鳍式光伏型全硅基红外信号感知单元、存储单元和读出电路逻辑计算单元纵向单片集成,实现新一代感知芯片。
从上述技术方案可以看出,本发明具有以下优势:
(1)芯片材料为全硅基和金属材料,制造技术与CMOS工艺兼容,该芯片可以将探测元器件与读出线路集成在一个衬底上,有利于高集成度、小型化的方向发展;
(2)芯片材料为全硅基和金属材料,成本低廉、理论来看目前红外焦平面探测列阵其达到12英寸晶圆的规模;此外,芯片可操作在室温或者高温环境、抗辐射能力强(SOI),可以应用在航天探测等重大领域;
(3)芯片敏感层中的单元器件为鳍式超表面结构,能够最大限度捕获入射光(完美吸收),实现红外波段高吸收率,且能实现光伏探测。而且,结合二维材料,如单层石墨烯,可提升芯片效率;
(4)芯片敏感层中的单元器件可借助超金属表面结构原理与性质,实现器件在1-3微米波段的选择性吸收,实现芯片多频段探测;
(5)芯片敏感层中的单元器件借助金属超表面和硅纳米线形成肖特基结,利用表面等离激元热载流子性质,解决了传统全硅基器件受材料能带限制而无法工作在大于1.1微米波段的难题;
(6)芯片敏感层中的单元器件基于一维硅纳米线,减小了器件工作的暗电流,有效提升了器件的探测率和低功率入射光监测能力;
(7)互连结构中介质通孔直径可以做到小于等于0.7 µm的直径,可有效减小器件的RC延迟;
(8)底层Si CMOS读出电路,可以采用现有的65纳米或者更小的节点工艺实现,以实现信号的高速读取;
(9)将红外感知单元和信号处理单元垂直堆叠起来,层间利用通孔填充技术实现Z方向垂直互联,更有利于实现高密度、低功耗、超大阵列规模的单片式焦平面阵列探测芯片。
本发明探测芯片的探测波段不受传统探测器的材料带隙的限制;超表面结构以及纳米线阵列的设计综合决定其探测波段,并能够覆盖整个1-3μm;可实现与CMOS读出电路完全兼容和直接集成,构成新型多频段、高分辨、大面积焦平面像素列阵的红外光电芯片架构。与传统的III-V/II-VI族化合物半导体探测器相比,本发明探测芯片可达到相媲美的性能水平,而且可工作于光伏型模式;在材料成本低廉环保、可工作于室温或者高温条件、可实现大面积(12英寸)、等方面有着远超传统探测器的优势,具有更加广泛的应用前景。
附图说明
图1为本发明芯片的工作原理图。
图2为本发明芯片的系统架构图。
图3为本发明芯片内部核心单元:鳍式光伏型全硅基探测器结构图。
图4为采用二维材料,如石墨烯,作为界面修饰层的鳍式光伏型硅基探测器结构图。
图5表示准备1号硅衬底,标准RCA清洗干净后高温氧化生成介质层。
图6表示将完成介质层生长的1号衬底用氢离子注入形成H2分层界面。
图7表示准备2号硅衬底,标准CMOS工艺完成读出电路的制备。
图8表示将1号衬底和2号衬底bonding。
图9表示将键合后的1号衬底和2号衬底进行退火工艺,则氢气泡会撕裂1号衬底,留下带有读出电路的SOI。
图10表示在带有读出电路的SOI顶部薄层硅内,基于标准CMOS工艺完成鳍式光伏型硅基红外探测单元阵列的制备。
图11表示完成芯片介质内通孔的刻蚀。
图12表示在介质通孔内生长阻挡层/衬垫层。
图13表示在介质通孔内完成金属填充,形成从顶部红外信号敏感单元到底层SiCMOS读出电路的高密度互连。
图14表示该鳍式全硅基光伏器件可在1-3微米波段实现选频探测功能。
图中标号:1为SOI衬底底层硅,2为SOI衬底中间介质层,3为介质通孔互连,4为顶层硅中制备的单频段红外敏感子阵列,5为红外敏感阵列中的单元器件:鳍式光伏型结构,6为鳍式光伏型硅基器件中的硅纳米线,7为鳍式光伏型硅基器件中的中间二氧化硅介质层,8为鳍式光伏型硅基器件中的CMOS读出电路层,9为鳍式光伏型硅基器件中的两端连通的金属电极,10为鳍式光伏型硅基器件中具有公共连接端的鳍式构筑超表面,11为二维材料界面修饰层,12为1号硅衬底,13为l号硅衬底氧化产生的二氧化硅介质层,14为1号硅衬底氢离子注入产生的H2界面层,15为具备读出电路的2号硅衬底,16为氢气泡撕裂后留下的带有读出电路的SOI衬底。
具体实施方式
下面结合附图和实施例进一步介绍本发明。参阅图1-3所示,整个器件结构包括:
一绝缘体上硅(SOI)衬底,该衬底的底层为用于制备CMOS信号读出电路的普通硅材料;中间层为介质层,可在其内部集成通孔互连结构;顶层为一薄层硅,作为红外光敏感层,在其内部分布了若干个对不同单波段响应的子阵列,以及分布于各个子阵列里的单像元鳍式光伏型器件。其中单像元鳍式光伏型器件结构,如图3所示:由SOI衬底上特定周期的硅纳米线阵列、两端连通的铝电极、具备公共连接端且集成在纳米线上的鳍式构筑超表面组成,分布于硅纳米线和鳍式构筑超表面之间的单层二维材料(如图4所示)可用于增强单像元光伏器件的量子效率。
图5-图13为本发明器件具体实施例所展示的制作流程图示,具体步骤为:
步骤1:准备硼离子注入的弱P型掺杂的1号硅衬底(参杂浓度~1015/cm3,<100>),按照标准RCA清洗:先SPM(硫酸+过氧化氢水溶液)去除有机物,4%的HF溶液去除氧化物,SC1(氢氧化铵+过氧化氢溶液)去除颗粒物,SC2 (盐酸+过氧化氢溶液)去除金属玷污,然后氮气干燥。之后将样品热氧化形成氧化硅介质层;
步骤2:在上述生长完氧化硅层的1号衬底上用氢离子注入(倾斜17°注入),注入分层深度为氧化层以下150纳米量级;
步骤3:准备2号硅衬底,在其正面按照标准CMOS制备工艺,完成光电探测芯片底层读出电路的制备;
步骤4:采用晶圆键合工艺,将上述氢离子注入后的带有氧化硅介质层的1号硅衬底和完成了读出电路制备的2号硅衬底的正面相键合;
步骤5:将上述键合后的样品进行退火工艺(500摄氏度退火15min),氢气泡撕裂1号硅衬底,得到:薄层硅-氧化硅介质层-硅衬底(已集成了CMOS读出电路)的SOI衬底;
步骤6:制备顶层光敏单元,先在上述SOI衬底的顶层硅内采用电子束光刻和干法刻蚀工艺制备若干个分布于不同区域的子阵列,且每个区域内子阵列的子像元具备相同的线条尺寸和周期;
步骤7:在上述纳米线阵列两端,采用光刻和金属沉积工艺形成连通的铝金属电极,然后退火形成Al和硅纳米线的欧姆接触;
步骤8:接着在上述纳米线区域采用光刻和金属沉积工艺制备具备公共连接端的纳米尺度鳍式构筑超表面;或者,先在纳米线区域转移一层CVD生长的单层石墨烯,然后采用光刻和金属沉积工艺制备具备公共连接端的金属超表面;并采用套刻技术,将该电极与底部相应通孔互连结构对准,其中:金属超表面材质为1 nm Ti和20nm Au;
步骤9:接着在上述纳米线附近,采用套刻工艺,在相应电极位置光刻和干法刻蚀制备穿过氧化硅介质层的通孔互连结构;
步骤10:在上述通孔中,采用CVD生长2纳米Ta材料,作为阻挡层/衬垫层;
步骤11:在上述通孔中,采用电子束蒸发,生长铜材料,实现信号互连,并精确连接到底部Si CMOS读出电路的信号输入端;
步骤12:完成探测芯片的三维堆叠封装。
以上所述的具体实施例及其工作原理和制备方法,对本发明的目的、技术方案和有益效果进行了进一步详细说明,所应理解的是,以上所述并不用于限制本发明,凡在本发明的精神和原则之内,所做的任何修改、等同替换、改进等,均应包含在本发明的保护范围之内。
Claims (9)
1.一种鳍式光伏型硅基等离激元热载流子红外探测芯片的制作方法,其特征在于,探测芯片结构包括:
一绝缘体上硅(SOI)衬底,该衬底的底层硅(1)制备有CMOS信号读出电路;
中间层(2),为介质层,其内部集成有若干个通孔互连结构(3);
顶层,为一薄层硅,作为红外光敏感层,在其内部分布有若干个对不同波段响应的像元阵列(4);
以及分布于像元子阵列里的单像元鳍式光伏型器件(5);
其中,所述单像元鳍式光伏型器件由特定周期的硅纳米线阵列(6)、氧化硅介质层(7)、硅衬底(8)、两端连通的金属电极(9)、具备公共连接端且集成于纳米线上的鳍式构筑金属超表面(10)组成;硅纳米线和鳍式构筑超表面之间分布有用于增强单像元光伏器件量子效率的单层二维材料(11)
具体步骤为:
(1)首先,准备1号硅衬底,按照标准RCA清洗;之后将样品热氧化形成氧化硅介质层;
(2)然后,在上述生长完氧化硅介质层的1号衬底上用氢离子注入,注入分层深度为氧化硅介质层以下小于等于200纳米;
(3)准备2号硅衬底,在其正面按照CMOS工艺,制备光电探测芯片底层读出电路;
(4)采用晶圆键合工艺,将上述氢离子注入后的带有氧化硅介质层的1号硅衬底和制备了读出电路的2号硅衬底的正面相键合;
(5)将键合后的样品进行退火处理,氢气泡撕裂1号硅衬底,得到薄层硅-氧化硅介质层-硅衬底的SOI衬底;
(6)接着,制备顶层光敏单元:先在上述SOI衬底的顶层硅内采用光刻和干法刻蚀工艺制备若干个分布于不同区域的纳米线阵列,且每个子阵列的子像元具备相同的线条尺寸和周期;然后在上述纳米线阵列两端,采用光刻和金属沉积工艺形成连通的金属电极,并对准到相应位置;接着在上述纳米线区域转移一层CVD生长的二维材料,然后采用光刻和金属沉积工艺制备具备公共连接端的纳米尺度鳍式构筑超表面;并采用套刻技术,将该电极与底部相应通孔互连结构对准;
(7)接着在上述硅纳米线附近,采用套刻工艺,在相应电极位置光刻和刻蚀制备穿过氧化硅介质层的通孔互连结构;
(8)在上述通孔中,采用CVD或者PVD生长Ta或者TaN材料,作为阻挡层/衬垫层;
(9)在上述通孔中,采用CVD、PVD、热蒸发或者电子束蒸发,生长铜、钌、铑、铱、或者钴材料,实现信号互连,并精确连接到底部Si CMOS读出电路的信号输入端;
(10)最后,完成探测芯片的三维堆叠封装,即将鳍式光伏型全硅基红外信号感知单元、存储单元和读出电路逻辑计算单元纵向单片集成,实现新一代感知芯片。
2.根据权利要求1所述的鳍式光伏型硅基等离激元热载流子红外探测芯片的制作方法,其特征在于,所述CMOS读出电路采用65纳米或者更小的节点工艺。
3. 根据权利要求1所述的鳍式光伏型硅基等离激元热载流子红外探测芯片的制作方法,其特征在于,所述通孔互连结构为through dielectric via工艺,其中填充材料为铜、钌、铑、铱或者钴,阻挡层/衬垫层为Ta或者TaN;通孔互联结构的通孔直径小于等于0.7 µm。
4.根据权利要求1所述的鳍式光伏型硅基等离激元热载流子红外探测芯片的制作方法,其特征在于,所述顶层薄层硅的厚度为小于或者等于200纳米;掺杂为中性、n型低掺杂或者p型低掺杂。
5.根据权利要求1所述的鳍式光伏型硅基等离激元热载流子红外探测芯片的制作方法,其特征在于,所述单像元鳍式光伏型器件,通过调节内部硅纳米线列阵的线宽、周期、占空比、高度、以及集成在纳米线上的金属超表面的线宽、周期、占空比、厚度,实现对单波段红外光敏感。
6.根据权利要求1所述的鳍式光伏型硅基等离激元热载流子红外探测芯片的制作方法,其特征在于,所述鳍式构筑超表面的材质为铬、金、银、铝、铜、钌、铑、铱、钴、铂金和硫化铜中的一种,或其中几种的组合;所述鳍式构筑超表面的金属厚度小于40 纳米。
7.根据权利要求1所述的鳍式光伏型硅基等离激元热载流子红外探测芯片的制作方法,其特征在于,所述分布于顶部薄层硅内的像元阵列的形状为圆形、长方形、正方形或者正六边形,并可通过调节各个阵列内部的子像元,即鳍式光伏型器件单元,使得单个子阵列仅对单波段红外光敏感,然后将这些对不同波长敏感的子阵列集成于一片衬底上,以实现单片多频段探测功能。
8.根据权利要求1所述的鳍式光伏型硅基等离激元热载流子红外探测芯片的制作方法,其特征在于,所述分布于纳米线和超表面之间的单层二维材料是石墨烯、二硫化钼或黑鳞。
9.根据权利要求1所述的鳍式光伏型硅基等离激元热载流子红外探测芯片的制作方法,其特征在于,所述的两端连通的金属电极材质为铝、铬、金、钨、镍、钛、钯、铜、钌、铑、铱、钴或银中的一种,或其中几种的组合。
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