CN112363906B - Test data processing device and method - Google Patents
Test data processing device and method Download PDFInfo
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- CN112363906B CN112363906B CN202010007239.7A CN202010007239A CN112363906B CN 112363906 B CN112363906 B CN 112363906B CN 202010007239 A CN202010007239 A CN 202010007239A CN 112363906 B CN112363906 B CN 112363906B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/36—Preventing errors by testing or debugging software
- G06F11/3668—Software testing
- G06F11/3672—Test management
- G06F11/3684—Test management for test design, e.g. generating new test cases
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/36—Preventing errors by testing or debugging software
- G06F11/3668—Software testing
- G06F11/3672—Test management
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/445—Program loading or initiating
- G06F9/44521—Dynamic linking or loading; Link editing at or after load time, e.g. Java class loading
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/448—Execution paradigms, e.g. implementations of programming paradigms
- G06F9/4482—Procedural
- G06F9/4484—Executing subprograms
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
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Abstract
The present invention relates to the field of data processing, and in particular, to a test data processing apparatus and method. The test data processing device comprises a dynamic link library module and an interface module; the dynamic link library module receives the test data, respectively starts a corresponding number of sub-threads according to the number of paths of the test data to process, and sends the processed data to the interface module; the interface module processes the received data into a form which can be directly identified by the J750 platform; the interface module imports the relevant test file to the J750 platform, creates a test instance and performs interface self-checking; during testing, the J750 test case sends an acquisition instruction to the analog board card or the digital board card, the analog board card or the digital board card sends test data to the data processing device, the data processing device processes the test data, and the test result is sent to the J750 test case. The test data processing device can modify and operate the debugging parameters on line, and improves the debugging efficiency.
Description
Technical Field
The present invention relates to the field of data processing, and in particular, to a test data processing apparatus and method.
Background
The J750 platform of Taruida is an industry standard for cost-effective testing of a wide variety of microcontrollers, FPGA (Field Programmable Gate Array), and digital audio/baseband devices. The system has more than 6000 mounting bases, can be widely used in more than 50 OSAT (On-Site Acceptance Tests) positions, and has a whole production interface solution for wafer classification and final test.
When J750 writes the test program, the test engineer may design using the system's own templates or VB code. With the development of integrated circuits, chip testing is more and more complex, the application range of templates carried by a J750 machine is more and more limited, and multiple ADC (Analog-to-Digital Converter)/DAC (Digital-to-Analog Converter) needs to be developed secondarily by a test engineer on the basis of the templates to meet the chip testing requirements.
The VB (Visual Basic) language used by the J750 machine has low efficiency of data and file processing capability relative to other languages, and the difference in the large data volume operation processing is obvious. In J750, the test time using VB was found to be 5 times or more longer than the calculation time using c++ in the ADC/DAC test where the data calculation is large. The method aims to improve the data processing efficiency on the J750 platform, firstly develops efficient VB data operation processing codes, and secondly adopts a dynamic link library method to construct a data processing algorithm by using other languages with higher data processing efficiency. For processing of multipath data, as VB has poor support on multithreading, J750 can only process one by one, and has low efficiency, if the multithreading is used, the advantage of multiple cores of the integrated circuit test system can be fully utilized, and the data processing speed is increased.
A dynamic link library file is an executable file that allows programs to share code and other resources necessary to perform a particular task. The dynamic link library may be created in multiple languages, such as C, C ++, VB, java, matlab, python, etc., and may also be run in the development platform of these languages. Because the dynamic link library can be called in a cross-platform manner, only the calling characteristic shared by all platforms is supported, and the dynamic link library is complicated to use.
Disclosure of Invention
Therefore, the main purpose of the present invention is to increase the data processing speed and the test efficiency.
To achieve the above object, the present invention provides a test data processing apparatus and method.
A test data processing device comprises a dynamic link library module and an interface module; the dynamic link library module receives the test data, respectively starts a corresponding number of sub-threads according to the number of paths of the test data to process, and sends the processed data to the interface module; the interface module processes the received data into a form which can be directly identified by the J750 platform; the interface module imports the relevant test file to the J750 platform, creates a test instance and performs interface self-checking; during testing, the J750 test case sends an acquisition instruction to the analog board card or the digital board card, the analog board card or the digital board card sends test data to the data processing device, the data processing device processes the test data, and the test result is sent to the J750 test case.
The interface module comprises a VB calling interface module and a class module; the VB calls an interface module to translate an interface of the dynamic link library module into an interface form which can be directly identified by the J750 platform; the class module re-integrates the interfaces to form members convenient for data processing and is used as a unified object for the test case of the J750 platform.
The dynamic link library module is realized by adopting C++ language programming, and the sub-threads in the dynamic link library module run asynchronously.
A method for processing test data by using a test data processing device comprises the following steps:
s1, importing relevant test files into a J750 platform and creating test cases;
s2, judging whether the interface self-checking passes or not, if so, entering the S3, otherwise, ending;
s3, running a J750 test case, and sending an acquisition instruction to an analog board card or a digital board card by the J750 test case;
s4, the analog board card or the digital board card sends test data to the data processing device;
s5, the data processing device processes the test data;
s6, judging whether the data processing is finished, if so, entering the S7, otherwise, judging again;
step S7, the data processing device sends the test result to the J750 test case.
The J750 test case operates in a VB environment, and the data processing device operates in a C++ environment.
After all the sub-threads for processing data in the dynamic link library module are finished running, the data processing device sends the test result to the J750 test case.
The invention has the beneficial effects that the scanning time is saved by adopting the optimization algorithm, the scanning test can be rapidly carried out, and the test efficiency is high. According to the invention, the code is written in VBA (Visual Basic for Application), so that the test system of J750 cannot be recompiled after the code is changed, the debugging parameters can be modified and operated on line, and the debugging efficiency is improved.
Drawings
FIG. 1 is a schematic diagram of a test data processing apparatus.
FIG. 2 is a flow chart of a test data processing method.
FIG. 3 is a class module self-test flow chart.
Detailed Description
A parameter rapid scan test apparatus and method according to the present invention will be described in detail with reference to the accompanying drawings.
As shown in fig. 1, a test data processing apparatus includes a dynamic link library module 1 and an interface module 2; the dynamic link library module 1 receives test data, starts corresponding number of sub threads for processing according to the number of paths of the test data, and sends the processed data to the interface module 2; the interface module 2 processes the received data into a form which can be directly identified by the J750 platform; the interface module 2 imports relevant test files to the J750 platform, creates test cases and performs interface self-checking; during testing, the J750 test case sends an acquisition instruction to the analog board card or the digital board card, the analog board card or the digital board card sends test data to the data processing device, the data processing device processes the test data, and the test result is sent to the J750 test case.
Because the dynamic link library can be called in a cross-platform manner, only the calling characteristic shared by all platforms is supported, and the use is complicated, so that the class module re-integrates all interfaces to form all members convenient for data processing.
The interface module 2 comprises a VB calling interface module 21 and a class module 22; VB calls the interface module 21 to 'translate' the interface of the dynamic link library module 1 into an interface form which can be directly identified by the J750 platform; class module 22 reassembles the interfaces to form the members that facilitate data processing and serve as a unified object for the test cases of the J750 platform.
The dynamic link library module 1 is realized by adopting C++ language programming, and the sub-threads in the dynamic link library module 1 run asynchronously.
As shown in fig. 2, a method for performing test data processing by using a test data processing device includes the following steps:
s1, importing relevant test files into a J750 platform and creating test cases;
s2, judging whether the interface self-checking passes or not, if so, entering the S3, otherwise, ending;
s3, running a J750 test case, and sending an acquisition instruction to an analog board card or a digital board card by the J750 test case;
s4, the analog board card or the digital board card sends test data to the data processing device;
s5, the data processing device processes the test data;
s6, judging whether the data processing is finished, if so, entering the S7, otherwise, judging again;
step S7, the data processing device sends the test result to the J750 test case.
The J750 test case operates in a VB environment, and the data processing device operates in a C++ environment.
After the running of all the sub-threads for processing data in the dynamic link library module 1 is finished, the data processing device sends the test result to the J750 test case.
After a new class module object is generated in the test case of J750, the class module will perform self-checking, and the self-checking flow is shown in fig. 3.
The dynamic link library file is a separate file, and file damage or interface parameter errors can cause unpredictable errors in interface call and even possible test system crash. When initializing the class module, a sample interface is called in advance to ensure that the link library file can be normally called; in order to prevent the unverified data processing module from running, the version information and the file content information of the dynamic link library are compared during initialization to confirm the correctness of the function call interface.
In the VB programming environment of J750, the multithreading support is poor, which easily leads to system breakdown; while the c++ environment supports better multithreading. When the dynamic link library processes multiple paths of data, each group of data is independently processed by sub-threads, so that the aim of minimizing the data processing time is achieved, and the data processing is synchronously performed while the J750 performs continuous data acquisition. After the dynamic link library receives the data, the data is processed in the sub-thread.
When a new sub-thread is started, the J750 test system can continue to execute subsequent test steps without waiting for data processing to complete until the test is completed.
And J750, after the test information is sent into the dynamic link library, the test case continues to run downwards without waiting for the completion of data processing, and after the test is finished, the test information is acquired from the dynamic link library when the test data is needed.
Because the sub-threads in the dynamic link library run asynchronously, the sub-threads may be performing data processing when obtaining the result, and thus, the final test result needs to be returned after waiting for all the sub-threads for data processing to end. Until all the sub-threads are processed or the test time is overtime, the dynamic link library returns the test related information and returns the test result to the test instance of J750.
Claims (7)
1. A test data processing apparatus, characterized in that: comprises a dynamic link library module (1) and an interface module (2); the dynamic link library module (1) receives test data, starts corresponding number of sub threads for processing according to the number of paths of the test data, and sends the processed data to the interface module (2); the interface module (2) processes the received data into a form which can be directly identified by the J750 platform; the interface module (2) imports relevant test files to the J750 platform, creates test cases and performs interface self-checking; during testing, the J750 test case sends an acquisition instruction to the analog board card or the digital board card, the analog board card or the digital board card sends test data to the data processing device, the data processing device processes the test data, and the test result is sent to the J750 test case.
2. The test data processing device of claim 1, wherein: the interface module (2) comprises a VB calling interface module (21) and a class module (22); the VB calls an interface module (21) to translate the interface of the dynamic link library module (1) into an interface form which can be directly identified by the J750 platform; the class module (22) reassembles the interfaces to form members that facilitate data processing and serve as a unified object for the test cases of the J750 platform.
3. Test data processing device according to claim 1 or 2, characterized in that: the dynamic link library module (1) is realized by adopting C++ language programming.
4. Test data processing device according to claim 1 or 2, characterized in that: the sub-threads in the dynamic link library module (1) run asynchronously.
5. A method of testing data processing using the testing data processing apparatus of claim 1, characterized by the steps of:
s1, importing relevant test files into a J750 platform and creating test cases;
s2, judging whether the interface self-checking passes or not, if so, entering the S3, otherwise, ending;
s3, running a J750 test case, and sending an acquisition instruction to an analog board card or a digital board card by the J750 test case;
s4, the analog board card or the digital board card sends test data to the data processing device;
s5, the data processing device processes the test data;
s6, judging whether the data processing is finished, if so, entering the S7, otherwise, judging again;
step S7, the data processing device sends the test result to the J750 test case.
6. The method of claim 5, wherein: the J750 test case operates in a VB environment, and the data processing device operates in a C++ environment.
7. The method of claim 5, wherein: after all the sub-threads for processing data in the dynamic link library module (1) are finished running, the data processing device sends the test result to the J750 test case.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3195366U (en) * | 2014-01-24 | 2015-01-15 | ▲し▼創電子股▲ふん▼有限公司 | Integrated circuit test interface in automatic test equipment |
| CN104866419A (en) * | 2014-10-17 | 2015-08-26 | 北汽福田汽车股份有限公司 | Virtual platform as well as application layer software testing method and system |
| CN109444723A (en) * | 2018-12-24 | 2019-03-08 | 成都华微电子科技有限公司 | A kind of chip detecting method based on J750 |
| CN109976306A (en) * | 2019-02-28 | 2019-07-05 | 北京空间飞行器总体设计部 | A kind of spacecraft telecommand based on Lua script quickly tests verifying system and method |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6868047B2 (en) * | 2001-12-12 | 2005-03-15 | Teradyne, Inc. | Compact ATE with time stamp system |
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- 2020-01-04 CN CN202010007239.7A patent/CN112363906B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3195366U (en) * | 2014-01-24 | 2015-01-15 | ▲し▼創電子股▲ふん▼有限公司 | Integrated circuit test interface in automatic test equipment |
| CN104866419A (en) * | 2014-10-17 | 2015-08-26 | 北汽福田汽车股份有限公司 | Virtual platform as well as application layer software testing method and system |
| CN109444723A (en) * | 2018-12-24 | 2019-03-08 | 成都华微电子科技有限公司 | A kind of chip detecting method based on J750 |
| CN109976306A (en) * | 2019-02-28 | 2019-07-05 | 北京空间飞行器总体设计部 | A kind of spacecraft telecommand based on Lua script quickly tests verifying system and method |
Non-Patent Citations (1)
| Title |
|---|
| 甘甜.基于Teradyne J750测试平台的射频芯片低成本测试方案开发及实现.《中国优秀硕士学位论文全文数据库信息科技辑》.2011,(第3期),I135-140. * |
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