CN112350765A - Multi-stage full-digital frequency conversion demodulation device based on digital resampling - Google Patents
Multi-stage full-digital frequency conversion demodulation device based on digital resampling Download PDFInfo
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- CN112350765A CN112350765A CN202011124867.XA CN202011124867A CN112350765A CN 112350765 A CN112350765 A CN 112350765A CN 202011124867 A CN202011124867 A CN 202011124867A CN 112350765 A CN112350765 A CN 112350765A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B7/00—Radio transmission systems, i.e. using radiation field
- H04B7/14—Relay systems
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Abstract
The invention discloses a multi-stage all-digital frequency conversion demodulation device based on digital resampling, and relates to the field of satellite data transmission. The device comprises a pre-sampling frequency converter, a shunt mapping frequency converter, a low-pass filter, a digital resampler, a matched filter, a digital forward frequency converter, a single-control digital frequency conversion orthogonal carrier generator, a digital reverse frequency converter and a double-control digital frequency conversion orthogonal carrier generator. The invention adopts a full digital signal processing flow, reasonably decomposes the demodulation process into a 4-level variable frequency processing process, and improves the flexibility and stability of the demodulation device. In addition, due to the addition of the digital resampling unit, the data processing capacity of the digital signal is optimized in the whole demodulation processing process, the distribution of the digital filter is optimized, the occupation scale of hardware resources of the device is reduced, and the realization efficiency of the demodulation device is improved.
Description
Technical Field
The invention relates to the field of satellite data transmission, in particular to a multi-stage full-digital frequency conversion demodulation device based on digital resampling, which can be used for receiving and demodulating satellite high-speed data transmission modulation signals in a satellite data ground receiving station data receiving subsystem.
Background
The satellite data ground receiving station data receiving subsystem is mainly used for receiving data transmission modulation signals transmitted by different satellites, the demodulation device demodulates the data transmission modulation signals to generate corresponding data, the data are transmitted to equipment such as a rear-end decoder or a security machine, further data processing is carried out, and finally remote sensing image data are obtained.
The traditional demodulation device is mainly divided into an intermediate frequency sampling demodulation device and a baseband sampling demodulation device, the baseband sampling demodulation device is essentially a demodulation mode combining digital signal processing and analog signal processing, the hardware complexity is high, the cost is high, and due to the non-ideal characteristic of an analog device, distortion is often brought to the processed signal, and the demodulation performance and the demodulation stability are influenced. The intermediate frequency sampling demodulation device can be realized in a full digital mode, but the software is complex to realize, the processing capacity of sampling data is large, the software realization complexity is high, and the logic resource quantity required by the software realization is large.
Disclosure of Invention
The invention aims to avoid the defects in the background technology and provides a multi-stage full-digital frequency conversion demodulation device based on digital resampling. The invention has the characteristics of high reliability, high stability, low complexity of realization and the like.
The purpose of the invention is realized as follows:
a multi-stage full-digital frequency conversion demodulation device based on digital resampling comprises a pre-sampling frequency converter 1, a shunt mapping frequency converter 2, a first low-pass filter 3-1, a second low-pass filter 3-2, a digital resampler 4, a first matched filter 5-1, a second matched filter 5-2, a digital forward frequency converter 6, a single-control digital frequency conversion orthogonal carrier generator 7, a digital reverse frequency converter 8 and a double-control digital frequency conversion orthogonal carrier generator 9; wherein the content of the first and second substances,
the pre-sampling frequency converter 1 performs sampling frequency conversion processing on an input intermediate frequency analog modulation signal and outputs a digital signal to the shunt mapping frequency converter 2; the method is characterized in that a pre-sampling frequency converter 1 sets parameters according to carrier frequency of an input intermediate frequency analog modulation signal, automatically adjusts sampling clock frequency, and enables in-band new carrier frequency generated after sampling and mixing of a sampling clock and the carrier frequency of the intermediate frequency analog modulation signal to be one fourth of the sampling clock frequency;
the shunt mapping frequency converter 2 processes the digital signals transmitted by the pre-sampling frequency converter 1 to generate two paths of orthogonal frequency mixing digital signals which are respectively transmitted to a first low-pass filter 3-1 and a second low-pass filter 3-2;
the first low-pass filter 3-1 and the second low-pass filter 3-2 respectively generate a digital baseband signal carrying a carrier error and transmit the digital baseband signal to the digital resampler 4;
the digital resampler 4 automatically adjusts the internal resampling data rate according to the modulation signal symbol rate setting parameters input from the outside and the baseband signal output by the digital inverse frequency converter 8, resamples two paths of digital baseband signals transmitted by the first low-pass filter 3-1 and the second low-pass filter 3-2, generates two paths of digital baseband signals sampled at double symbol rates, and respectively transmits the two paths of digital baseband signals to the first matched filter 5-1 and the second matched filter 5-2;
the first matched filter 5-1 and the second matched filter 5-2 carry out matched filtering processing on the input signal, and then the processed signal is transmitted to the digital forward frequency converter 6;
the single-control digital frequency conversion orthogonal carrier generator 7 generates two paths of orthogonal carrier signals according to externally input digital frequency conversion orthogonal carrier frequency control words and inputs the two paths of orthogonal carrier signals to the digital forward frequency converter 6;
the digital forward frequency converter 6 outputs two paths of digital baseband signals carrying stable forward carrier errors to the digital reverse frequency converter 8 according to signals input by the first matched filter 5-1 and the second matched filter 5-2 and the corresponding two paths of orthogonal carrier signals;
the double-control digital frequency conversion orthogonal carrier generator 9 controls the digital and baseband signals output by the digital inverse frequency converter 8 according to the digital frequency conversion orthogonal carrier frequency, automatically adjusts and generates two paths of orthogonal carrier signals and feeds the two paths of orthogonal carrier signals back to the digital inverse frequency converter 8;
the digital inverse frequency converter 8 outputs a digital baseband signal after coherent demodulation according to the input signal of the digital forward frequency converter 6 and the feedback signal of the double-control digital frequency conversion orthogonal carrier generator 9, and completes coherent demodulation of the analog intermediate frequency modulation signal.
Further, the split mapping frequency converter 2 includes a serial-to-parallel converter 10, a first fixed coefficient mapper 11-1, a second fixed coefficient mapper 11-2, a third fixed coefficient mapper 11-3, a fourth fixed coefficient mapper 11-4, a fifth fixed coefficient mapper 11-5, a sixth fixed coefficient mapper 11-6, a seventh fixed coefficient mapper 11-7, an eighth fixed coefficient mapper 11-8, a first parallel-to-serial converter 12-1, and a second parallel-to-serial converter 12-2; the serial-to-parallel converter 10 converts the serial digital signal input from the pre-sampling frequency converter 1 into 4 parallel digital signals, inputs the first parallel signal after conversion to the first fixed coefficient mapper 11-1 and the fifth fixed coefficient mapper 11-5, inputs the second parallel signal after conversion to the second fixed coefficient mapper 11-2 and the sixth fixed coefficient mapper 11-6, inputs the third parallel signal after conversion to the third fixed coefficient mapper 11-3 and the seventh fixed coefficient mapper 11-7, and inputs the fourth parallel signal after conversion to the fourth fixed coefficient mapper 11-4 and the eighth fixed coefficient mapper 11-8; the first fixed coefficient mapper 11-1 maps the input signal to 0 directly and outputs it; the second fixed coefficient mapper 11-2 maps the input signal directly to an output signal; the third fixed coefficient mapper 11-3 maps the input signal to 0 directly and outputs it; the fourth fixed coefficient mapper 11-4 maps the input signal directly to its own negative value and outputs it; the fifth fixed coefficient mapper 11-5 maps the input signal directly to an output signal; the sixth fixed coefficient mapper 11-6 maps the input signal to 0 directly and outputs it; the seventh fixed coefficient mapper 11-7 maps the input signal directly to its own negative value and outputs it; the eighth fixed coefficient mapper 11-8 maps the input signal to 0 directly and outputs it; the first parallel-to-serial converter 12-1 receives the output signals of the first fixed coefficient mapper 11-1, the second fixed coefficient mapper 11-2, the third fixed coefficient mapper 11-3 and the fourth fixed coefficient mapper 11-4 in sequence, converts them into equivalent serial data, and then transmits them to the first low pass filter 3-1; the second parallel-to-serial converter 12-2 receives output signals of the fifth, sixth, seventh and eighth fixed coefficient mappers 11-5, 11-6, 11-7 and 11-8 in sequence, converts them into equivalent serial data, and then passes to the second low pass filter 3-2.
Further, the digital resampler 4 includes a first data buffer 13-1, a second data buffer 13-2, a data high truncator 14, a data low truncator 15, a first accumulator 16, a first data loop memory 17-1, a second data loop memory 17-2, a filter coefficient memory 18, a first weighted summer 19-1, a second weighted summer 19-2, a rate matcher 20, and a timing error extractor 21; the first data buffer 13-1 receives the digital signal output by the first low-pass filter 3-1, sequentially combines 3 adjacent input signals with the current input signal as a start to generate a combined signal with 4 input signals as a group, and outputs the combined signal to the first data circular memory 17-1; the second data buffer 13-2 receives the digital signal output by the second low-pass filter 3-2, sequentially combines 3 adjacent input signals with the current input signal as a start to generate a combined signal with 4 input signals as a group, and outputs the combined signal to the second data circular memory 17-2; the space addresses stored in the first data circulating memory 17-1 and the second data circulating memory 17-2 are in a circulating accumulation mode, so that the combined signals output by the first data buffer 13-1 and the second data buffer 13-2 respectively complete circulating storage; in addition, the second data buffer 13-2 also outputs a data cumulative buffering amount data signal to the rate matcher 20; the first data cycle memory 17-1 and the second data cycle memory 17-2 respectively receive the data reading address transmitted by the data high-order bit interceptor 14 and output the stored combined signal corresponding to the currently received data reading address; the combined signals output by the first data cycle memory 17-1 and the second data cycle memory 17-2 are respectively transmitted to a first weighted summer 19-1 and a second weighted summer 19-2; the filter coefficient memory 18 receives the data reading address output by the data low-order bit interceptor 15 and outputs the filter combination coefficient corresponding to the currently received data reading address, and each group of output filter combination coefficients comprises 4 filter coefficients; the first weighted summing device 19-1 receives the combined signal output by the first data loop memory 17-1 and the filter combined coefficient output by the filter coefficient memory 18, and sequentially uses 4 filter coefficients in the filter combined coefficient as weighted values of 4 data in the combined signal, completes the weighted summing operation of the filter combined coefficient and the combined signal, and outputs the result to the first matched filter 5-1; the second weighted summing device 19-2 receives the combined signal output by the second data loop memory 17-2 and the filter combined coefficient output by the filter coefficient memory 18, and sequentially uses 4 filter coefficients in the filter combined coefficient as weighted values of 4 data in the combined signal, completes the weighted summing operation of the filter combined coefficient and the combined signal, and outputs the result to the second matched filter 5-2; the timing error extractor 21 receives the baseband signal output by the digital inverse frequency converter 8, generates a timing error signal, and inputs the timing error signal to the first accumulator 16; the first accumulator 16 receives the timing error signal output by the timing error extractor 21 and the modulation signal symbol rate setting parameter input from the outside, combines the timing error signal and the modulation signal symbol rate setting parameter, and performs the accumulation calculation as an iterative value, generates address information and outputs the address information to the data high-order bit truncator 14 and the data low-order bit truncator 15, the first accumulator 16 simultaneously receives the address information output control signal output by the rate matcher 20, when the address information output control signal is valid, the first accumulator 16 performs the accumulation calculation inside, generates and outputs the address information, and when the address information output control signal is invalid, the first accumulator 16 stops the accumulation calculation inside and stops outputting the address information; the data high-order bit interceptor 14 receives the address information output by the first accumulator 16, and intercepts the high-order address information to generate a data reading address and an address high-order accumulated total data signal, wherein the data reading address is output to the first data cycle memory 17-1 and the second data cycle memory 17-2, respectively, and the address high-order accumulated total data signal is output to the rate matcher 20; the data low-order bit interceptor 15 receives the address information output by the first accumulator 16, intercepts the low-order address information and outputs the low-order address information to the filter coefficient memory 18; the rate matcher 20 receives the data accumulation buffered total data signal output by the second data buffer 13-2 and the address high-order accumulated total data signal output by the data high-order bit truncator 14, compares the received two paths of data to generate a control signal, and outputs the control signal to the first accumulator 16.
Further, the digital forward converter 6 comprises a first multiplier 22-1, a second multiplier 22-2, a third multiplier 22-3, a fourth multiplier 22-4, a first adder 23 and a first subtractor 24; the first multiplier 22-1 receives the output signal of the first matched filter 5-1 and the 1 st path signal output by the single-control digital frequency conversion orthogonal carrier generator 7, multiplies the two paths of signals and outputs the multiplied signals to the first subtracter 24; the second multiplier 22-2 receives the output signal of the first matched filter 5-1 and the 2 nd path signal output by the single-control digital frequency conversion orthogonal carrier generator 7, multiplies the two paths of signals and outputs the multiplied signals to the first adder 23; the third multiplier 22-3 receives the output signal of the second matched filter 5-2 and the 1 st path signal output by the single-control digital frequency conversion orthogonal carrier generator 7, multiplies the two paths of signals and outputs the multiplied signals to the first adder 23; the fourth multiplier 22-4 receives the output signal of the second matched filter 5-2 and the 2 nd path signal output by the single-control digital frequency conversion orthogonal carrier generator 7, multiplies the two paths of signals and outputs the multiplied signals to the first subtracter 24; the first adder 23 adds the two received data and outputs the data to the digital inverse frequency converter 8; the first subtractor 24 subtracts the received output signal of the fourth multiplier 22-4 from the received output signal of the first multiplier 22-1 and outputs the subtracted result to the digital inverse converter 8.
Further, the digital inverse frequency converter 8 comprises a fifth multiplier 25-1, a sixth multiplier 25-2, a seventh multiplier 25-3, an eighth multiplier 25-4, a second subtractor 26 and a second adder 27; the fifth multiplier 25-1 receives the first path of signal output by the digital forward frequency converter 6 and the 1 st path of signal output by the dual-control digital frequency conversion orthogonal carrier generator 9, multiplies the two paths of signals and outputs the multiplied signals to the second adder 27; the sixth multiplier 25-2 receives the first path of signal output by the digital forward frequency converter 6 and the 2 nd path of signal output by the double-control digital frequency conversion orthogonal carrier generator 9, multiplies the two paths of signals and outputs the multiplied signals to the second subtracter 26; the seventh multiplier 25-3 receives the second path of signals output by the digital forward frequency converter 6 and the 1 st path of signals output by the double-control digital frequency conversion orthogonal carrier generator 9, multiplies the two paths of signals and outputs the multiplied signals to the second subtracter 26; the eighth multiplier 25-4 receives the second path of signal output by the digital forward frequency converter 6 and the 2 nd path of signal output by the dual-control digital frequency conversion orthogonal carrier generator 7, multiplies the two paths of signals and outputs the multiplied signals to the second adder 27; the second adder 27 adds the two received data and outputs the result; the second subtractor 26 subtracts the received output signal of the sixth multiplier 25-2 from the received output signal of the seventh multiplier 25-3 and outputs the result.
Further, the single-control digital frequency conversion orthogonal carrier generator 7 comprises a second accumulator 28, a first truncator 29, a first sine wave data memory 30 and a first cosine wave data memory 31; the second accumulator 28 receives the digital frequency conversion orthogonal carrier frequency control word, and performs accumulation operation by using the digital frequency conversion orthogonal carrier frequency control word as an accumulation stepping value, and the second accumulator 28 outputs the accumulation value to the first truncator 29; the first truncator 29 truncates the received accumulated value to generate and output an address signal; the first sine wave data memory 30 receives the address signal output by the first truncator 29 and outputs the sine wave data value corresponding to the currently received address signal to the digital forward converter 6; the first cosine wave data memory 31 receives the address signal output by the first truncator 29, and outputs a cosine sampling data value corresponding to the currently received address signal to the digital forward converter 6.
Further, the dual-control digital frequency conversion orthogonal carrier generator 9 includes a third accumulator 32, a third adder 33, a second bit truncator 34, a second sine wave data memory 35, a second cosine wave data memory 36 and a carrier error extractor 37; the third accumulator 28 receives the signal output by the third adder 33, and performs accumulation operation using the signal as an accumulation step value, and the third accumulator 32 outputs the accumulation value to the second truncator 34; the second truncator 34 truncates the received accumulated value, generates an address signal and outputs the address signal; the second sine wave data memory 35 receives the address signal output by the second truncator 34, and outputs the sine wave data value corresponding to the currently received address signal to the digital inverse frequency converter 8; the second cosine wave data memory 36 receives the address signal output by the second truncator 34, and outputs a cosine sampling data value corresponding to the currently received address signal to the digital inverse frequency converter 8; the carrier error extractor 37 receives the output signal of the digital inverse frequency converter 8, calculates to obtain a carrier error signal and outputs the carrier error signal; the third adder 33 receives the digital frequency-conversion orthogonal carrier frequency control word and the carrier error signal output by the carrier error extractor 37, adds the two received signals, and outputs the sum to the third accumulator 32.
Compared with the background technology, the invention has the following advantages:
1. the invention reasonably decomposes the demodulation process into a 4-level variable frequency processing process, thereby reducing the realization complexity of the demodulation device.
2. The digital resampling unit is added in the invention, so that the data processing capacity of the digital signal is optimized in the whole demodulation processing process, the distribution of the digital filter is optimized, the logic resource required by software implementation is reduced, and the stability and the implementation efficiency of the demodulation device are improved.
3. The invention is realized in a full digital mode, has simple structure and strong portability, and can be realized in an embedded software mode because units such as a ROM, a lookup table, a multiplier, an adder and the like are integrated in the current mainstream FPGA, thereby having popularization and application values.
Drawings
FIG. 1 is a schematic block diagram of a circuit of an embodiment of the invention.
Fig. 2 is a schematic block circuit diagram of the shunt-mapped frequency converter of fig. 1.
Fig. 3 is a circuit schematic block diagram of the digital resampler of fig. 1.
Fig. 4 is a schematic block circuit diagram of the digital forward converter of fig. 1.
Fig. 5 is a schematic block circuit diagram of the digital inverse converter of fig. 1.
Fig. 6 is a schematic block diagram of the circuit of the single-controlled digital frequency-converted quadrature carrier generator of fig. 1.
Fig. 7 is a schematic block diagram of the dual-control digital frequency-conversion quadrature carrier generator of fig. 1.
Detailed Description
The technical solution of the present invention will be described in detail below with reference to the accompanying drawings.
Referring to fig. 1 to 7, a digital resampling-based multi-stage all-digital frequency conversion demodulation apparatus includes a pre-sampling frequency converter 1, a shunt mapping frequency converter 2, a low pass filter 3-1 and a low pass filter 3-2, a digital resampler 4, a matched filter 5-1 and a matched filter 5-2, a digital forward frequency converter 6, a single-control digital frequency conversion orthogonal carrier generator 7, a digital inverse frequency converter 8, and a double-control digital frequency conversion orthogonal carrier generator 9.
The pre-sampling frequency converter 1 performs sampling frequency conversion processing on an input intermediate frequency analog modulation signal. Here, the pre-sampling frequency converter 1 automatically adjusts the sampling clock frequency according to the input carrier frequency setting parameter of the modulation signal, so that the in-band new carrier frequency generated after the sampling clock is mixed with the carrier sampling of the intermediate frequency analog modulation signal is one fourth of the sampling clock frequency.
The digital signal output by the pre-sampling frequency converter 1 is processed by the shunt mapping frequency converter 2 to generate two paths of orthogonal frequency mixing digital signals. The two paths of orthogonal frequency mixing digital signals are respectively processed by a low-pass filter 3-1 and a low-pass filter 3-2 to generate two paths of digital baseband signals carrying carrier errors.
The two paths of digital baseband signals output by the low-pass filter 3-1 and the low-pass filter 3-2 are processed by a digital resampler 4. Here, the digital resampler 4 automatically adjusts the internal resampling data rate according to the input modulation signal symbol rate setting parameter and the baseband signal output by the digital inverse frequency converter 8, and generates two paths of digital baseband signals sampled at twice the symbol rate.
The two paths of digital baseband signals output by the digital resampler 4 are respectively subjected to matched filtering processing through a matched filter 5-1 and a matched filter 5-2. The output signals of the matched filter 5-1 and the matched filter 5-2 are respectively input into the digital forward frequency converter 6, and simultaneously, the single-control digital frequency conversion orthogonal carrier generator 7 generates two paths of orthogonal carrier signals according to the digital frequency conversion orthogonal carrier frequency control word and inputs the two paths of orthogonal carrier signals into the digital forward frequency converter 6.
The digital forward frequency converter 6 outputs two paths of digital baseband signals carrying stable forward carrier errors to the digital reverse frequency converter 8, and meanwhile, the double-control digital frequency conversion orthogonal carrier generator 9 controls the digital baseband signals output by the digital reverse frequency converter 8 according to the digital frequency conversion orthogonal carrier frequency, automatically adjusts and generates two paths of orthogonal carrier signals and inputs the two paths of orthogonal carrier signals to the digital reverse frequency converter 8.
The digital inverse frequency converter 8 outputs the digital baseband signal after coherent demodulation, and completes coherent demodulation of the analog intermediate frequency modulation signal.
In this embodiment, the shunt mapping frequency converter 2, the low pass filter 3-1 and the low pass filter 3-2, the digital resampler 4, the matched filter 5-1 and the matched filter 5-2, the digital forward frequency converter 6, the single-control digital frequency conversion orthogonal carrier generator 7, the digital inverse frequency converter 8 and the double-control digital frequency conversion orthogonal carrier generator 9 are all implemented by a Virtex7 type FPGA manufactured by XILINX corporation, usa.
Fig. 2 is a schematic block diagram of a shunt-mapped frequency converter, an embodiment connecting the lines according to fig. 2. The demux mapping frequency converter 2 includes a serial-to-parallel converter 10, a fixed coefficient mapper 11-1, a fixed coefficient mapper 11-2, a fixed coefficient mapper 11-3, a fixed coefficient mapper 11-4, a fixed coefficient mapper 11-5, a fixed coefficient mapper 11-6, a fixed coefficient mapper 11-7 and a fixed coefficient mapper 11-8, a parallel-to-serial converter 12-1, and a parallel-to-serial converter 12-2.
The serial-to-parallel converter 10 converts the serial digital signal input by the pre-sampling frequency converter 1 into 4 paths of parallel digital signals, inputs the first path of parallel signals after conversion into the fixed coefficient mapper 11-1 and the fixed coefficient mapper 11-5, inputs the second path of parallel signals after conversion into the fixed coefficient mapper 11-2 and the fixed coefficient mapper 11-6, inputs the third path of parallel signals after conversion into the fixed coefficient mapper 11-3 and the fixed coefficient mapper 11-7, and inputs the fourth path of parallel signals after conversion into the fixed coefficient mapper 11-4 and the fixed coefficient mapper 11-8.
The fixed coefficient mapper 11-1 maps the input signal to 0 directly and outputs it; the fixed coefficient mapper 11-2 maps the input signal directly to an output signal; the fixed coefficient mapper 11-3 maps the input signal to 0 directly and outputs it; the fixed coefficient mapper 11-4 maps the input signal directly to its own negative value and outputs it; the fixed coefficient mapper 11-5 maps the input signal directly to an output signal; the fixed coefficient mapper 11-6 maps the input signal to 0 directly and outputs it; the fixed coefficient mapper 11-7 maps the input signal directly to its own negative value and outputs it; the fixed coefficient mapper 11-8 directly maps the input signal to 0 and outputs it.
The parallel-to-serial converter 12-1 receives the output signals of the fixed coefficient mapper 11-1, the fixed coefficient mapper 11-2, the fixed coefficient mapper 11-3 and the fixed coefficient mapper 11-4 in sequence and converts them into equivalent serial data; the output signal of the parallel-to-serial converter 12-1 is input to a low-pass filter 3-1.
The parallel-to-serial converter 12-2 receives the output signals of the fixed coefficient mapper 11-5, the fixed coefficient mapper 11-6, the fixed coefficient mapper 11-7 and the fixed coefficient mapper 11-8 in sequence and converts them into equivalent serial data; the output signal of the parallel-to-serial converter 12-2 is input to the low-pass filter 3-2.
FIG. 3 is a schematic block diagram of a digital resampler, an embodiment connecting lines according to FIG. 3. The digital resampler 4 includes data buffers 13-1 and 13-2, a data upper truncator 14, a data lower truncator 15, an accumulator 16, data loop memories 17-1 and 17-2, a filter coefficient memory 18, weighted summers 19-1 and 19-2, a rate matcher 20, and a timing error extractor 21.
The data buffer 13-1 receives the digital signal output by the low-pass filter 3-1, sequentially combines 3 adjacent input signals starting from the current input signal to generate a combined signal with 4 input signals as a group, and outputs the combined signal to the data circular memory 17-1.
The data buffer 13-2 receives the digital signal output from the low-pass filter 3-2, sequentially combines 3 adjacent input signals starting from the current input signal to generate a combined signal in which 4 input signals are grouped, and outputs the combined signal to the data loop memory 17-2. In addition, the second data buffer 13-2 outputs a data accumulation buffer amount data signal to the rate matcher 20.
The addresses of the storage spaces in the data circulating memory 17-1 and the data circulating memory 17-2 are in a circulating accumulation mode, so that the combined signals output by the data buffer 13-1 and the data buffer 13-2 respectively complete circulating storage; the data cycle memory 17-1 and the data cycle memory 17-2 respectively receive the data read addresses generated and output by the data high-order bit truncator 14 and output the stored combined signals corresponding to the currently received data read addresses.
The combined signals output from the data loop memory 17-1 and the data loop memory 17-2 are input to the weighted summer 19-1 and the weighted summer 19-2, respectively.
The filter coefficient memory 18 receives the data read address output by the data low-order bit truncator 15, and outputs the filter combination coefficient corresponding to the currently received data read address, where each group of output filter combination coefficients includes 4 filter coefficients.
The weighted summing device 19-1 receives the combined signal output from the data loop memory 17-1 and the filter combining coefficient output from the filter coefficient memory 18, and sequentially uses 4 filter coefficients in the filter combining coefficient as weighted values of 4 data in the combined signal, thereby completing the weighted summing operation of the filter combining coefficient and the combined signal, and outputting the result to the matched filter 5-1.
The weighted summing device 19-2 receives the combined signal output from the data loop memory 17-2 and the filter combining coefficient output from the filter coefficient memory 18, and sequentially uses 4 filter coefficients in the filter combining coefficient as weighted values of 4 data in the combined signal, thereby completing the weighted summing operation of the filter combining coefficient and the combined signal, and outputting the result to the matched filter 5-2.
The timing error extractor 21 receives the baseband signal output from the digital inverse converter 8, generates a timing error signal, and inputs the timing error signal to the accumulator 16.
The accumulator 16 receives the timing error signal and the modulation signal symbol rate setting parameter output by the timing error extractor 21, combines them to be an iterative value to perform accumulation calculation, generates address information and outputs the address information to the data high-order truncator 14 and the data low-order truncator 15, the accumulator 16 simultaneously receives the address information output control signal output by the rate matcher 20, when the address information output control signal is valid, the accumulator 16 performs accumulation operation to generate and output address information, and when the address information output control signal is invalid, the accumulator 16 stops accumulation operation and stops outputting address information.
The data high-order bit truncator 14 receives the address information output by the first accumulator 16, and truncates the high-order address information to generate a data reading address and an address high-order cumulative total data signal, wherein the data reading address is output to the first data cycle memory 17-1 and the second data cycle memory 17-2, and the address high-order cumulative total data signal is output to the rate matcher 20.
The data low-order bit truncator 15 receives the address information output by the accumulator 16, truncates the low-order address information and outputs the result to the filter coefficient memory 18.
The rate matcher 20 receives the data accumulation buffer total amount data signal output by the data buffer 13-2 and the address high-order accumulation total amount data signal output by the data high-order bit truncator 14, compares the values of the two received data paths, generates a control signal, and outputs the control signal to the accumulator 16.
Fig. 4 is a circuit schematic of a digital forward converter, an embodiment connecting the lines according to fig. 4. The digital forward converter 6 comprises a multiplier 22-1, a multiplier 22-2, a multiplier 22-3, a multiplier 22-4, an adder 23 and a subtracter 24.
The multiplier 22-1 receives the output signal of the matched filter 5-1 and the 1 st path signal output by the single-control digital frequency conversion orthogonal carrier generator 7, multiplies the two paths of signals and outputs the multiplied signals to the subtracter 24.
The multiplier 22-2 receives the output signal of the matched filter 5-1 and the 2 nd path signal output by the single-control digital frequency conversion orthogonal carrier generator 7, multiplies the two paths of signals and outputs the multiplied signals to the adder 23.
The multiplier 22-3 receives the output signal of the matched filter 5-2 and the 1 st path signal output by the single-control digital frequency conversion orthogonal carrier generator 7, multiplies the two paths of signals and outputs the multiplied signals to the adder 23.
The multiplier 22-4 receives the output signal of the matched filter 5-2 and the 2 nd path signal output by the single-control digital frequency conversion orthogonal carrier generator 7, multiplies the two paths of signals and outputs the multiplied signals to the subtracter 24.
The adder 23 adds the two received data and outputs the result to the digital inverse converter 8.
The subtractor 24 subtracts the received output signal of the multiplier 22-4 from the received output signal of the multiplier 22-1 and outputs the subtracted result to the digital inverse converter 8.
Fig. 5 is a schematic block diagram of a digital inverse converter, an embodiment connecting the lines according to fig. 5. The digital inverse converter 7 includes a multiplier 25-1, a multiplier 25-2, a multiplier 25-3, a multiplier 25-4, a subtractor 26, and an adder 27.
The multiplier 22-1 receives the first path of signal output by the digital forward frequency converter 6 and the 1 st path of signal output by the dual-control digital frequency conversion orthogonal carrier generator 9, multiplies the two paths of signals, and outputs the multiplied signals to the adder 27.
The multiplier 25-2 receives the first path of signal output by the digital forward frequency converter 6 and the 2 nd path of signal output by the dual-control digital frequency conversion orthogonal carrier generator 9, multiplies the two paths of signals and outputs the multiplied signals to the subtracter 26.
The multiplier 25-3 receives the second path of signal output by the digital forward frequency converter 6 and the 1 st path of signal output by the dual-control digital frequency conversion orthogonal carrier generator 9, multiplies the two paths of signals and outputs the multiplied signals to the subtracter 26.
The multiplier 25-4 receives the second path of signal output by the digital forward frequency converter 6 and the 2 nd path of signal output by the dual-control digital frequency conversion orthogonal carrier generator 7, multiplies the two paths of signals and outputs the multiplied signals to the adder 27.
The adder 27 adds the two received data and outputs the result; the subtractor 26 subtracts the received output signal of the multiplier 25-2 from the received output signal of the multiplier 25-3 and outputs the subtracted result.
FIG. 6 is a schematic block diagram of a single-control digital frequency-conversion quadrature carrier generator, an embodiment connecting lines according to FIG. 6.
The single-control digital frequency-conversion quadrature carrier generator 7 comprises an accumulator 28, a truncator 29, a sine wave data memory 30 and a cosine wave data memory 31.
The accumulator 28 receives the digital frequency conversion orthogonal carrier frequency control word and performs accumulation operation using the digital frequency conversion orthogonal carrier frequency control word as an accumulation step value, and the accumulator 28 outputs the accumulation value to the truncator 29.
The truncator 29 truncates the received accumulated value, generates an address signal, and outputs the address signal.
The sine wave data memory 30 receives the address signal output from the bit slicer 29, and outputs the sine wave data value corresponding to the currently received address signal to the digital forward converter 6.
The cosine wave data memory 31 receives the address signal output from the bit truncator 29, and outputs a cosine sampling data value corresponding to the currently received address signal to the digital forward converter 6.
FIG. 7 is a schematic block diagram of a digital resampling unit, an embodiment connecting the lines according to FIG. 7. The dual-control digital frequency-conversion quadrature carrier generator 9 includes an accumulator 32, an adder 33, a truncator 34, a sine wave data memory 35, a cosine wave data memory 36, and a carrier error extractor 37.
The accumulator 28 receives the signal output from the adder 33 and performs an accumulation operation as an accumulation step value, and the accumulator 32 outputs the accumulation value to the truncator 34.
The truncator 34 performs truncating processing on the received accumulated value, generates and outputs an address signal.
The sine wave data memory 35 receives the address signal output from the bit slicer 34, and outputs the sine wave data value corresponding to the currently received address signal to the digital inverse converter 8.
The cosine wave data memory 36 receives the address signal output by the bit truncator 34, and outputs a cosine sampling data value corresponding to the currently received address signal to the digital inverse converter 8.
The carrier error extractor 37 receives the output signal of the digital inverse frequency converter 8, calculates a carrier error signal, and outputs the carrier error signal.
The adder 33 receives the digital frequency conversion orthogonal carrier frequency control word and the carrier error signal output by the carrier error extractor 37, adds the two received signals, and outputs the sum to the accumulator 32.
When the device works, the prepositive sampling frequency converter 1 carries out sampling frequency conversion processing on an input intermediate frequency analog modulation signal, specifically, the prepositive sampling frequency converter 1 sets parameters according to the carrier frequency of the input modulation signal and automatically adjusts the frequency of a sampling clock, so that the in-band new carrier frequency generated after the sampling clock and the carrier sampling frequency mixing of the intermediate frequency analog modulation signal is one fourth of the frequency of the sampling clock. The digital signal output by the pre-sampling frequency converter 1 is processed by a shunt mapping frequency converter 2 to generate two paths of orthogonal frequency mixing digital signals; the two paths of orthogonal frequency mixing digital signals are respectively processed by a low-pass filter 3-1 and a low-pass filter 3-2 to generate two paths of digital baseband signals carrying carrier errors. The two paths of digital baseband signals output by the low-pass filter 3-1 and the low-pass filter 3-2 are processed by a digital resampler 4, specifically, the digital resampler 4 automatically adjusts the internal resampling data rate according to the input modulation signal symbol rate setting parameter and the baseband signal output by a digital inverse frequency converter 8, and generates two paths of digital baseband signals sampled at double symbol rate. The two paths of digital baseband signals output by the digital resampler 4 are respectively subjected to matched filtering processing through a matched filter 5-1 and a matched filter 5-2. Output signals of the matched filter 5-1 and the matched filter 5-2 are respectively input into the digital forward frequency converter 6, and meanwhile, the single-control digital frequency conversion orthogonal carrier generator 7 generates two paths of orthogonal carrier signals according to digital frequency conversion orthogonal carrier frequency control words and inputs the two paths of orthogonal carrier signals into the digital forward frequency converter 6. The digital forward frequency converter 6 outputs two paths of digital baseband signals carrying stable forward carrier errors to the digital reverse frequency converter 8, and the double-control digital frequency conversion orthogonal carrier generator 9 automatically adjusts and generates two paths of orthogonal carrier signals according to the digital frequency conversion orthogonal carrier frequency control digital and the baseband signals output by the digital reverse frequency converter 8 and inputs the two paths of orthogonal carrier signals into the digital reverse frequency converter 8. Finally, the digital inverse frequency converter 8 outputs the digital baseband signal after coherent demodulation, so as to realize the multi-stage full digital frequency conversion demodulation based on digital resampling.
Compared with the traditional demodulation device, the invention adopts the intermediate frequency sampling all-digital signal processing flow and reasonably decomposes the demodulation process into the 4-level variable frequency processing process, thereby reducing the realization complexity of the demodulation device. In addition, due to the addition of the digital resampling unit, the data processing capacity of the digital signal is optimized in the whole demodulation processing process, the distribution of the digital filter is optimized, the logic resource required by software implementation is reduced, and the stability and the implementation efficiency of the demodulation device are improved. The invention can be applied to a data receiving subsystem of a satellite data ground receiving station and has stronger practical value.
Claims (7)
1. A multi-stage full-digital frequency conversion demodulation device based on digital resampling is characterized by comprising a pre-sampling frequency converter (1), a shunt mapping frequency converter (2), a first low-pass filter (3-1), a second low-pass filter (3-2), a digital resampler (4), a first matched filter (5-1), a second matched filter (5-2), a digital forward frequency converter (6), a single-control digital frequency conversion orthogonal carrier generator (7), a digital reverse frequency converter (8) and a double-control digital frequency conversion orthogonal carrier generator (9); wherein the content of the first and second substances,
the pre-sampling frequency converter (1) carries out sampling frequency conversion processing on an input intermediate frequency analog modulation signal and outputs a digital signal to the shunt mapping frequency converter (2); the method is characterized in that a pre-sampling frequency converter (1) sets parameters according to the carrier frequency of an input intermediate frequency analog modulation signal, automatically adjusts the frequency of a sampling clock, and enables the in-band new carrier frequency generated after sampling and mixing the sampling clock and the carrier frequency of the intermediate frequency analog modulation signal to be one fourth of the frequency of the sampling clock;
the shunt mapping frequency converter (2) processes the digital signals transmitted by the pre-sampling frequency converter (1) to generate two paths of orthogonal frequency mixing digital signals which are respectively transmitted to a first low-pass filter (3-1) and a second low-pass filter (3-2);
the first low-pass filter (3-1) and the second low-pass filter (3-2) respectively generate a digital baseband signal carrying a carrier error and transmit the digital baseband signal to the digital resampler (4);
the digital resampler (4) automatically adjusts the internal resampling data rate according to the externally input modulation signal symbol rate setting parameters and the baseband signal output by the digital inverse frequency converter (8), resamples two paths of digital baseband signals transmitted by the first low-pass filter (3-1) and the second low-pass filter (3-2), generates two paths of digital baseband signals sampled at double symbol rates, and respectively transmits the two paths of digital baseband signals to the first matched filter (5-1) and the second matched filter (5-2);
the first matched filter (5-1) and the second matched filter (5-2) carry out matched filtering processing on the input signal, and then the processed signal is transmitted to the digital forward frequency converter (6);
the single-control digital frequency conversion orthogonal carrier generator (7) generates two paths of orthogonal carrier signals according to an externally input digital frequency conversion orthogonal carrier frequency control word and inputs the two paths of orthogonal carrier signals to the digital forward frequency converter (6);
the digital forward frequency converter (6) outputs two paths of digital baseband signals carrying stable forward carrier errors to the digital backward frequency converter (8) according to signals input by the first matched filter (5-1) and the second matched filter (5-2) and the corresponding two paths of orthogonal carrier signals;
the double-control digital frequency conversion orthogonal carrier generator (9) controls the baseband signals output by the digital and digital inverse frequency converter (8) according to the digital frequency conversion orthogonal carrier frequency, automatically adjusts and generates two paths of orthogonal carrier signals and feeds the two paths of orthogonal carrier signals back to the digital inverse frequency converter (8);
and the digital inverse frequency converter (8) outputs a digital baseband signal after coherent demodulation according to the input signal of the digital forward frequency converter (6) and the feedback signal of the double-control digital frequency conversion orthogonal carrier generator (9), thereby completing the coherent demodulation of the analog intermediate frequency modulation signal.
2. The digital resampling based multi-stage all-digital frequency conversion demodulation device according to claim 1, wherein the shunt mapping frequency converter (2) comprises a serial-to-parallel converter (10), a first fixed coefficient mapper (11-1), a second fixed coefficient mapper (11-2), a third fixed coefficient mapper (11-3), a fourth fixed coefficient mapper (11-4), a fifth fixed coefficient mapper (11-5), a sixth fixed coefficient mapper (11-6), a seventh fixed coefficient mapper (11-7), an eighth fixed coefficient mapper (11-8), a first parallel-to-serial converter (12-1) and a second parallel-to-serial converter (12-2); wherein, the serial-parallel converter (10) converts the serial digital signal input from the pre-sampling frequency converter (1) into 4 paths of parallel digital signals, inputs the first path of parallel signals after conversion to a first fixed coefficient mapper (11-1) and a fifth fixed coefficient mapper (11-5), inputs the second path of parallel signals after conversion to a second fixed coefficient mapper (11-2) and a sixth fixed coefficient mapper (11-6), inputs the third path of parallel signals after conversion to a third fixed coefficient mapper (11-3) and a seventh fixed coefficient mapper (11-7), and inputs the fourth path of parallel signals after conversion to a fourth fixed coefficient mapper (11-4) and an eighth fixed coefficient mapper (11-8); a first fixed coefficient mapper (11-1) directly maps the input signal to 0 and outputs it; a second fixed coefficient mapper (11-2) directly maps the input signal to an output signal; a third fixed coefficient mapper (11-3) directly maps the input signal to 0 and outputs it; a fourth fixed coefficient mapper (11-4) directly maps the input signal to its own negative value and outputs it; a fifth fixed coefficient mapper (11-5) directly maps the input signal to an output signal; a sixth fixed coefficient mapper (11-6) directly maps the input signal to 0 and outputs it; a seventh fixed coefficient mapper (11-7) directly maps the input signal to its own negative value and outputs it; an eighth fixed coefficient mapper (11-8) directly maps the input signal to 0 and outputs it; the first parallel-serial converter (12-1) receives the output signals of the first fixed coefficient mapper (11-1), the second fixed coefficient mapper (11-2), the third fixed coefficient mapper (11-3) and the fourth fixed coefficient mapper (11-4) in sequence, converts the output signals into equivalent serial data and then transmits the equivalent serial data to the first low-pass filter (3-1); the second parallel-to-serial converter (12-2) receives the output signals of the fifth fixed coefficient mapper (11-5), the sixth fixed coefficient mapper (11-6), the seventh fixed coefficient mapper (11-7) and the eighth fixed coefficient mapper (11-8) in sequence, converts them into equivalent serial data, and then passes them to the second low pass filter (3-2).
3. The digital resampling based multi-stage all-digital frequency conversion demodulation device according to claim 1, wherein the digital resampler (4) comprises a first data buffer (13-1), a second data buffer (13-2), a data high bit truncator (14), a data low bit truncator (15), a first accumulator (16), a first data loop memory (17-1), a second data loop memory (17-2), a filter coefficient memory (18), a first weighted summator (19-1), a second weighted summator (19-2), a rate matcher (20) and a timing error extractor (21); the first data buffer (13-1) receives the digital signals output by the first low-pass filter (3-1), sequentially combines 3 adjacent input signals by taking the current input signal as a start to generate a combined signal with 4 input signals as a group, and outputs the combined signal to the first data circulating memory (17-1); the second data buffer (13-2) receives the digital signals output by the second low-pass filter (3-2), sequentially combines 3 adjacent input signals by taking the current input signal as a start to generate a combined signal with 4 input signals as a group, and outputs the combined signal to the second data circulating memory (17-2); the space addresses stored in the first data circulating memory (17-1) and the second data circulating memory (17-2) are in a circulating accumulation mode, so that the combined signals output by the first data buffer (13-1) and the second data buffer (13-2) respectively complete circulating storage; in addition, the second data buffer (13-2) also outputs a data accumulation buffer total amount data signal to the rate matcher (20); the first data cycle memory (17-1) and the second data cycle memory (17-2) respectively receive the data reading address transmitted by the data high-order bit interceptor (14) and output the stored combined signal corresponding to the currently received data reading address; the combined signals output by the first data cycle memory (17-1) and the second data cycle memory (17-2) are respectively transmitted to a first weighted summator (19-1) and a second weighted summator (19-2); the filter coefficient memory (18) receives the data reading address output by the data low-order bit interceptor (15) and outputs the filter combination coefficient corresponding to the currently received data reading address, and each group of output filter combination coefficients comprises 4 filter coefficients; the first weighted summator (19-1) receives the combined signal output by the first data cycle memory (17-1) and the filter combined coefficient output by the filter coefficient memory (18), sequentially takes 4 filter coefficients in the filter combined coefficient as weighted values of 4 data in the combined signal, completes the weighted summation operation of the filter combined coefficient and the combined signal, and outputs the result to the first matched filter (5-1); the second weighted summator (19-2) receives the combined signal output by the second data cycle memory (17-2) and the filter combined coefficient output by the filter coefficient memory (18), sequentially takes 4 filter coefficients in the filter combined coefficient as weighted values of 4 data in the combined signal, completes the weighted summation operation of the filter combined coefficient and the combined signal, and outputs the result to the second matched filter (5-2); a timing error extractor (21) receives the baseband signal output by the digital inverse frequency converter (8), generates a timing error signal and inputs the timing error signal into a first accumulator (16); the first accumulator (16) receives a timing error signal output by the timing error extractor (21) and a modulation signal symbol rate setting parameter input from the outside, combines the timing error signal and the modulation signal symbol rate setting parameter to be used as an iterative value to carry out accumulation calculation, generates address information and outputs the address information to the data high-order bit truncator (14) and the data low-order bit truncator (15), the first accumulator (16) simultaneously receives an address information output control signal output by the rate matcher (20), when the address information output control signal is valid, the first accumulator (16) internally carries out accumulation calculation to generate and output address information, and when the address information output control signal is invalid, the first accumulator (16) internally stops accumulation calculation and stops outputting the address information; the data high-order bit interceptor (14) receives the address information output by the first accumulator (16), intercepts and processes the high-order address information and respectively generates a data reading address and an address high-order accumulated total data signal, wherein the data reading address is respectively output to the first data circulating memory (17-1) and the second data circulating memory (17-2), and the address high-order accumulated total data signal is output to the rate matcher (20); the data low-order bit interceptor (15) receives the address information output by the first accumulator (16), intercepts the low-order address information and outputs the low-order address information to the filter coefficient memory (18); the rate matcher (20) receives a data accumulation buffer total amount data signal output by the second data buffer (13-2) and an address high-order accumulated total amount data signal output by the data high-order bit interceptor (14), compares the values of the two received paths of data, generates a control signal and outputs the control signal to the first accumulator (16).
4. The digital resampling based multi-stage full digital frequency conversion demodulation device according to claim 1, wherein the digital forward converter (6) comprises a first multiplier (22-1), a second multiplier (22-2), a third multiplier (22-3), a fourth multiplier (22-4), a first adder (23) and a first subtracter (24); the first multiplier (22-1) receives the output signal of the first matched filter (5-1) and the 1 st path of signal output by the single-control digital frequency conversion orthogonal carrier generator (7), multiplies the two paths of signals and outputs the multiplied signals to the first subtracter (24); the second multiplier (22-2) receives the output signal of the first matched filter (5-1) and the 2 nd path of signal output by the single-control digital frequency conversion orthogonal carrier generator (7), multiplies the two paths of signals and outputs the multiplied signals to the first adder (23); the third multiplier (22-3) receives the output signal of the second matched filter (5-2) and the 1 st path of signal output by the single-control digital frequency conversion orthogonal carrier generator (7), multiplies the two paths of signals and outputs the multiplied signals to the first adder (23); a fourth multiplier (22-4) receives the output signal of the second matched filter (5-2) and the 2 nd path of signal output by the single-control digital frequency conversion orthogonal carrier generator (7), multiplies the two paths of signals and outputs the multiplied signals to a first subtracter (24); the first adder (23) adds the two paths of received data and outputs the data to the digital inverse frequency converter (8); the first subtracter (24) subtracts the received output signal of the fourth multiplier (22-4) and the received output signal of the first multiplier (22-1) and outputs the result to the digital inverse frequency converter (8).
5. The digital resampling based multi-stage full digital frequency conversion demodulation device according to claim 1, wherein the digital inverse frequency converter (8) comprises a fifth multiplier (25-1), a sixth multiplier (25-2), a seventh multiplier (25-3), an eighth multiplier (25-4), a second subtractor (26) and a second adder (27); the fifth multiplier (25-1) receives the first path of signal output by the digital forward frequency converter (6) and the 1 st path of signal output by the double-control digital frequency conversion orthogonal carrier generator (9), multiplies the two paths of signals and outputs the multiplied signals to the second adder (27); a sixth multiplier (25-2) receives the first path of signal output by the digital forward frequency converter (6) and the 2 nd path of signal output by the double-control digital frequency conversion orthogonal carrier generator (9), multiplies the two paths of signals and outputs the multiplied signals to a second subtracter (26); a seventh multiplier (25-3) receives the second path of signals output by the digital forward frequency converter (6) and the 1 st path of signals output by the double-control digital frequency conversion orthogonal carrier generator (9), multiplies the two paths of signals and outputs the multiplied signals to a second subtracter (26); the eighth multiplier (25-4) receives the second path of signals output by the digital forward frequency converter (6) and the 2 nd path of signals output by the double-control digital frequency conversion orthogonal carrier generator (7), multiplies the two paths of signals and outputs the multiplied signals to the second adder (27); the second adder (27) adds the two received paths of data and outputs the data; and the second subtracter (26) subtracts the received output signal of the sixth multiplier (25-2) and the received output signal of the seventh multiplier (25-3) and outputs the result.
6. The digital resampling based multi-stage all-digital frequency conversion demodulation device according to claim 1, wherein the single-control digital frequency conversion quadrature carrier generator (7) comprises a second accumulator (28), a first bit truncator (29), a first sine wave data memory (30) and a first cosine wave data memory (31); the second accumulator (28) receives the digital frequency conversion orthogonal carrier frequency control word and takes the digital frequency conversion orthogonal carrier frequency control word as an accumulation stepping value to carry out accumulation operation, and the second accumulator (28) outputs the accumulation value to the first truncator (29); the first bit truncator (29) carries out bit truncating processing on the received accumulated value, generates and outputs an address signal; a first sine wave data memory (30) receives the address signal output by the first truncator (29) and outputs a sine wave data value corresponding to the currently received address signal to the digital forward frequency converter (6); the first cosine wave data memory (31) receives the address signal output by the first truncator (29) and outputs the cosine sampling data value corresponding to the currently received address signal to the digital forward converter (6).
7. The digital resampling based multi-stage all-digital frequency conversion demodulation device according to claim 1, wherein the dual-control digital frequency conversion quadrature carrier generator (9) comprises a third accumulator (32), a third adder (33), a second bit truncator (34), a second sine wave data memory (35), a second cosine wave data memory (36) and a carrier error extractor (37); the third accumulator (28) receives the signal output by the third adder (33) and performs accumulation operation as an accumulation stepping value, and the third accumulator (32) outputs the accumulation value to the second truncator (34); the second truncator (34) carries out truncation processing on the received accumulated value, generates and outputs an address signal; a second sine wave data memory (35) receives the address signal output by the second truncator (34) and outputs the sine wave data value corresponding to the currently received address signal to the digital inverse frequency converter (8); a second cosine wave data memory (36) receives the address signal output by the second truncator (34) and outputs a cosine sampling data value corresponding to the currently received address signal to the digital inverse frequency converter (8); a carrier error extractor (37) receives the output signal of the digital inverse frequency converter (8), calculates to obtain a carrier error signal and outputs the carrier error signal; the third adder (33) receives the digital frequency conversion orthogonal carrier frequency control word and the carrier error signal output by the carrier error extractor (37), adds the two received signals and outputs the sum to the third accumulator (32).
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