CN112349821A - Method for reducing dislocation and stress by using stacking faults, LED epitaxial wafer and application - Google Patents

Method for reducing dislocation and stress by using stacking faults, LED epitaxial wafer and application Download PDF

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CN112349821A
CN112349821A CN202011136251.4A CN202011136251A CN112349821A CN 112349821 A CN112349821 A CN 112349821A CN 202011136251 A CN202011136251 A CN 202011136251A CN 112349821 A CN112349821 A CN 112349821A
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gan
growing
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gan layer
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周圣军
唐斌
宫丽艳
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Wuhan University WHU
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Wuhan University WHU
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26Materials of the light emitting region
    • H01L33/30Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
    • H01L33/32Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005Processes
    • H01L33/0062Processes for devices with an active region comprising only III-V compounds
    • H01L33/0075Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/12Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/16Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular crystal structure or orientation, e.g. polycrystalline, amorphous or porous

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  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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Abstract

The invention discloses a method for reducing dislocation and stress by using stacking faults, an LED epitaxial wafer and application, and is suitable for the technical field of semiconductors. The LED epitaxial wafer structure grown by the method comprises a sapphire substrate, and a stacking fault inducing layer, an undoped GaN layer, an n-type GaN layer, a multi-quantum well layer, a p-type AlGaN layer and a p-type GaN layer which are sequentially grown from bottom to top. The invention utilizes the stacking fault inducing layer to form basal plane stacking faults in the undoped GaN material which is epitaxially grown, can make up for the mismatch of lattice constants of GaN and sapphire, thereby reducing the dislocation density and residual stress of the GaN epitaxial film, and is particularly suitable for constructing a high-indium-component InGaN/GaN multi-quantum well structure on the undoped GaN layer. Meanwhile, the method has the advantages of simplicity, feasibility, good repeatability and the like, and has great application value.

Description

Method for reducing dislocation and stress by using stacking faults, LED epitaxial wafer and application
Technical Field
The invention relates to the technical field of semiconductors, in particular to a method for reducing dislocation and stress by using stacking faults, an LED epitaxial wafer and application.
Background
The GaN-based LED device has the advantages of light weight, small volume, environmental protection, energy conservation, greenness, health, high reliability, long service life and the like. In addition, the light-emitting spectrum of the device can cover a wide range from ultraviolet to infrared, the monolithic integration of the three primary color light-emitting device is expected to be realized, and the device has important significance for developing high-resolution full-color display and illumination.
At present, the external quantum efficiency of commercial GaN-based blue LED devices has broken through 80%, but due to the lack of high-efficiency GaN-based LED devices in the longer emission band, high-efficiency full-color display and illumination based on group iii nitride has not been achieved. This is due to the requirement of InGaN/GaN quantum wells with higher In composition to build GaN-based LED devices with longer emission bands. On one hand, the non-radiative recombination problem caused by more serious defects exists In the InGaN/GaN quantum well with high In component; on the other hand, when InGaN/GaN quanta with high In components grow on the sapphire substrate, larger piezoelectric polarization electric field is generated due to larger difference of lattice constants, overlapping integral of wave functions of electrons and holes is reduced, and radiative recombination probability is reduced.
Disclosure of Invention
Aiming at the defects of the prior art, the invention aims to provide a method for reducing dislocation and stress by using stacking faults, an LED epitaxial wafer and application, wherein the dislocation density and residual stress in an epitaxial film are reduced by forming basal plane stacking faults through induction to make up the lattice constant mismatch between GaN and sapphire.
In order to achieve the purpose, the technical scheme of the invention is as follows:
in a first aspect, the present invention provides a method of reducing dislocation and stress using stacking faults, characterized by: namely, a method for reducing dislocation density and residual stress of GaN-based long wavelength LED epitaxial material by using stacking faults, comprising the following steps:
(1) growing a stacking fault inducing layer on the sapphire substrate;
(2) raising the temperature of the reaction chamber to a preset temperature;
(3) growing an undoped GaN layer on the stacking fault inducing layer;
(4) growing an n-type GaN layer on the undoped GaN layer;
(5) growing a multi-quantum well layer on the n-type GaN layer;
(6) growing a p-type AlGaN layer on the multi-quantum well layer;
(7) and growing a p-type GaN layer on the p-type AlGaN layer.
Preferably, in the step (1), the stacking fault inducing layer has a composite structure of AlN/GaN or AlN/AlGaN.
Furthermore, in the AlN/GaN or AlN/AlGaN composite structure, the growth mode of AlN is a physical vapor deposition method, and the thickness is 10-35 nm; the growth mode of GaN or AlGaN is MOCVD, the thickness is 7-15nm, and the growth temperature is 750-900 ℃.
Further, hydrogen and ammonia gas are continuously introduced into the reaction chamber during the process of raising the temperature of the reaction chamber to the preset temperature in the step (2).
Further, in the step (3), the undoped GaN layer is grown on the dislocation inducing layer at a high temperature of 1050-.
In a second aspect, the present invention further provides an LED epitaxial wafer, which is characterized in that: i.e. a dislocation density of about 1 x 107cm-2The long wavelength LED epitaxial wafer of (1), the structure comprises: the GaN-based multilayer structure comprises a sapphire substrate, and a stacking fault inducing layer, an undoped GaN layer, an n-type GaN layer, a multi-quantum well layer, a p-type AlGaN layer and a p-type GaN layer which are sequentially grown from bottom to top.
Preferably, the sapphire substrate, the stacking fault inducing layer and the undoped GaN layer form a structure with a gradually increasing lattice constant.
Further, a stacking fault band structure is formed at the interface of the stacking fault inducing layer and the undoped GaN layer. The structure can form basal plane stacking faults with the extension length of hundreds of nanometers at the interface of the stacking fault inducing layer and the undoped GaN layer, prevent dislocation from climbing upwards, and reduce the compressive stress in the upper layer structure.
Optionally, the sapphire substrate has a size of 2-8 inches;
optionally, the stacking fault inducing layer is an AlN/GaN or AlN/AlGaN composite structure.
In a third aspect, the present invention also provides undoped GaN grown according to the above method and its use in the manufacture of semiconductor optoelectronic and microelectronic devices.
Compared with the prior art, the invention has the following advantages and beneficial effects:
according to the invention, the structure with the gradually changed lattice constant of the sapphire/the stacking fault inducing layer/the undoped GaN layer is formed by introducing the stacking fault inducing layer, so that basal plane stacking faults with the extension length of hundreds of nanometers are formed at the interface of the stacking fault inducing layer and the undoped GaN layer, the lattice constant mismatch of GaN and sapphire can be effectively compensated, and the dislocation density and the residual stress in the LED epitaxial film are reduced.
Drawings
Fig. 1 is a schematic structural diagram of a long wavelength LED epitaxial wafer according to an embodiment of the present invention;
FIG. 2 is a transmission electron microscope photograph of a cross section of an LED epitaxial wafer without a induced stacking fault layer according to example 1 of the present invention;
FIG. 3 is a transmission electron microscope photograph of a cross section of an LED epitaxial wafer with a stacking fault inducing layer according to embodiment 1 of the present invention;
fig. 4 is a raman scattering spectrum of an LED epitaxial wafer according to embodiment 1 of the present invention;
FIG. 5 is an XRD rocking curve diagram of (102) crystal plane of an LED epitaxial wafer provided in example 1 of the present invention;
fig. 6 is an electroluminescence spectrum of an LED epitaxial wafer according to embodiment 1 of the present invention.
In the figure: 101-a sapphire substrate; 102-a stacking fault inducing layer; 103-undoped GaN layer; a 104-n type GaN layer; 105-a MQW layer; a 106-p type AlGaN layer; 107-p type GaN layer.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in further detail with reference to examples.
Example 1
1) Selecting a c-plane sapphire substrate, putting the c-plane sapphire substrate into a magnetron sputtering reaction chamber, wherein the target material is high-purity Al, the reaction gas is nitrogen, the carrier gas is argon, and the AlN deposition thickness is 25 nm;
2) putting the mixture into an MOCVD reaction chamber, introducing ammonia gas and trimethyl gallium, and growing GaN with the thickness of 15nm at 800 ℃;
3) introducing hydrogen and ammonia gas, and heating to 1150 ℃;
4) growing an undoped GaN layer with the thickness of 3 mu m on the stacking fault inducing layer;
5) cooling to 1100 deg.c to grow 2 micron thick n-type GaN layer on un-doped GaN;
6) and (3) growing a multi-quantum well layer with 9 periods on the n-type GaN, wherein the GaN barrier layer: thickness 15nm, growth temperature 850 ℃, InGaN well layer: the thickness is 3nm, and the growth temperature is 700 ℃;
7) heating to 950 ℃, and growing a p-type AlGaN layer with the thickness of 30nm on the multiple quantum wells;
8) a p-type GaN layer with the thickness of 150nm is grown on the p-type AlGaN layer at 900 ℃;
9) and cooling to room temperature to finish the growth.
Example 2
1) Selecting a c-plane sapphire substrate, putting the c-plane sapphire substrate into a magnetron sputtering reaction chamber, wherein the target material is high-purity Al, the reaction gas is nitrogen, the carrier gas is argon, and the AlN deposition thickness is 20 nm;
2) placing into MOCVD reaction chamber, introducing ammonia gas, trimethyl gallium and trimethyl aluminum, and growing 10nm thick Al at 900 deg.C0.2Ga0.8N;
3) Introducing hydrogen and ammonia gas, and heating to 1150 ℃;
4) introducing ammonia gas and trimethyl gallium, and growing an undoped GaN layer with the thickness of 3 mu m;
5) cooling to 1100 deg.c to grow 2.5 micron thick n-type GaN layer on un-doped GaN;
6) and growing a multi-quantum well layer with 8 periods on the n-type GaN, wherein the GaN barrier layer comprises the following components: thickness of 13.5nm, growth temperature of 850 ℃, InGaN well layer: the thickness is 3.5nm, and the growth temperature is 700 ℃;
7) heating to 950 ℃, and growing a p-type AlGaN layer with the thickness of 30nm on the multiple quantum wells;
8) a p-type GaN layer with the thickness of 150nm is grown on the p-type AlGaN layer at 900 ℃;
9) and cooling to room temperature to finish the growth.
The inventionIn the embodiment, the stacking fault inducing layer is introduced to form a structure with a lattice constant gradually changing between the sapphire/stacking fault inducing layer/undoped GaN layer, and basal plane stacking faults with the extension length reaching hundreds of nanometers are formed at the interface of the stacking fault inducing layer and the undoped GaN layer, so that the lattice constant mismatch between the GaN and the sapphire is effectively compensated, and the dislocation density and the residual stress of the LED epitaxial wafer are reduced. The Raman test result shows that the epitaxial wafer E with the layer fault inducing layer2(high) mode Raman Peak vs. unstrained GaN bulk substrate (Peak position 566.65 cm)-1) Red-shifted and frequency-shifted by 2.05cm-1Epitaxial wafer E without induced stacking faults2(high) mode Raman peak red-shifted and frequency-shifted to 3.99cm relative to unstrained GaN bulk substrate-1Therefore, the compressive stress of the epitaxial wafer with the induced layer of the stacking fault is obviously smaller than that of the epitaxial wafer without the induced layer of the stacking fault; XRD test results show that the full width at half maximum of a crystal plane rocking curve of the epitaxial wafer (102) with the stacking fault induction layer is 192arcsec, the full width at half maximum of a crystal plane rocking curve of the epitaxial wafer (102) without the stacking fault induction layer is 282arcsec, and the epitaxial wafer with the stacking fault induction layer has lower dislocation density; the electroluminescence test result shows that when the injection current is 30mA, the luminous intensity of the epitaxial wafer with the induced stacking fault layer is about 1.2 times higher than that of the epitaxial wafer without the induced stacking fault layer.

Claims (10)

1. A method of reducing dislocation and stress using stacking faults, characterized by: the method comprises the following steps:
(1) growing a stacking fault inducing layer (102) on a sapphire substrate (101);
(2) raising the temperature of the reaction chamber to a preset temperature;
(3) growing an undoped GaN layer (103) on the stacking fault inducing layer (102);
(4) growing an n-type GaN layer (104) on the undoped GaN layer (103);
(5) growing a multiple quantum well layer (105) on the n-type GaN layer (104);
(6) growing a p-type AlGaN layer (106) on the MQW layer (105);
(7) growing a p-type GaN layer (107) on the p-type AlGaN layer (106).
2. The method of utilizing stacking faults to reduce dislocations and stress as claimed in claim 1, wherein: in the step (1), the stacking fault inducing layer (102) is of an AlN/GaN or AlN/AlGaN composite structure.
3. A method of reducing dislocations and stress using stacking faults as claimed in claim 2, wherein: in the AlN/GaN or AlN/AlGaN composite structure, the growth mode of AlN is a physical vapor deposition method, and the thickness is 10-35 nm; the growth mode of GaN or AlGaN is MOCVD, the thickness is 7-15nm, and the growth temperature is 750-900 ℃.
4. A method for reducing dislocations and stress using stacking faults according to any one of claims 1 to 3, wherein: and (3) introducing hydrogen and ammonia gas into the reaction cavity all the time in the process of raising the temperature of the reaction cavity to the preset temperature in the step (2).
5. A method for reducing dislocations and stress using stacking faults according to any one of claims 1 to 3, wherein: growing the undoped GaN layer (103) on the dislocation inducing layer (102) at a high temperature in the step (3), wherein the growth temperature is 1050-.
6. The method of utilizing stacking faults to reduce dislocations and stress according to claim 4, wherein: growing the undoped GaN layer (103) on the dislocation inducing layer (102) at a high temperature in the step (3), wherein the growth temperature is 1050-.
7. An LED epitaxial wafer is characterized in that: the method according to any one of claims 1 to 6, having a structure comprising a sapphire substrate (101) and a stacking fault inducing layer (102), an undoped GaN layer (103), an n-type GaN layer (104), a multi-quantum well layer (105), a p-type AlGaN layer (106), and a p-type GaN layer (107) grown in this order from bottom to top.
8. The LED epitaxial wafer of claim 7, wherein: the sapphire substrate (101), the stacking fault inducing layer (102) and the undoped GaN layer (103) form a structure with gradually increasing lattice constants.
9. The LED epitaxial wafer of claim 7 or 8, wherein: a stacking fault band structure is formed at the interface between the stacking fault inducing layer (102) and the undoped GaN layer (103).
10. Use of undoped GaN in the manufacture of semiconductor optoelectronic and microelectronic devices, characterized by: the undoped GaN is grown according to the method of any of claims 1 to 6.
CN202011136251.4A 2020-10-22 2020-10-22 Method for reducing dislocation and stress by using stacking faults, LED epitaxial wafer and application Pending CN112349821A (en)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104393125A (en) * 2014-12-17 2015-03-04 安徽三安光电有限公司 Method for preparing light emitting element
CN108346725A (en) * 2017-12-29 2018-07-31 华灿光电(苏州)有限公司 A kind of gallium nitride based LED epitaxial slice and its manufacturing method
CN109300855A (en) * 2018-10-17 2019-02-01 湘能华磊光电股份有限公司 Improve the LED epitaxial growth method of growth quality
CN110739373A (en) * 2019-10-21 2020-01-31 武汉大学 Light emitting diode chip with composite nucleation layer and preparation method thereof
CN111180564A (en) * 2020-02-14 2020-05-19 福建兆元光电有限公司 High-luminous-efficiency green light LED epitaxial wafer and manufacturing method thereof

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104393125A (en) * 2014-12-17 2015-03-04 安徽三安光电有限公司 Method for preparing light emitting element
CN108346725A (en) * 2017-12-29 2018-07-31 华灿光电(苏州)有限公司 A kind of gallium nitride based LED epitaxial slice and its manufacturing method
CN109300855A (en) * 2018-10-17 2019-02-01 湘能华磊光电股份有限公司 Improve the LED epitaxial growth method of growth quality
CN110739373A (en) * 2019-10-21 2020-01-31 武汉大学 Light emitting diode chip with composite nucleation layer and preparation method thereof
CN111180564A (en) * 2020-02-14 2020-05-19 福建兆元光电有限公司 High-luminous-efficiency green light LED epitaxial wafer and manufacturing method thereof

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