CN112349687B - Six-layer wiring arbitrary-layer interconnection LCP (liquid Crystal display) packaging substrate, manufacturing method and multi-chip system-level packaging structure - Google Patents

Six-layer wiring arbitrary-layer interconnection LCP (liquid Crystal display) packaging substrate, manufacturing method and multi-chip system-level packaging structure Download PDF

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CN112349687B
CN112349687B CN202011038836.2A CN202011038836A CN112349687B CN 112349687 B CN112349687 B CN 112349687B CN 202011038836 A CN202011038836 A CN 202011038836A CN 112349687 B CN112349687 B CN 112349687B
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lcp
layer
patterned metal
substrate
metal circuit
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CN112349687A (en
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戴广乾
徐诺心
曾策
边方胜
易明生
廖翱
龚小林
高阳
舒攀林
徐榕青
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CETC 29 Research Institute
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H01L23/49894—Materials of the insulating layers or coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/09—Use of materials for the conductive, e.g. metallic pattern

Abstract

The invention discloses a six-layer wiring arbitrary layer interconnection LCP packaging substrate, a manufacturing method and a multi-chip system level packaging structure, wherein the LCP packaging substrate comprises: 6 patterned metal circuit layers distributed from the surface to the bottom, wherein at least one edge of the outermost periphery of the first patterned metal circuit layer is distributed with bonding pads or patterns for external secondary cascade I/O (input/output) welding of the LCP packaging substrate; 5 insulating medium layers positioned between adjacent patterned metal circuit layers; a plurality of blind grooves which are positioned in the insulating medium layer between the first patterned metal circuit layer and the second patterned metal circuit layer and are opened towards the first patterned metal circuit layer; and a plurality of blind holes penetrating and connecting the adjacent patterned metal circuit layers. The LCP packaging substrate of the airtight packaging structure can meet the system-level packaging requirements of multiple chips, high airtight requirements, high electromagnetic shielding and high reliable interconnection.

Description

Six-layer wiring arbitrary-layer interconnection LCP (liquid Crystal display) packaging substrate, manufacturing method and multi-chip system-level packaging structure
Technical Field
The invention relates to the technical field of integrated circuits and chip packaging, in particular to a six-layer wiring arbitrary layer interconnection LCP packaging substrate, a manufacturing method and a multi-chip system level packaging structure, which are used for high-reliability system level packaging for high-frequency applications such as radio frequency, microwave, millimeter wave and the like.
Background
With the advancement of semiconductor and integrated circuit technologies, the requirements of system integration are further improved, and the current electronic circuit design and manufacture are both developed towards smaller size and higher integration density, so that considerable work is performed in the field of multi-chip packaging. In an advanced package form, a plurality of Radio Frequency (RF) chips, digital Integrated Circuit (IC) chips, micro chip type components, and the like are assembled on a package substrate by SIP technology and then integrated into one package body. The multi-chip packaging form shortens the pin distance between chips, greatly improves the packaging density and can meet the requirements of system-in-package to a certain extent.
The packaging modes can be generally divided into two types according to different packaging substrate materials: one is a multilayer ceramic package having a cavity structure, and the other is a plastic package using a multilayer PCB substrate as a chip substrate material.
The ceramic package substrate has the advantages of high integration density, high reliability, high air tightness, high heat conductivity, excellent corrosion resistance and the like. However, due to the thermal mismatch between the ceramic material and the PCB material, large-size package cannot be performed, and meanwhile, the ceramic package has the problem of extremely high manufacturing cost.
The plastic packaging substrate has the characteristics of low cost, relatively simple process and higher interconnection density, and can realize secondary high-density interconnection with the PCB motherboard in the form of BGA and the like. The biggest defect is that the common PCB material has high moisture absorption rate and poor water vapor blocking performance, and can not realize airtight packaging; meanwhile, the dielectric properties (dielectric constant and dielectric loss) of the common resin material are limited, and the resin material cannot be applied to radio frequency/microwave transmission. These deficiencies limit the application of plastic packages in high reliability, high performance chip packages, whose main field of application is consumer electronics today.
The Liquid Crystal Polymer (LCP) material has the outstanding advantages of excellent dielectric transmission characteristics, extremely low moisture absorption rate, water permeability and oxygen permeability, planar thermal expansion coefficient matched with copper, high heat resistance, chemical corrosion resistance and the like, meets the severe requirements of a radio frequency/microwave chip on a packaging substrate material, and is a new generation of substrate material with high reliability, high performance, huge potential in the chip packaging application field and wide application prospect.
Chinese patent CN106486427A, CN206259334U discloses a packaging case based on LCP substrate and a preparation method, wherein the LCP substrate is used as a substrate layer for mounting a chip, and technologies such as chip assembly, metal enclosure, and cover plate welding are used as auxiliary materials, so as to provide a solution for airtight packaging of the chip. In this package form, a specific structure and a manufacturing method as a package substrate are not given; the packaging form lacks an external interconnection interface, so that the secondary cascade of the packaging body cannot be realized; the LCP substrate does not have the characteristic of circuit partition, cannot provide a good electromagnetic shielding basis for a multi-chip complex system, and the problem of circuit crosstalk is difficult to avoid.
Chinese patent CN102593077a discloses a liquid crystal polymer packaging structure, which is a structure for airtight packaging of chips formed by combining a high melting point LCP composite cover plate and a low melting point LCP tube shell by hot melting. The package structure is too simple and does not relate to specific structural features and implementation methods of the substrate.
Chinese patent CN104282632B discloses a packaging case based on LCP substrate and a method for preparing the same, which uses LCP multilayer substrate as carrier to hermetically package chips. The LCP packaging substrate structure is divided into a surface sealing layer, a chip mounting layer, a welding layer, an interconnection layer and the like, and each component structure characteristic is limited. In the substrate structure, the holes of the circuit interconnection layer are positioned at the periphery of the chip sealing area, and the periphery of the chip is non-airtight due to the existence of the through holes; the surface layer is defined as a sealing area, and is designed separately from the inner bonding layer, and is electrically disconnected or only connected with the ground. The disclosed implementation method adopts a mode of multi-lamination and hot pressing. The LCP adhesive film material is thermoplastic in nature and theoretically cannot be laminated multiple times, so the process of this construction is very difficult and impractical to achieve.
Chinese patent CN107324273B discloses a packaging method for MEMS devices based on LCP multilayer stacking technology, in which a cap for MEMS devices is prepared by multilayer LCP stacking lamination, and LCP materials are directly applied to plastic packaging of single chips. In the invention, the LCP material only plays a role of a packaging cap, and the application field does not relate to a packaging substrate, and wiring design cannot be performed.
Chinese patent CN102683220B discloses a method for fabricating a multi-layer organic liquid crystal polymer substrate structure, in which active and passive devices can be embedded into the multi-layer liquid crystal polymer substrate simultaneously, so as to achieve hermetic packaging of the chip. The active device with the salient points is connected to the LCP substrate by using a flip-chip bonding technology, then the LCP adhesive film is windowed, laminated and finally interconnected through a metalized through hole, and finally the packaging structure is formed. The packaging structure adopts a manufacturing route of the chip embedded substrate, is mainly oriented to single-chip packaging, and is not applicable to multi-chip packaging application with high electromagnetic shielding requirements; the interconnection holes of the substrate are manufactured through one-time drilling metallization, the interconnection function of the substrate is simple, and the complex interconnection requirements of the multi-chip package cannot be met.
Chinese patent CN106252339B discloses a high-density radio frequency multi-chip package structure, which uses a multi-layer substrate and a housing as a carrier, and stacks a plurality of chips and devices in a vertical direction for three-dimensional high-density hybrid integration. The multi-chip package is essentially mixed integration in a multi-chip package body, has limited electromagnetic shielding performance, relates to multi-temperature gradient and solder selection, and has difficult process realization.
Chinese patent CN103165479B discloses a method for manufacturing a multi-chip system-in-package structure, in which a plurality of chips are integrated on an interposer in a manner of vertically stacking the multi-chips to form a system-in-package structure. The structure is suitable for high-density integration of the IC chip, but is not suitable for electromagnetic shielding requirements of multiple radio frequency chips.
Chinese patent CN103930989B discloses a radio frequency package on package circuit, which forms a two-level package of a radio frequency package on package (PoP) circuit by vertical stacking of two radio frequency packages. The structure package body does not relate to the electromagnetic shielding problem of the chip in the single package body in detail, and the substrate has simple function and is not described in detail in the aspect of the substrate structure.
U.S. patent No. 2019/0080817Al discloses a manufacturing method of an LCP resin multilayer substrate, which can improve flatness and avoid manufacturing problems such as warping caused by glue shortage by using special LCP paste as an adhesive layer and a thickness adjusting layer of the LCP multilayer substrate. The interconnected holes of the substrate structure are filled with the conductive paste, and the substrate manufactured by the method cannot bear high-temperature application occasions because the adhesive component of the conductive paste volatilizes at high temperature to cause the risk of substrate delamination, bubbling and even board explosion. And the adhesion of the LCP paste to the LCP layer, the LCP paste to the conductive paste, is much poorer theoretically than in conventional LCP adhesive film lamination methods. The multilayer LCP substrate manufactured in this way is not suitable for radio frequency chip packaging applications with high interconnect hole reliability.
The prior art has not realized a technical solution for realizing a packaging substrate and a system-in-package structure which meet the requirements of system-in-package of multiple chips, high air tightness, high electromagnetic shielding and high reliability interconnection by using LCP.
Disclosure of Invention
The technical problems to be solved by the invention are as follows: aiming at the problems, the invention provides a six-layer wiring arbitrary layer interconnection LCP packaging substrate, a manufacturing method and a multi-chip system-in-package structure based on the substrate, so as to meet the system-in-package requirements of multi-chip, high air tightness, high electromagnetic shielding and high reliability interconnection.
The invention provides a six-layer wiring arbitrary layer interconnection LCP packaging substrate, which comprises:
the 6 patterned metal circuit layers are distributed from the surface to the bottom and sequentially comprise a first patterned metal circuit layer, a second patterned metal circuit layer, a third patterned metal circuit layer, a fourth patterned metal circuit layer, a fifth patterned metal circuit layer and a sixth patterned metal circuit layer; at least one edge of the outermost periphery of the first patterned metal circuit layer is distributed with bonding pads or patterns for external secondary cascade I/O (input/output) welding of the LCP packaging substrate;
5 insulating medium layers positioned between adjacent patterned metal circuit layers;
a plurality of blind grooves which are positioned in the insulating medium layer between the first patterned metal circuit layer and the second patterned metal circuit layer and are opened towards the first patterned metal circuit layer;
and a plurality of blind holes penetrating and connecting the adjacent patterned metal circuit layers, wherein a plurality of blind holes are distributed on the bonding pad or pattern for the external secondary cascade I/O welding.
Further, the first patterned metal circuit layer comprises a bonding pad or a pattern for external secondary cascade connection I/O (input/output) at the outermost periphery, an inner surrounding metal layer and a plurality of groups of chip I/O welding and signal transmission circuit layers at the inner side of the surrounding metal layer, wherein each group of chip I/O welding and signal transmission circuit layers is in a rectangular or irregularly-shaped island shape, and each group of chip I/O welding and signal transmission circuit layers is connected with the surrounding metal layer through an electric insulation area; the electrical property of the surrounding metal layer is a grounding layer, and the technological property is an airtight welding layer; the upper surface of the first patterned metal circuit layer is sequentially provided with a coating layer and an upper surface solder resist layer; the coating layer covers the bonding pad or graph for external secondary cascade I/O welding, the surrounding metal layer and each group of chip I/O welding and signal transmission line layers; the upper surface solder mask comprises a first surrounding solder mask layer and a plurality of second surrounding solder mask layers, wherein each second surrounding solder mask layer correspondingly surrounds each electric insulation area, and the first surrounding solder mask layer surrounds all the second surrounding solder mask layers;
Each group of chip I/O welding and signal transmission line layers comprises a chip I/O welding pad, a signal transmission line and one or more blind grooves; the transmission of signals in each group of chip I/O welding and signal transmission circuit layers is completed jointly through the chip I/O welding and signal transmission circuit in each group of chip I/O welding and signal transmission circuit layers or through corresponding parts in each layer of blind holes and the lower layer of patterned metal circuit layers; the signal transmission between two or more groups of chip I/O welding and signal transmission layers and between a plurality of groups of chip I/O welding and signal transmission layers and an external secondary cascade I/O welding pad or pattern is completed by blind holes of each layer and corresponding parts in the lower patterned metal circuit layer.
Further, insulating medium layers positioned between the second patterned metal circuit layer and the third patterned metal circuit layer, between the third patterned metal circuit layer and the fourth patterned metal circuit layer and between the fourth patterned metal circuit layer and the fifth patterned metal circuit layer are formed by LCP substrates; the insulating medium layer is positioned between the first patterned metal circuit layer and the second patterned metal circuit layer and between the fifth patterned metal circuit layer and the sixth patterned metal circuit layer and consists of an LCP substrate and an LCP bonding film; the melting point of the LCP adhesive film is 10-60 ℃ lower than that of the LCP substrate.
Further, the bottom of the blind groove is a large-area metal grounding layer of a second patterned metal circuit layer and is provided with a coating layer; the blind groove is a chip I/O pad or pattern around the opening of the first patterned metal circuit layer; the number and the size of the blind slots are determined according to the number and the size of the mounted chips.
Further, all blind holes can be aligned or staggered and stacked in the vertical direction, so that the requirement of interconnection of any layer in the 6 layers of patterned metal circuit layers can be met; the diameter of each blind hole is the same, the depth-diameter ratio of the blind holes is less than or equal to 1, and the blind holes are filled with solid electroplated copper.
Further, the technological property and the electrical property of the sixth patterned metal circuit layer are large-area metal stratum.
The invention also provides a manufacturing method of the LCP packaging substrate with any interconnection layers of six layers of wiring, which is used for manufacturing the LCP packaging substrate and comprises the following steps:
s1, laser drilling blind holes on a double-sided copper-clad LCP substrate to form third blind holes penetrating through and connecting a third patterned metal circuit layer and a fourth patterned metal circuit layer;
s2, metallizing the blind holes to form third blind holes filled with solid electroplated copper;
S3, manufacturing a third patterned metal circuit layer and a fourth patterned metal circuit layer on the upper surface and the lower surface of the double-sided copper-clad LCP substrate;
s4, taking a second single-sided copper-clad LCP substrate and a third single-sided copper-clad LCP substrate
Then, aligning and laminating the second single-sided copper-clad LCP substrate, the double-sided copper-clad LCP substrate treated by the S3 and the third single-sided copper-clad LCP substrate from top to bottom under the high-temperature high-pressure vacuumizing condition, and then pressing to form four layers of wiring LCP substrates; wherein the copper-clad surface of the second single-sided copper-clad LCP substrate faces upwards, and the copper-clad surface of the third single-sided copper-clad LCP substrate faces downwards;
s5, laser drilling blind holes on a second single-sided copper-clad LCP substrate and a third single-sided copper-clad LCP substrate of the four-layer wiring LCP substrate, and respectively forming second type blind holes penetrating and connecting a second patterned metal circuit layer and a third patterned metal circuit layer and fourth type blind holes penetrating and connecting a fourth patterned metal circuit layer and a fifth patterned metal circuit layer;
s6, metallizing the blind holes to form second-type blind holes and fourth-type blind holes filled with solid electroplated copper;
s7, respectively manufacturing a second patterned metal circuit layer and a fifth patterned metal circuit layer on the upper surface of a second single-sided copper-clad LCP substrate and the lower surface of a third single-sided copper-clad LCP substrate of the four-layer wiring LCP substrate;
S8, taking a first single-sided copper-clad LCP substrate, a fourth single-sided copper-clad LCP substrate, a first LCP bonding film and a second LCP bonding film, and then laminating the first single-sided copper-clad LCP substrate, the first LCP bonding film, the four-layer wiring LCP substrate treated in the S7, the second LCP bonding film and the fourth single-sided copper-clad LCP substrate in the order from top to bottom, and then laminating the six-layer wiring LCP substrate; wherein the first single-sided copper-clad LCP substrate faces upwards, and the copper-clad surface of the fourth single-sided copper-clad LCP substrate faces downwards; the melting point of the first LCP bonding film and the second LCP bonding film is lower than that of the first single-sided copper-clad LCP substrate, the second single-sided copper-clad LCP substrate, the double-sided copper-clad LCP substrate, the third single-sided copper-clad LCP substrate and the fourth single-sided copper-clad LCP substrate;
s9, laser drilling blind holes on a first single-sided copper-clad LCP substrate and a fourth single-sided copper-clad LCP substrate of the six-layer wiring LCP substrate, and respectively forming a first type blind hole penetrating and connecting a first patterned metal circuit layer and a second patterned metal circuit layer and a fifth type blind hole penetrating and connecting a fifth patterned metal circuit layer and a sixth patterned metal circuit layer;
s10, metallizing blind holes to form first type blind holes and fifth type blind holes filled with solid electroplated copper;
S11, manufacturing a first patterned metal circuit layer on the upper surface of a first single-sided copper-clad LCP substrate of the six-layer wiring LCP substrate, and manufacturing a sixth patterned metal circuit layer on the lower surface of a fourth single-sided copper-clad LCP substrate; copper in a blind groove slotting area in the first patterned metal circuit layer is removed;
s12, grooving the blind groove grooving area by adopting a laser processing means to form a blind groove for installing a chip, and decontaminating the bottom and the side wall of the blind groove;
s13, manufacturing a coating layer on the first patterned metal circuit layer and the bottom of the blind groove, and manufacturing an upper surface solder mask layer on the coating layer of the corresponding part to obtain an LCP packaging substrate;
and S14, if the LCP packaging substrate is manufactured in a spliced form through steps S1 to S13, milling the LCP packaging substrate manufactured in the spliced form to form a single LCP packaging substrate.
Further, the depth-diameter ratio of the blind holes is less than or equal to 1.
Further, the melting points of the first LCP adhesive film and the second LCP adhesive film are 10 to 60 ℃ lower than the melting points of the first single-sided copper-clad LCP substrate, the second single-sided copper-clad LCP substrate, the double-sided copper-clad LCP substrate, the third single-sided copper-clad LCP substrate, and the fourth single-sided copper-clad LCP substrate.
The invention also provides a multi-chip system-in-package structure, comprising: the LCP packaging substrate, the chip, the metal surrounding frame and the metal cover plate;
the multi-chip system level packaging structure is fixed on a PCB motherboard in a conductive adhesive bonding or welding mode, and a bonding pad or a graph for external secondary cascade I/O welding on the LCP packaging substrate is used as an external secondary cascade I/O interface of the multi-chip system level packaging structure;
the metal surrounding frame is internally provided with metal separation ribs; the metal surrounding frame and the metal separating ribs are welded on the upper surface of the LCP packaging substrate, the bonding pad or the pattern for external secondary cascade I/O welding is arranged outside the metal surrounding frame, the metal cover plate is welded on the metal surrounding frame and the metal separating ribs, and a plurality of cavity structures with airtight packaging performance and electromagnetic shielding performance are formed between the LCP packaging substrate and the metal cover plate through the metal surrounding frame and the metal separating ribs; each cavity structure comprises one or more blind grooves; each blind groove is used for installing a chip, when the installed chip has no electromagnetic shielding requirement, the blind grooves are installed in the same cavity structure, and when the installed chip has the electromagnetic shielding requirement, the blind grooves are installed in different cavity structures; the chip is adhered to the blind groove through conductive adhesive, and is electrically interconnected with the chip I/O welding and signal transmission circuit layer in the first patterned metal circuit layer in a gold wire bonding mode.
In summary, due to the adoption of the technical scheme, the beneficial effects of the invention are as follows:
1. the invention realizes the all-LCP material system packaging substrate for multi-chip airtight packaging by utilizing the excellent high-frequency transmission characteristic, extremely low moisture absorption and water permeability and oxygen permeability of the Liquid Crystal Polymer (LCP) material.
2. The packaging substrate is based on an all-first-order basic interconnection blind hole structural design, can realize any layer interconnection wiring of 6 layers of pattern lines, contains a plurality of blind slots for chip installation, and is matched with the design of electromagnetic compatibility and process compatibility of the surface layer lines of the substrate, so that the packaging substrate can meet the requirements of multi-chip, high electromagnetic shielding and high-reliability system-level packaging.
3. When preparing any interconnection substrate of 6 layers of wiring by a lamination method, two lamination processes are needed, and the LCP adhesive film material is thermoplastic and cannot be laminated for multiple times theoretically. According to the 6-layer wiring LCP packaging substrate, the 3 layers of high-melting-point LCP substrates are directly subjected to high-temperature fusion lamination in the first step, and the substrates are laminated with the low-melting-point LCP adhesive films in the second step to form a lamination temperature gradient, so that the risk of deformation failure of the LCP adhesive films after secondary lamination is effectively avoided.
4. The multi-chip system level packaging structure realized by adopting the packaging substrate is fixed on a PCB motherboard in a conductive adhesive bonding or welding mode, and is used as a secondary cascade I/O interface of the multi-chip system level packaging structure to the outside by using a bonding pad or a pattern for external secondary cascade I/O welding positioned at the outermost periphery of the packaging substrate, has good compatibility with the PCB motherboard, is simple to package and use, has high assembly efficiency, and can be used for carrying out system level packaging with large size and high integration density.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic view showing the structure of an LCP package substrate according to embodiment 1 of the present invention;
wherein: 1-LCP package substrate; 11-patterning the metal circuit layer; 111-a first patterned metal circuit layer; 112-a second patterned metal circuit layer; 113-a third patterned metal line layer; 114-fourth patterned metal circuit layer; 115-fifth layer patterning metal line layer; 116-sixth patterned metal circuit layers; 12-blind groove; 13-coating layer; 14-blind holes; 141-first class blind holes; 142-second class blind holes; 143-third class blind holes; 144-fourth class of blind holes; 145-a fifth class of blind holes; 15-an insulating medium layer; 151-a first single sided copper clad LCP substrate; 152-a first LCP adhesive film; 153-a second single sided copper clad LCP substrate; 154-double-sided copper-clad LCP substrate; 155-a third single sided copper clad LCP substrate; 156-a second LCP adhesive film; 157-fourth single sided copper-clad LCP substrate; 16-an intra-substrate signal transmission path; 17-upper surface solder mask; 1111-pads or graphics for external secondary cascaded I/O bonding.
FIG. 2 is a schematic diagram of a first patterned metal circuit layer according to embodiment 1 of the present invention;
wherein, 21, 22, 23-chip I/O welding and signal transmission line layer; 211. 221, 231-chip mounting blind slot positions; 212. 222, 232 chip I/O pads and signal transmission lines; 213. 223, 233-electrically insulating regions; 171. 172, 173-a second surrounding solder mask; 24-surrounding the metal layer; 174-a first surrounding solder mask; 16-an intra-substrate signal transmission path; 1111-pads or graphics for external secondary cascaded I/O bonding.
Fig. 3 is a flow chart of a method for manufacturing an LCP package substrate of embodiment 2 of the present invention.
Fig. 4a to 4o are schematic structural views showing the steps in the flow of the LCP package substrate manufacturing method according to embodiment 2 of the present invention:
FIG. 4a is a schematic diagram of a laser drilling blind holes on a double-sided copper-clad LCP substrate to form a third type of blind holes;
FIG. 4b is a schematic view of a third type of blind via metallization;
FIG. 4c is a schematic diagram of the structure after the third and fourth patterned metal circuit layers are fabricated;
FIG. 4d is a schematic diagram of the structure of an alignment stack for fabricating a four layer wiring LCP substrate;
FIG. 4e is a schematic diagram of the structure after lamination to make a four layer wiring LCP substrate;
FIG. 4f is a schematic diagram of a laser drilled blind via forming a second type of blind via and a fourth type of blind via for a four layer wiring LCP substrate;
FIG. 4g is a schematic diagram of a structure for blind hole metallization of second and fourth types of blind holes;
FIG. 4h is a schematic diagram of the structure after the second and fifth patterned metal circuit layers are fabricated;
FIG. 4i is a schematic diagram of the structure of an alignment stack for fabricating a six-layer wired LCP substrate;
fig. 4j is a schematic structural diagram of a laminated LCP substrate after fabrication of six layers of wiring;
FIG. 4k is a schematic view of a laser drilled blind via of a six layer wiring LCP substrate to form a first type of blind via and a fifth type of blind via;
FIG. 4l is a schematic diagram of a structure for blind hole metallization of the first type of blind holes and the fifth type of blind holes;
FIG. 4m is a schematic diagram of the structure after the first and sixth patterned metal circuit layers are fabricated; wherein: 121-blind slot slotting region.
FIG. 4n is a schematic diagram of the structure after making the blind trench;
fig. 4o is a schematic structural diagram of the LCP package substrate obtained after the fabrication of the coating layer and the solder mask layer.
FIG. 5 is a schematic diagram of a multi-chip system-in-package structure based on LCP package substrate of embodiment 3 of the present invention;
wherein: 1-LCP package substrate; 2-multi-chip system-in-package structure; 3-chip; 4-gold wire; 5-a metal surrounding frame; 51-metal spacer ribs; 6-a metal cover plate; 7-cavity structure; 16-signal transmission path within the substrate.
Detailed Description
The features and capabilities of the present invention are described in further detail below in connection with the examples.
Example 1
As shown in fig. 1, a six-layer wiring arbitrary layer interconnection LCP package substrate of the present embodiment includes:
the 6 patterned metal circuit layers are distributed from the surface to the bottom and sequentially comprise a first patterned metal circuit layer, a second patterned metal circuit layer, a third patterned metal circuit layer, a fourth patterned metal circuit layer, a fifth patterned metal circuit layer and a sixth patterned metal circuit layer; at least one edge of the outermost periphery of the first patterned metal circuit layer is distributed with bonding pads or patterns for external secondary cascade I/O (input/output) welding of the LCP packaging substrate;
5 insulating medium layers positioned between adjacent patterned metal circuit layers;
a plurality of blind grooves which are positioned in the insulating medium layer between the first patterned metal circuit layer and the second patterned metal circuit layer and are opened towards the first patterned metal circuit layer;
and a plurality of blind holes penetrating and connecting the adjacent patterned metal circuit layers, wherein a plurality of blind holes are distributed on the bonding pad or pattern for the external secondary cascade I/O welding.
1. 6 layers of graphical metal circuit layers:
as shown in fig. 2, the first patterned metal circuit layer 111 includes an outermost bonding pad or pattern 1111 for external secondary cascade I/O bonding, an inner surrounding metal layer 24, and a plurality of groups of chip I/O bonding and signal transmission circuit layers 21, 22, 23 inside the surrounding metal layer 24, each group of chip I/O bonding and signal transmission circuit layers 21, 22, 23 has a rectangular or irregularly shaped island shape, and each group of chip I/O bonding and signal transmission circuit layers 21, 22, 23 is connected to the surrounding metal layer 24 via an electrically insulating region 213, 223, 233; the electrical property of the surrounding metal layer 24 is a ground layer and the process property is an airtight welding layer; the upper surface of the first patterned metal circuit layer 111 is sequentially provided with a coating layer 13 and an upper surface solder resist layer 17; the coating layer 13 covers the bonding pads or patterns 1111 for external secondary cascade I/O bonding, the surrounding metal layer 24, and the I/O bonding and signal transmission line layers 21, 22, 23 of each group of chips; the upper surface solder mask 17 comprises a first surrounding solder mask 174 and a plurality of second surrounding solder masks 171, 172, 173, wherein each second surrounding solder mask 171, 172, 173 surrounds each electrically insulating region 213, 223, 233, and the first surrounding solder mask 174 surrounds all second surrounding solder masks 171, 172, 173;
Each group of chip I/O pads and signal transmission lines layers 21, 22, 23 includes chip I/O pads and signal transmission lines 212, 222, 232, and one or more blind slots 12; the transmission of signals in each group of chip I/O welding and signal transmission line layers 21, 22 and 23 is completed jointly through corresponding parts in the chip I/O welding and signal transmission line layers 21, 22 and 23, the chip I/O welding and signal transmission line layers 212, 222 and 232 or through blind holes 14 (141, 142, 143, 144 and 145) and lower patterned metal line layers (the second patterned metal line layer 112, the third patterned metal line layer 113, the fourth patterned metal line layer 114, the fifth patterned metal line layer 115 and the sixth patterned metal line layer 116); the signal transmission between two or more groups of chip I/O welding and signal transmission layers and between the groups of chip I/O welding and signal transmission layers 21, 22 and 23 and the bonding pad or pattern 1111 for external secondary cascade I/O welding is completed by corresponding parts in each layer of blind holes 14 (141, 142, 143, 144 and 145) and the lower layer of patterned metal circuit layers (the second layer of patterned metal circuit layer 112, the third layer of patterned metal circuit layer 113, the fourth layer of patterned metal circuit layer 114, the fifth layer of patterned metal circuit layer 115 and the sixth layer of patterned metal circuit layer 116) together, such as a transmission path 16 in FIG. 2.
The second patterned metal circuit layer 112 to the fifth patterned metal circuit layer 115 include a plurality of groups of chip I/O solder and signal transmission circuit layers, an electrically insulating region and a surrounding metal layer, which are conventional patterned metal circuit layers, and the specific structure thereof will not be described herein. The process and electrical properties of the 6 th patterned metal line layer 116 are large area metal formations.
2. Insulating dielectric layer
The insulating dielectric layers 15 located between the second patterned metal line layer 112 and the third patterned metal line layer 113, between the third patterned metal line layer 113 and the fourth patterned metal line layer 114, and between the fourth patterned metal line layer 114 and the fifth patterned metal line layer 115 in the 6-layer patterned metal line layer 11 are formed of an LCP substrate (dielectric portion of the double-sided copper-clad LCP substrate 154); insulating dielectric layers located between the first patterned metal wiring layer 111 and the second patterned metal wiring layer 112, and between the fifth patterned metal wiring layer 115 and the sixth patterned metal wiring layer 116, and composed of LCP substrates (dielectric portions of the first single-sided copper-clad LCP substrate 151, the second single-sided copper-clad LCP substrate 153, the third single-sided copper-clad LCP substrate 155, and the fourth single-sided copper-clad LCP substrate 157) and LCP adhesive films (first LCP adhesive film 152 and second LCP adhesive film 156); the melting point of the LCP adhesive film is 10-60 ℃ lower than that of the LCP substrate; the LCP substrate and LCP adhesive film mixed medium are used because a low melting point LCP adhesive film is required as an adhesive layer of the LCP substrate in the lamination process of the multi-layered substrate.
3. Blind groove
The bottom of the blind groove 12 (211, 221, 231) is a large-area metal grounding layer in the second patterned metal circuit layer 112 and is provided with a coating layer; the blind via 12 is a chip I/O pad or pattern (i.e., a chip I/O pad or pattern in the chip I/O pad and signal transmission lines 212, 222, 232) around the opening of the first patterned metal line layer 111; the number and size of the blind slots 12 are determined according to the number and size of the mounted chips.
4. Blind hole
The blind holes are classified into five types according to positions in the 6 patterned metal circuit layers:
the first type of blind holes penetrate through and connect the first patterned metal circuit layer and the second patterned metal circuit layer;
the second type of blind holes penetrate through and connect the second patterned metal circuit layer to the third patterned metal circuit layer;
the third type of blind holes penetrate through and connect the third patterned metal circuit layer and the fourth patterned metal circuit layer;
the fourth type blind holes penetrate through and connect the fourth layer of patterned metal circuit layer to the fifth layer of patterned metal circuit layer;
the fifth type of blind holes penetrate through and connect the fifth layer of patterned metal circuit layer and the sixth layer of patterned metal circuit layer;
all the blind holes 14 of the above five types can be aligned or staggered in the vertical direction for realizing any layer interconnection requirement in the 6-layer patterned metal circuit layer 11. In addition, the diameter of each blind hole 14 is the same, the depth-to-diameter ratio of the blind holes is less than or equal to 1, and the blind holes 14 are filled with solid electroplated copper. The diameters of the five blind holes 14 are the same, on the one hand, the post-filling of the solid electroplated copper can be uniformly manufactured; more importantly, the integrated packaging substrate can be uniformly deformed in the later high-temperature assembly process, so that the interconnection reliability of the integrated packaging substrate is improved. The depth-diameter ratio of the blind holes is less than or equal to 1, so that the process of filling the blind holes with solid copper plating can be better realized, and the defect of copper plating holes is avoided.
Example 2
As shown in fig. 3, the present embodiment provides a manufacturing method of a six-layer wiring arbitrary layer interconnection LCP package substrate 1 as described in embodiment 1, including the steps of:
s1, as shown in FIG. 4a, blind holes are drilled on a double-sided copper-clad LCP substrate 154 by laser, so that a third type of blind holes 143 penetrating through and connecting a third patterned metal circuit layer 113 and a fourth patterned metal circuit layer 114 are formed, and the depth-to-diameter ratio of the blind holes is less than or equal to 1;
s2, as shown in FIG. 4b, the blind holes are metallized to form third type blind holes 143 filled with solid electroplated copper; before blind hole metallization, the pretreatment such as blind hole drilling, pollution removal, plasma activation and the like is needed; the blind hole metallization is realized by a hole filling copper electroplating process, and after hole filling electroplating, a copper plating layer on the surface is thinned to form a third type of blind hole 143 filled with solid copper electroplating;
s3, as shown in FIG. 4c, a third patterned metal circuit layer 113 and a fourth patterned metal circuit layer 114 can be manufactured on the upper surface and the lower surface of the double-sided copper-clad LCP substrate through the conventional process flows of film pasting, exposure, development, etching and the like of the printed board;
s4, taking a second single-sided copper-clad LCP substrate 153 and a third single-sided copper-clad LCP substrate 155, then carrying out alignment lamination as shown in FIG. 4d according to the sequence of the second single-sided copper-clad LCP substrate 153, the double-sided copper-clad LCP substrate 154 treated by S3 and the third single-sided copper-clad LCP substrate 155 from top to bottom, and then pressing under the conditions of high temperature and high pressure and vacuum pumping to form a four-layer wiring LCP substrate as shown in FIG. 4 e; wherein the copper-clad side of the second single-sided copper-clad LCP substrate 153 faces upward and the copper-clad side of the third single-sided copper-clad LCP substrate 155 faces downward;
S5, as shown in FIG. 4f, blind holes are drilled on the second single-sided copper-clad LCP substrate 153 and the third single-sided copper-clad LCP substrate 155 of the four-layer wiring LCP substrate by laser, and a second type blind hole 142 penetrating and connecting the second patterned metal circuit layer 112 and the third patterned metal circuit layer 113 and a fourth type blind hole 144 penetrating and connecting the fourth patterned metal circuit layer 114 and the fifth patterned metal circuit layer 115 are respectively formed;
s6, as shown in FIG. 4g, the blind holes are metallized to form second type blind holes 142 and fourth type blind holes 144 filled with solid electroplated copper;
s7, as shown in fig. 4h, the second patterned metal line layer 112 and the fifth patterned metal line layer 115 may be manufactured on the upper surface of the second single-sided copper-clad LCP substrate 153 and the lower surface of the third single-sided copper-clad LCP substrate 155 of the four-layer wiring LCP substrate, respectively, by the same method as in step S3;
s8, taking the first single-sided copper-clad LCP substrate 151, the fourth single-sided copper-clad LCP substrate 157, the first LCP adhesive film 152 and the second LCP adhesive film 156, then performing alignment lamination as shown in FIG. 4i according to the sequence of the four-layer wiring LCP substrate, the second LCP adhesive film 156 and the fourth single-sided copper-clad LCP substrate 157 after the treatment of the first single-sided copper-clad LCP substrate 151, the first LCP adhesive film 152 and the S7 from top to bottom, and then pressing to form six-layer wiring LCP substrates as shown in FIG. 4 j; wherein the copper-clad surface of the first single-sided copper-clad LCP substrate 151 faces upward, and the copper-clad surface of the fourth single-sided copper-clad LCP substrate 157 faces downward; the melting point of the first LCP adhesive film 152 and the second LCP adhesive film 156 is lower than that of the first single-sided copper-clad LCP substrate 151, the second single-sided copper-clad LCP substrate 153, the double-sided copper-clad LCP substrate 154, the third single-sided copper-clad LCP substrate 155, and the fourth single-sided copper-clad LCP substrate 157, which are typically lower by 10 to 60 ℃; because the temperature and pressure required by the lamination of the LCP adhesive film are lower than the conditions required by the lamination of the step S4 to form the four-layer wiring LCP substrate, the lamination can not influence the structure of the existing four-layer wiring LCP substrate, thereby providing a necessary foundation for the realization of the six-layer wiring LCP substrate.
S9, as shown in FIG. 4k, blind holes are drilled on a first single-sided copper-clad LCP substrate 151 and a fourth single-sided copper-clad LCP substrate 157 of the six-layer wiring LCP substrate by laser, and a first blind hole 141 penetrating and connecting the first patterned metal circuit layer 111 and the second patterned metal circuit layer 112, and a fifth blind hole 145 penetrating and connecting the fifth patterned metal circuit layer 115 and the sixth patterned metal circuit layer 116 are respectively formed, wherein the depth-to-diameter ratio of the blind holes is less than or equal to 1;
s10, as shown in FIG. 4l, the blind holes are metallized to form first type blind holes 141 and fifth type blind holes 145 filled with solid electroplated copper;
s11, as shown in fig. 4m, the same method as in step S3 may be used to manufacture the first patterned metal wiring layer 111 on the upper surface of the first single-sided copper-clad LCP substrate 151 and the sixth patterned metal wiring layer 116 on the lower surface of the fourth single-sided copper-clad LCP substrate 157; and copper of the blind groove slotting region 121 in the first patterned metal circuit layer 111 is removed; the blind groove slotting region 121 is a position determined according to design, is a nonmetallic region, can be processed by adopting a copper etching process, and can remove a copper layer of the blind groove slotting region 121 so as to facilitate subsequent laser slotting treatment;
S12, as shown in FIG. 4n, grooving the blind groove area by adopting a laser processing means to form a blind groove 12 for mounting a chip, and decontaminating the bottom and the side wall of the blind groove 12; the laser processing means comprises a laser light source which is solid ultraviolet laser or gas carbon dioxide laser;
s13, as shown in fig. 4o, a first patterned metal circuit layer 111 and the bottom of the blind trench 12 are subjected to a coating layer manufacturing, and an upper surface solder resist layer 17 is formed on the coating layer 13 of the corresponding portion, thereby obtaining the LCP package substrate 1. The coating layer 13 material includes, but is not limited to, electro-gold plating, electroless nickel-gold, electroless nickel-palladium-gold.
S14, if the LCP package substrate is manufactured in the spliced form through steps S1 to S13, the LCP package substrate manufactured in the spliced form is milled to form the individual LCP package substrate 1.
That is, when the LCP package substrate is directly manufactured by using a single LCP substrate through steps S1 to S13, the resulting LCP package substrate 1 is a desired structure; when the LCP package substrate is manufactured in a spliced form through steps S1 to S13, the resulting LCP package substrate 1 needs to be milled to a desired structure.
Example 3
As shown in fig. 5, the present embodiment provides a multi-chip system-in-package structure 2 based on the LCP package substrate of embodiments 1-2, comprising: the LCP package substrate 1, as described in embodiments 1-2, and a chip 3, a metal enclosure 5, and a metal cover plate 6;
The multi-chip system-in-package structure 2 is fixed on a PCB motherboard in a bonding or welding mode by conductive adhesive, and an external secondary cascade I/O welding pad or pattern 1111 positioned on the LCP package substrate 1 is used as an external secondary cascade I/O interface of the multi-chip system-in-package structure 2;
the metal surrounding frame 5 is internally provided with metal separation ribs 51; the metal surrounding frame 5 and the metal barrier ribs 51 are welded on the upper surface of the LCP packaging substrate 1, the bonding pad or the pattern 1111 for the external secondary cascade I/O welding is arranged outside the metal surrounding frame 5, the metal cover plate 6 is welded on the metal surrounding frame 5 and the metal barrier ribs 51, and a plurality of cavity structures 7 with airtight packaging performance and electromagnetic shielding performance are formed between the LCP packaging substrate 1 and the metal cover plate 6 through the metal surrounding frame 5 and the metal barrier ribs 51; each cavity structure 7 contains one or more blind slots 12 therein; each blind slot 12 is used for installing one chip 3, when the installed chip 3 has no electromagnetic shielding requirement, the blind slots can be installed in the same cavity structure 7, and when the installed chip 3 has the electromagnetic shielding requirement, the blind slots are installed in different cavity structures 7; the chip 3 is adhered in the blind groove 12 through conductive adhesive, and is electrically interconnected with the chip I/O welding and signal transmission circuit layers 21, 22 and 23 in the first patterned metal circuit layer 111 in a gold wire 4 bonding mode;
The transmission of signals in each group of chip I/O welding and signal transmission line layers 21, 22 and 23 is completed jointly through corresponding parts in the chip I/O welding and signal transmission line layers 21, 22 and 23, the chip I/O welding and signal transmission line layers 212, 222 and 232 or through blind holes 14 (141, 142, 143, 144 and 145) and lower patterned metal line layers (the second patterned metal line layer 112, the third patterned metal line layer 113, the fourth patterned metal line layer 114, the fifth patterned metal line layer 115 and the sixth patterned metal line layer 116); the signal transmission between the two or more chip I/O bonding and signal transmission layers 21, 22, 23 and between the plurality of chip I/O bonding and signal transmission layers 21, 22, 23 and the external secondary cascade I/O bonding pad or pattern 1111 is completed by the corresponding parts of the blind holes 14 (141, 142, 143, 144, 145) and the lower patterned metal wiring layers (the second patterned metal wiring layer 112, the third patterned metal wiring layer 113, the fourth patterned metal wiring layer 114, the fifth patterned metal wiring layer 115, the sixth patterned metal wiring layer 116) in common, as the transmission path 16 in fig. 5.
The foregoing description of the preferred embodiments of the invention is not intended to limit the invention to the particular embodiments disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention 。

Claims (9)

1. A six-layer wiring arbitrary layer interconnect LCP package substrate, comprising:
the 6 patterned metal circuit layers are distributed from the surface to the bottom and sequentially comprise a first patterned metal circuit layer, a second patterned metal circuit layer, a third patterned metal circuit layer, a fourth patterned metal circuit layer, a fifth patterned metal circuit layer and a sixth patterned metal circuit layer; at least one edge of the outermost periphery of the first patterned metal circuit layer is distributed with bonding pads or patterns for external secondary cascade I/O (input/output) welding of the LCP packaging substrate;
5 insulating medium layers positioned between adjacent patterned metal circuit layers; the insulating medium layers are positioned between the second patterned metal circuit layer and the third patterned metal circuit layer, between the third patterned metal circuit layer and the fourth patterned metal circuit layer and between the fourth patterned metal circuit layer and the fifth patterned metal circuit layer and are formed by LCP substrates; the insulating medium layer is positioned between the first patterned metal circuit layer and the second patterned metal circuit layer and between the fifth patterned metal circuit layer and the sixth patterned metal circuit layer and consists of an LCP substrate and an LCP bonding film;
A plurality of blind grooves which are positioned in the insulating medium layer between the first patterned metal circuit layer and the second patterned metal circuit layer and are opened towards the first patterned metal circuit layer;
a plurality of blind holes penetrating and connecting adjacent graphical metal circuit layers, wherein a plurality of blind holes are distributed on the bonding pad or the graph for external secondary cascade I/O welding;
the first patterned metal circuit layer comprises a bonding pad or a pattern for external secondary cascade I/O welding at the outermost periphery, an inner surrounding metal layer and a plurality of groups of chip I/O welding and signal transmission circuit layers at the inner side of the surrounding metal layer, wherein each group of chip I/O welding and signal transmission circuit layers is in a rectangular or irregularly-shaped island shape, and each group of chip I/O welding and signal transmission circuit layers is connected with the surrounding metal layer through an electric insulation area; the electrical property of the surrounding metal layer is a grounding layer, and the technological property is an airtight welding layer; the upper surface of the first patterned metal circuit layer is sequentially provided with a coating layer and an upper surface solder resist layer; the coating layer covers the bonding pad or graph for external secondary cascade I/O welding, the surrounding metal layer and each group of chip I/O welding and signal transmission line layers; the upper surface solder mask comprises a first surrounding solder mask layer and a plurality of second surrounding solder mask layers, wherein each second surrounding solder mask layer correspondingly surrounds each electric insulation area, and the first surrounding solder mask layer surrounds all the second surrounding solder mask layers;
Each group of chip I/O welding and signal transmission line layers comprises a chip I/O welding pad, a signal transmission line and one or more blind grooves; the transmission of signals in each group of chip I/O welding and signal transmission circuit layers is completed jointly through the chip I/O welding and signal transmission circuit in each group of chip I/O welding and signal transmission circuit layers or through corresponding parts in each layer of blind holes and the lower layer of patterned metal circuit layers; the signal transmission between two or more groups of chip I/O welding and signal transmission layers and between a plurality of groups of chip I/O welding and signal transmission layers and an external secondary cascade I/O welding pad or pattern is completed by blind holes of each layer and corresponding parts in the lower patterned metal circuit layer.
2. The LCP packaging substrate of claim 1, wherein the LCP adhesive film has a melting point 10-60 ℃ lower than that of the LCP substrate.
3. The LCP package substrate of claim 1, wherein the blind trench bottom is a large area metal ground layer in a second patterned metal line layer, and has a coating layer; the blind groove is a chip I/O pad or pattern around the opening of the first patterned metal circuit layer; the number and the size of the blind slots are determined according to the number and the size of the mounted chips.
4. The LCP package substrate of claim 1, wherein all blind vias are vertically aligned or staggered to achieve any of the interconnect requirements of the 6 patterned metal wiring layers; the diameter of each blind hole is the same, the depth-diameter ratio of the blind holes is less than or equal to 1, and the blind holes are filled with solid electroplated copper.
5. The LCP package substrate of claim 1, wherein the process and electrical properties of the sixth patterned metal wiring layer are large area metal strata.
6. A method of manufacturing a six-layer wiring arbitrary layer interconnect LCP package substrate, wherein the manufacturing method is used to manufacture the LCP package substrate of any one of claims 1-5, comprising the steps of:
s1, laser drilling blind holes on a double-sided copper-clad LCP substrate to form third blind holes penetrating through and connecting a third patterned metal circuit layer and a fourth patterned metal circuit layer;
s2, metallizing the blind holes to form third blind holes filled with solid electroplated copper;
s3, manufacturing a third patterned metal circuit layer and a fourth patterned metal circuit layer on the upper surface and the lower surface of the double-sided copper-clad LCP substrate;
s4, taking a second single-sided copper-clad LCP substrate and a third single-sided copper-clad LCP substrate, and then laminating the second single-sided copper-clad LCP substrate, the double-sided copper-clad LCP substrate treated in the S3 and the third single-sided copper-clad LCP substrate in sequence from top to bottom under the conditions of high temperature and high pressure vacuum pumping, and then laminating to form four layers of wiring LCP substrates; wherein the copper-clad surface of the second single-sided copper-clad LCP substrate faces upwards, and the copper-clad surface of the third single-sided copper-clad LCP substrate faces downwards;
S5, laser drilling blind holes on a second single-sided copper-clad LCP substrate and a third single-sided copper-clad LCP substrate of the four-layer wiring LCP substrate, and respectively forming second type blind holes penetrating and connecting a second patterned metal circuit layer and a third patterned metal circuit layer and fourth type blind holes penetrating and connecting a fourth patterned metal circuit layer and a fifth patterned metal circuit layer;
s6, metallizing the blind holes to form second-type blind holes and fourth-type blind holes filled with solid electroplated copper;
s7, respectively manufacturing a second patterned metal circuit layer and a fifth patterned metal circuit layer on the upper surface of a second single-sided copper-clad LCP substrate and the lower surface of a third single-sided copper-clad LCP substrate of the four-layer wiring LCP substrate;
s8, taking a first single-sided copper-clad LCP substrate, a fourth single-sided copper-clad LCP substrate, a first LCP bonding film and a second LCP bonding film, and then laminating the first single-sided copper-clad LCP substrate, the first LCP bonding film, the four-layer wiring LCP substrate treated in the S7, the second LCP bonding film and the fourth single-sided copper-clad LCP substrate in the order from top to bottom, and then laminating the six-layer wiring LCP substrate; wherein the copper-clad surface of the first single-sided copper-clad LCP substrate faces upwards, and the copper-clad surface of the fourth single-sided copper-clad LCP substrate faces downwards; the melting point of the first LCP bonding film and the second LCP bonding film is lower than that of the first single-sided copper-clad LCP substrate, the second single-sided copper-clad LCP substrate, the double-sided copper-clad LCP substrate, the third single-sided copper-clad LCP substrate and the fourth single-sided copper-clad LCP substrate;
S9, laser drilling blind holes on a first single-sided copper-clad LCP substrate and a fourth single-sided copper-clad LCP substrate of the six-layer wiring LCP substrate, and respectively forming a first type blind hole penetrating and connecting a first patterned metal circuit layer and a second patterned metal circuit layer and a fifth type blind hole penetrating and connecting a fifth patterned metal circuit layer and a sixth patterned metal circuit layer;
s10, metallizing blind holes to form first type blind holes and fifth type blind holes filled with solid electroplated copper;
s11, manufacturing a first patterned metal circuit layer on the upper surface of a first single-sided copper-clad LCP substrate of the six-layer wiring LCP substrate, and manufacturing a sixth patterned metal circuit layer on the lower surface of a fourth single-sided copper-clad LCP substrate; copper in a blind groove slotting area in the first patterned metal circuit layer is removed;
s12, grooving the blind groove grooving area by adopting a laser processing means to form a blind groove for installing a chip, and decontaminating the bottom and the side wall of the blind groove;
s13, manufacturing a coating layer on the first patterned metal circuit layer and the bottom of the blind groove, and manufacturing an upper surface solder mask layer on the coating layer of the corresponding part to obtain an LCP packaging substrate;
and S14, if the LCP packaging substrate is manufactured in a spliced form through steps S1 to S13, milling the LCP packaging substrate manufactured in the spliced form to form a single LCP packaging substrate.
7. The method of manufacturing an LCP package substrate of claim 6, wherein the blind via ratio is 1 or less.
8. The method of manufacturing an LCP package substrate according to claim 6, wherein the melting point of the first and second LCP adhesive films is 10-60 ℃ lower than the melting point of the first single-sided copper-clad LCP substrate, the second single-sided copper-clad LCP substrate, the double-sided copper-clad LCP substrate, the third single-sided copper-clad LCP substrate, and the fourth single-sided copper-clad LCP substrate.
9. A multi-chip system-in-package structure, comprising: an LCP package substrate as recited in any one of claims 1-5, and a chip, a metal bezel, and a metal cover plate;
the multi-chip system level packaging structure is fixed on a PCB motherboard in a conductive adhesive bonding or welding mode, and a bonding pad or a graph for external secondary cascade I/O welding on the LCP packaging substrate is used as an external secondary cascade I/O interface of the multi-chip system level packaging structure;
the metal surrounding frame is internally provided with metal separation ribs; the metal surrounding frame and the metal separating ribs are welded on the upper surface of the LCP packaging substrate, the bonding pad or the pattern for external secondary cascade I/O welding is arranged outside the metal surrounding frame, the metal cover plate is welded on the metal surrounding frame and the metal separating ribs, and a plurality of cavity structures with airtight packaging performance and electromagnetic shielding performance are formed between the LCP packaging substrate and the metal cover plate through the metal surrounding frame and the metal separating ribs; each cavity structure comprises one or more blind grooves; each blind groove is used for installing a chip, when the installed chip has no electromagnetic shielding requirement, the blind grooves are installed in the same cavity structure, and when the installed chip has the electromagnetic shielding requirement, the blind grooves are installed in different cavity structures; the chip is adhered to the blind groove through conductive adhesive, and is electrically interconnected with the chip I/O welding and signal transmission circuit layer in the first patterned metal circuit layer in a gold wire bonding mode.
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