CN112347028A - Data processing method and system based on FPGA - Google Patents
Data processing method and system based on FPGA Download PDFInfo
- Publication number
- CN112347028A CN112347028A CN202011016308.7A CN202011016308A CN112347028A CN 112347028 A CN112347028 A CN 112347028A CN 202011016308 A CN202011016308 A CN 202011016308A CN 112347028 A CN112347028 A CN 112347028A
- Authority
- CN
- China
- Prior art keywords
- data
- descriptor
- dmac
- fpga
- soft core
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000003672 processing method Methods 0.000 title claims abstract description 36
- MHABMANUFPZXEB-UHFFFAOYSA-N O-demethyl-aloesaponarin I Natural products O=C1C2=CC=CC(O)=C2C(=O)C2=C1C=C(O)C(C(O)=O)=C2C MHABMANUFPZXEB-UHFFFAOYSA-N 0.000 claims abstract description 145
- 238000000034 method Methods 0.000 claims abstract description 19
- 230000008569 process Effects 0.000 claims description 10
- 239000002245 particle Substances 0.000 claims description 6
- 238000004891 communication Methods 0.000 abstract description 16
- 230000005540 biological transmission Effects 0.000 description 31
- 238000009825 accumulation Methods 0.000 description 10
- 230000003139 buffering effect Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000007246 mechanism Effects 0.000 description 3
- 230000004044 response Effects 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 2
- 230000001960 triggered effect Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7839—Architectures of general purpose stored program computers comprising a single central processing unit with memory
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0875—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0877—Cache access modes
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Communication Control (AREA)
Abstract
The invention provides a data processing method based on FPGA, which is characterized in that the data of Ethernet is sent to an FPGA soft core through DMAC, and the method comprises the following steps: step S10, the DMAC obtaining the current idle descriptor; step S20, according to the data reception start condition, the DMAC writes the data of the ethernet into the data block corresponding to the DDR and the current descriptor, step S30, according to the data reception end condition, the control position "0" of the current descriptor is set by the control register; and step S40, the FPGA soft core reads the data written in the data block. In the invention, when the data of the Ethernet is sent to the FPGA soft core, the Ethernet and an off-chip storage device (such as DDR) directly transmit a large amount of data without passing through the FPGA soft core through the DMAC, thereby overcoming the problem that the processing capacity of the FPGA soft core is not enough to match the communication rate of the Ethernet.
Description
[ technical field ] A method for producing a semiconductor device
The invention relates to the technical field of FPGA (field programmable gate array), in particular to a data processing method and a data processing system based on FPGA.
[ background of the invention ]
The hardware structure of the gigabit Ethernet may be divided into a MAC controller and a PHY processing chip, where the MAC controller may be implemented by an Ethernet IP core of an FPGA (Field Programmable gate array). On the basis, the Cortex M1 soft core based on FPGA (FPGA soft core) is used for matching with CACHE equipment, so that the application scenarios of Ethernet are greatly widened, for example, the LwIP protocol stack based on the Cortex M1 soft core is realized. However, the Cortex M1 soft core has the characteristics of low power consumption, low system dominant frequency, and multiple CACHE operation cycle overhead, which results in the processing power of the Cortex M1 soft core being far from matching the communication rate of ethernet.
Therefore, how to improve the processing capability of Cortex M1 soft core to match the communication rate of ethernet is a pending problem.
[ summary of the invention ]
The invention aims to provide an embedded Ethernet data processing method and system based on an FPGA.
In order to achieve the above object, the present invention provides a data processing method based on an FPGA, wherein the data processing method is to send ethernet data to an FPGA soft core through DMAC, and comprises the following steps:
step S10, the DMAC obtaining the current idle descriptor;
step S20, according to the data receiving start condition, the DMAC writes the data of the ethernet into the data block corresponding to the current descriptor of the DDR,
step S30, according to the data reception end condition, the control position "0" of the current descriptor is set by the control register;
and step S40, the FPGA soft core reads the data written in the data block.
Preferably, in step S20, the data reception start condition is that the TSMAC _ rvald signal in the TSMAC IP user-side data interface is raised; in step S30, the data reception end condition is that the TSMAC _ rlast signal in the TSMAC IP user-side data interface is pulled high.
Preferably, in step S20, the writing, by the DMAC, the data of the ethernet into the data block corresponding to the current descriptor in the DDR includes:
step S21, the DMAC writes the ethernet data into a data buffer register;
and step S22, writing the data written into the data buffer register into the DDR particles through a ping-pong structure.
Preferably, step S40 is preceded by the DMAC obtaining a link of the current descriptor and performing step S20.
Preferably, in step S40, specifically,
step S41, the FPGA soft core receives the current descriptor and the data length;
and step S42, reading the data written into the data block by the FPGA soft core through forced refreshing.
Preferably, after step S40, the data processing method further comprises,
step S50, after data are read, sending the current descriptor to the FPGA through a control register; meanwhile, the control position of the current descriptor is '1' through the control register;
step S60, the DMAC obtains the link of the current descriptor, and the DMAC determines whether the control bit of the next descriptor is 0, and if the control bit is 0, executes step S40.
Preferably, the data processing method further includes the steps of:
step S01, the FPGA soft core sends the descriptor which needs to be initialized to the DMAC;
step S02, the FPGA soft core sends the descriptor information of the current descriptor to the DMAC;
step S03, the DMAC completes initialization configuration according to the received descriptor and the descriptor information;
step S04, if all the descriptors are not initialized, repeating the step S01; if all the descriptors are initialized completely, the initialization process is finished, and the initial done is sent to the DMAC through the state register.
The invention also provides a data processing system based on the FPGA, which comprises an FPGA soft core, a DMAC and a DDR, wherein the FPGA soft core is communicated with the DMAC through an AHB bus, and the DMAC is communicated with the DDR through an AXI bus; the DMAC includes an RX descriptor ring; the data processing system also comprises the FPGA-based data processing method applied to the data processing system.
Preferably, the RX descriptor ring includes 1024-level RX descriptors.
Preferably, the RX descriptor includes a control bit, a link, a packet address and packet length information.
The invention has the beneficial effects that: according to the data processing method based on the FPGA, when the data of the Ethernet is sent to the FPGA soft core, the Ethernet and an off-chip storage device (such as DDR) are directly transmitted in large data volume without passing through the FPGA soft core through the DMAC, and therefore the problem that the processing capacity of the FPGA soft core is not enough to match the communication rate of the Ethernet is solved.
[ description of the drawings ]
FIG. 1 is a flow chart of an FPGA-based data processing method according to an embodiment of the present invention;
FIG. 2 is an RX flow diagram of an FPGA-based data processing method according to an embodiment of the present invention;
FIG. 3 is a system block diagram of an FPGA-based data processing system in accordance with an embodiment of the present invention;
FIG. 4 is a block diagram of the DMAC of the FPGA based data processing system according to one embodiment of the present invention.
[ detailed description ] embodiments
In order to make the objects, technical solutions and advantages of the present disclosure more clear, the technical solutions of the present disclosure will be clearly and completely described below with reference to the specific embodiments of the present disclosure and the accompanying drawings. It is to be understood that the embodiments described are only a few embodiments of the present disclosure, and not all embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present specification without any creative effort belong to the protection scope of the present specification.
The terms "first," "second," and "third," etc. in the description and claims of the present invention and the above-described drawings are used for distinguishing between different objects and not for describing a particular order. Furthermore, the terms "comprises" and any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or inherent to such process, method, article, or apparatus.
Referring to fig. 1, an embodiment of the present invention provides an embedded ethernet data processing method based on an FPGA, where the data processing method sends ethernet data to an FPGA soft core through a DMAC, that is, an RX (receive) data transmission flow, and includes the following steps:
step S10, the DMAC obtains the currently idle descriptor. The DMAC obtains a descriptor that is currently idle on the descriptor ring, wherein after the initialization procedure, the RX data transmission procedure is performed by default starting with descriptor 0.
Step S20, according to the data reception start condition, the DMAC writes the data of the ethernet into the data block corresponding to the current descriptor and the DDR. The data receiving starting condition is that a TSMAC _ valid signal in a TSMAC IP user side data interface is pulled high. The TSMAC IP is used for realizing the connection between the MAC in the Ethernet structure and the DMAC through a data bus specified by the TSMAC IP; the TSMAC _ valid is a control signal of the TSMAC IP data bus that is pulled up automatically in the IP, which is an input signal to the DMAC, without the DMAC performing a pull-up operation.
The writing of the data of the ethernet into the data block corresponding to the current descriptor by the DMAC includes:
step S21, the DMAC writes the ethernet data into a data buffer register. That is, the DMAC directly writes the ethernet valid data into a data buffer register and integrates the ethernet valid data into a data width recognizable by the AXI interface.
And step S22, writing the data written into the data buffer register into a data block corresponding to the current descriptor of the DDR through a ping-pong structure.
Step S23, each time data write (AXI transfer) is completed, the word counter and address counter of the DMAC accumulate the number of bytes of the write (actually transferred) data, and count the number of bytes (byte accumulation number) of the write data in one packet/one frame.
Step S30, according to the data reception end condition, the control position of the current descriptor is "0" through the control register. And the data receiving end condition is that a TSMAC _ rlast signal in a TSMAC IP user side data interface is pulled high. TSMAC _ rlast is a control signal of the TSMAC IP data bus, pulling up automatically in the IP, which is an input signal to the DMAC, without the DMAC performing a pull-up operation.
Further, the control position of the current descriptor is set to be '0' through a control register, and meanwhile, the receiving interruption is triggered; i.e. the control register will control the current descriptor to be "0" and trigger the receive interrupt. And sending the current descriptor (the descriptor of the current descriptor) and the received data length (byte accumulation) to the FPGA soft core through an interrupt function, and clearing the interrupt after sending.
And step S40, the FPGA soft core reads the data written in the data block. In this step, data written in a data block corresponding to the DDR and the current descriptor is read to the FPGA soft core, so that the data of the ethernet is sent to the FPGA soft core.
The reading and writing of the data in the data block by the FPGA soft core specifically comprises the following steps:
step S41, the FPGA soft core receives a current descriptor (descriptor of the current descriptor) and a data length (byte accumulation);
and step S42, reading the data written into the data block by the FPGA soft core through forced refreshing. In this step, the FPGA soft core performs forced refresh through the DCACHE according to the received and stored current descriptor (descriptor of the current descriptor) and data length (byte accumulation), and the FPGA soft core reads data written in the data block.
Wherein the forced refresh includes, in response to the request,
s421, the FPGA soft core sends the initial address and the data length of the data to be refreshed to a Dcache module through an AHB bus;
s422, the FPGA soft core sends a forced refreshing instruction; meanwhile, the FPGA soft core is forcibly suspended, namely, the execution operation of the instruction and the data is suspended;
s423, the Dcache module receives the forced refresh command and triggers the Dcache module to carry out forced refresh operation;
s424, the Dcache module scans Tag information of the cache line and judges whether the Tag of the cache line is hit; if the Tag corresponding to the cache line is cleared, the cache line is refreshed; if not, skipping over the cache line; wherein, the hit is consistent with the Tag of the data to be refreshed in the FPGA soft core and the Tag of the scanning cache line of the Dcache module;
s425, the Dcache module scans each cache line and executes the step S424;
and S426, after the forced refreshing is finished, feeding back the finished state information to the FPGA soft core through an AHB bus.
Preferably, step S40 is preceded by the DMAC obtaining a link of the current descriptor and performing step S20. The DMAC starts preparing for reception (buffering) of the next data through step S400, i.e., the DMAC starts preparing for writing the next data transmitted over the ethernet into the data block corresponding to the next descriptor of the DDR. Steps S10 → S20 → S30, and S400 → S20 → S30 → S400 loop back and forth, during which step S400 is identical to step S10, the DMAC acquires the current (next) free descriptor (linker), writes the data sent over the ethernet to the data block corresponding to the DDR and current (next) descriptor. When the next idle descriptor is obtained and data reception is started, the next idle descriptor is also the current idle descriptor.
In the loop, RX data transmission flow is continuously performed (ethernet data is continuously transmitted to the FPGA soft core), and the FPGA soft core needs to open multiple buffer spaces to retain descriptors of current (next) descriptors and descriptor information.
Step S41, according to the number of times of sending data by Ethernet, the FPGA soft core receives and stores the descriptor (descriptor symbol) and the data length (byte accumulation) of actual reception each time;
and step S42, the FPGA soft core reads the data written into the data block corresponding to the current (next) descriptor of the DDR one by one through forced refreshing according to the received and stored descriptor and the actually received data length.
The embedded ethernet data processing method based on FPGA of the embodiments of the present invention further includes,
step S50, after the data reading is finished, sending the current descriptor to the FPGA soft core through a control register dmac _ control [31:16 ]; control position "1" of the current descriptor is set by control register dmac _ control [2 ]. Specifically, after the data reading of the FPGA soft core is finished, the descriptor of the current descriptor is sent to the FPGA through the control register dmac _ control [31:16], and meanwhile, the control position "1" of the current descriptor is sent through the control register dmac _ control [2], and the current descriptor is in an idle state.
And step S60, the FPGA soft core judges whether unread data exist in the DDR according to the sequence of the received and stored descriptors and the data length, if so, the step S40 is executed, and if not, the RX data transmission flow is ended.
Specifically, the FPGA soft core determines whether there is unread (extracted) data in the DDR corresponding to the received descriptor according to the sequence of the received and stored descriptor and the actually received data length, if so, executes step S40, otherwise, ends the RX data transmission flow.
The FPGA soft core starts to prepare for reading of the next (cached) data, that is, the FPGA soft core starts to prepare for reading data written in the data block corresponding to the next descriptor by the DDR, through step S60. Steps S40 → S50 → S60, and S60 → S40 → S50 → S60 are repeated, during which the FPGA soft core reads all data written in the data block corresponding to the next descriptor of the DDR, so far the RX data transfer flow is ended.
In the above, the step S10(S400) and the step S40 may be performed in synchronization.
Further, the embedded ethernet data processing method further includes an RX packet loss mechanism, that is, when the DMAC receives the ethernet data, a new (received) data packet is discarded without changing the control bit state of the descriptor ring. Wherein, the packet discarding includes the following conditions:
1) the descriptor ring initialization is not complete;
2) RX status is busy;
3) DCACHE forced refresh is being performed;
4) there is no idle descriptor.
In the embedded ethernet data processing method based on the FPGA of the embodiments of the present invention, when the data of the ethernet is sent to the FPGA soft core, the DMAC enables the ethernet and the off-chip storage device (e.g., DDR) to directly transmit a large amount of data without passing through the FPGA soft core, thereby overcoming a problem that the processing capability of the FPGA soft core is not sufficient to match the communication rate of the ethernet. Furthermore, when the FPGA soft core data is written back and updated, DCACHE forced refreshing operation is synchronously matched, and the CACHE consistency problem is solved.
The embedded ethernet data processing method based on FPGA of the embodiment of the present invention further includes an initialization process before step 10, specifically:
step S01, the FPGA soft core sends the descriptor which needs to be initialized currently in the descriptor ring to the DMAC through a descriptor register descriptor _ num [15:0 ];
step S02, the FPGA soft core sequentially sends descriptor information such as descriptor control register descriptor _ ctrl [15:0] (rx), descriptor receiving starting address descriptor _ rxaddr, descriptor data length descriptor _ len [15:0] (rx) and the like corresponding to the current descriptor to the DMAC;
step S03, the DMAC completes the initialization configuration of the received descriptor according to the descriptor (descriptor) and the descriptor information of the received descriptor ring;
step S04, if all the descriptors (descriptor symbols) on the descriptor ring are not initialized, repeating the step S01; if all the descriptors (descriptors) on the descriptor ring are initialized completely, the initialization process is ended, and the initial done is sent to the DMAC through the status register DMAC _ states [1 ]. I.e., status position "1" of the status register, and is sent to the DMAC.
In this embodiment, the descriptor ring is an RX descriptor ring, the descriptor is an RX descriptor, and the descriptor is an RX descriptor. The descriptor ring comprises a plurality of descriptors, and each descriptor on the descriptor ring corresponds to a descriptor so as to locate the position of the required descriptor on the descriptor ring.
The embodiment of the invention also provides an embedded Ethernet data processing system based on the FPGA, which comprises an FPGA soft core, a DMAC (Ethernet DMAC controller) and a DDR, wherein the FPGA soft core is communicated with the DMAC through an AHB bus, and controls the DMAC through the AHB bus; the DMAC and DDR communicate over an AXI bus.
The DMAC performs read-write operations of initialization and other registers through an AHB bus, and issues or uploads related initialization, control and state information; and the direct communication between the Ethernet (Ethernet) and the DDR is carried out by utilizing the register, and the conversion of the AXI4 bus interface and the Ethernet (Ethernet) interface and the AXI4 arbitration are simultaneously realized.
The DMAC includes a soft core control module, a DMA communication control module, and an RX descriptor ring.
The soft core control module is used for controlling RX (receiving) of the DMAC by the FPGA soft core, exchanging the length of an RX actual data packet and receiving initialization RX descriptor ring information. The DMA communication control module is used for buffering DDR data and Ethernet (Ethernet) data, storing AXI4 address/byte count and integrating AXI4 address/data format, and simultaneously, initialization and state control are carried out on an RX descriptor ring by using descriptor control logic. The RX descriptor ring is used to store control bits, a linker, a packet address, and packet length information of the DMAC RX descriptor ring.
RX descriptor ring (RX descriptor) structure: { control bit (empty _ flag), chaining symbol (Link), packet start address, packet length }; wherein the control bit indicates whether the descriptor is empty; the linker represents the next descriptor; the starting address of the data packet represents the starting address of the buffer area corresponding to the descriptor; the packet length indicates the size of the buffer space corresponding to the descriptor.
In order to match the rate of gigabit ethernet, in the embodiment of the present invention, the RX descriptor ring has at most 1024 levels of RX descriptors; RX sets the linker to sequential execution, i.e., RX is 0-1-2- … -1023-0.
The embedded ethernet data processing system of the embodiment of the present invention further includes the above-mentioned embedded ethernet data processing method, so as to send the ethernet data to the FPGA soft core through the DMAC, and repeated parts are not described again.
The DMAC is used for RX (receive) data transmission flow: under the control of the FPGA soft core (in this example, Cortex M1 is adopted), the data of the Ethernet is directly written into an appointed (corresponding to a descriptor) position in the DDR particle through the DMAC, and then the data of the Ethernet is read into the FPGA soft core for processing through DCACHE forced refreshing.
The embedded Ethernet data processing system of the embodiment of the invention realizes an FPGA soft core system with Ethernet DMAC in FPGA, so as to match the application requirement of Ethernet communication rate and provide hardware basis for LwIP and other communication protocol stacks.
The embodiment of the invention also provides an embedded Ethernet data processing method based on the FPGA, and the data processing method comprises a TX (sending) data transmission flow and an RX (receiving) data transmission flow.
The TX (transmit) data transmission process, i.e. transmitting data in the FPGA soft core to the ethernet through DMAC, includes the following steps:
and step S110, the FPGA soft core acquires the current idle TX descriptor.
Specifically, the FPGA soft core reads back the currently idle TX descriptor by sending the descriptor register dmac _ txnum [16], so that the FPGA soft core locates the position of the currently idle TX descriptor on the TX descriptor ring. After the initialization procedure, the TX data transmission procedure is performed by default starting from TX descriptor 0.
And step S120, the FPGA soft core sends a data length value to the DMAC, and the DMAC writes the data length value into a length register corresponding to the current TX descriptor.
Specifically, the FPGA soft core sends a data length value to the DMAC through a sending data length register DMAC _ txlen [31:16], and the DMAC automatically writes the data length value into a length register corresponding to the current TX descriptor. And the data length value is the actual data length value to be sent of the FPGA soft core.
And step S130, the FPGA soft core updates data to a data block corresponding to the DDR and the current TX descriptor. Specifically, when the status register dmac _ states [0] is 0, the FPGA soft core updates data to the data block corresponding to the current TX descriptor of the DDR by the DCACHE forced write-back. Status register dmac _ states [0] is 0, i.e., the RX descriptor ring is idle. The current no-RX data transmission flow ensures no data loss or control confusion in the Ethernet data receiving process.
Wherein the forced write back includes, in response to the write request,
s131, the FPGA soft core sends the initial address and the data length of the data to be written back to the Dcache module through an AHB bus;
s132, the FPGA soft core sends a forced write-back instruction; meanwhile, the FPGA soft core is forcibly suspended, namely, the execution operation of the instruction and the data is suspended;
s133, the Dcache module receives the forced write-back instruction;
s134, the Dcache module scans the Tag of the cache line and judges whether the Tag of the cache line is hit; if the cache line is hit, the cache line is written back to the DDR of the corresponding position; if not, skipping over the cache line; wherein, the hit is the Tag of the data to be written back in the FPGA soft core is consistent with the Tag of the scan cache line of the Dcache module;
s135, the Dcache module scans each cache line and executes the step S134;
and S136, after the forced write-back is finished, feeding back the finishing state information to the FPGA soft core through an AHB bus.
Step S140, after the data updating of the FPGA soft core is finished, the control position of the current TX descriptor is set to be 0 through a control register dmac _ control [3 ].
Preferably, step S140 further includes step S141, the FPGA soft core reads the linker of the current TX descriptor, acquires the next idle TX descriptor, and performs step S120. The FPGA soft core is made to start preparing for the next data transmission by step S141. That is, steps S110 → S120 → S130 → S140, and S141 → S120 → S130 → S140 → S141 reciprocate a loop in which step S141 is identical to step S110, the FPGA soft core locates the position of the currently (next) free TX descriptor on the TX descriptor ring, and the FPGA soft core updates data into the data block corresponding to the DDR and the current (next) TX descriptor.
Step S150, the DMAC sends the data updated to the data block to the ethernet through an ethernet interface.
Preferably, step S150 further includes before step S1500, the DMAC determining whether the control bit of the current TX descriptor is 0, and if the control bit is 0, executing step S150. That is, the DMAC determines whether the control bit of the current TX descriptor is 0, and if the control bit is 0, the DMAC sends the data updated to the data block to the ethernet through the ethernet interface.
The DMAC sending data updated into the data block to the ethernet over an ethernet interface includes,
step S151, reading the data updated to the data block by the DMAC into a data buffer (FIFO); wherein the DMAC reads data from the DDR address pointed to by the start address of the current TX descriptor.
Step S152, after the DMAC data reading is finished, sending the data read to the data buffer one by one according to the sending timing sequence of the ethernet user side.
Step S153, each time data transmission (AXI transmission) is completed, the word counter and the address counter of the DMAC accumulate the number of bytes of the transmitted (actually transmitted) data until the number of bytes of the DMAC is consistent with the number of transmitted bytes included in the current TX descriptor, and complete the data transmission. Wherein the number of transmission bytes comprised by the current TX descriptor, i.e. the data length value in the transmission data length register dmac _ txlen [31:16 ].
Step S160, after the DMAC data transmission is finished, the control position "1" of the current TX descriptor is sent through the control register, and at this time, the current TX descriptor is in an idle state and is in a state that the FPGA soft core can obtain.
Step S170, the DMAC reads the linker of the current TX descriptor, the DMAC determines whether the control bit of the next TX descriptor is 0, if the control bit is 0, then step S150 is executed; otherwise, the DMAC is in a waiting state, that is, the DMAC does not execute step S150 sends the data updated to the data block to the ethernet through the ethernet interface until the control register sends the control position "0" of the current TX descriptor, and then executes step S150.
The DMAC starts sending next data to the ethernet via step S170. That is, steps S1500 → S150(S151 → S152 → S153) → S160 → S170 and steps S170 → S150(S151 → S152 → S153) → S160 → S170 loop back and forth, during which step S1500 and step S170 are identical, the DMAC sends the data updated into the data block to the ethernet via the ethernet interface based on obtaining the current (next) free TX descriptor control bit as 0. When the next idle TX descriptor is obtained and data transmission is started, the next idle TX descriptor is also the current idle TX descriptor.
As described above, step S110(S141) and step S1500(S170) may be performed in synchronization.
Referring to fig. 2, the RX (receive) data transmission flow, i.e. sending ethernet data to the FPGA soft core via DMAC, includes the following steps:
step S210, the DMAC obtains the currently idle RX descriptor. The DMAC obtains a currently idle RX descriptor on the RX descriptor ring, wherein after the initialization procedure, the RX data transmission procedure is performed by default starting from RX descriptor 0.
Step S220, according to the data reception start condition, the DMAC writes the data of the ethernet into the data block corresponding to the current RX descriptor and the DDR. The data receiving starting condition is that a TSMAC _ valid signal in a TSMAC IP user side data interface is pulled high. The TSMAC IP is used for realizing the connection between the MAC in the Ethernet structure and the DMAC through a data bus specified by the TSMAC IP; the TSMAC _ valid is a control signal of the TSMAC IP data bus that is pulled up automatically in the IP, which is an input signal to the DMAC, without the DMAC performing a pull-up operation.
The writing of the data of the ethernet into a data block corresponding to the current RX descriptor by the DMAC includes:
step S221, the DMAC writes the data of the ethernet into a data buffer register. That is, the DMAC directly writes the ethernet valid data into a data buffer register and integrates the ethernet valid data into a data width recognizable by the AXI interface.
Step S222, writing the data written into the data buffer register into the data block corresponding to the current RX descriptor in the DDR through the ping-pong structure.
Step S223, each time data write (AXI transfer) is completed, the word counter and the address counter of the DMAC accumulate the number of bytes of the write (actually transferred) data, and at the same time, count the number of bytes (byte accumulation number) of the write data in one packet/one frame.
Step S230, according to the data reception end condition, the control position of the current RX descriptor is set to "0" through the control register. And the data receiving end condition is that a TSMAC _ rlast signal in a TSMAC IP user side data interface is pulled high. TSMAC _ rlast is a control signal of the TSMAC IP data bus, pulling up automatically in the IP, which is an input signal to the DMAC, without the DMAC performing a pull-up operation.
Furthermore, the control position "0" of the current trace RX descriptor is used by the control register, and meanwhile, the receiving interruption is triggered; i.e. the control register will control the current RX descriptor to "0" and trigger a receive interrupt. And sending a current RX descriptor (descriptor of the current RX descriptor) and the length (byte accumulation) of received data to the FPGA soft core through an interrupt function, and clearing an interrupt after sending.
And S240, reading the data written into the data block by the FPGA soft core. In this step, data written in a data block corresponding to the DDR and the current RX descriptor is read to the FPGA soft core, so that the data of the ethernet is sent to the FPGA soft core.
The reading and writing of the data in the data block by the FPGA soft core specifically comprises the following steps:
step S241, the FPGA soft core receives a current RX descriptor (descriptor of the current RX descriptor) and a data length (byte accumulation);
step S242, when the status register dmac _ states [0] is 0 (no ethernet data reception operation is currently performed), the FPGA soft core reads data written in the data block through DCACHE forced refresh. In this step, the FPGA soft core performs forced refresh by DCACHE according to the received and stored current RX descriptor (descriptor of the current RX descriptor) and data length (byte accumulation), and reads data written in the data block. Wherein the status register dmac _ states [0] is 0, i.e., the RX descriptor ring is idle.
Wherein the forced refresh includes, in response to the request,
s2421, the FPGA soft core sends the initial address and the data length of the data to be refreshed to a Dcache module through an AHB bus;
s2422, the FPGA soft core sends a forced refreshing instruction; meanwhile, the FPGA soft core is forcibly suspended, namely, the execution operation of the instruction and the data is suspended;
s2423, the Dcache module receives the forced refreshing instruction and triggers the Dcache module to carry out forced refreshing operation;
s2424, the Dcache module scans Tag information of the cache line and judges whether the Tag of the cache line is hit; if the Tag corresponding to the cache line is cleared, the cache line is refreshed; if not, skipping over the cache line; wherein, the hit is consistent with the Tag of the data to be refreshed in the FPGA soft core and the Tag of the scanning cache line of the Dcache module;
s2425, the Dcache module scans each cache line and executes the step S2424;
and S2426, after the forced refreshing is finished, feeding back the finishing state information to the FPGA soft core through an AHB bus.
Preferably, step S240 further includes, before step S2400, the DMAC acquiring a link of the current RX descriptor, and performing step S220. The DMAC starts preparing for reception (buffering) of the next data through step S2400, i.e., the DMAC starts preparing for writing the next data transmitted by the ethernet into the data block corresponding to the next RX descriptor of the DDR. Step S210 → S220 → S230, and step S2400 → S220 → S230 → S2400 iterate a loop in which step S2400 is identical to step S210, and the DMAC acquires the currently (next) idle RX descriptor (linker), writes the data transmitted over the ethernet into the data block corresponding to the DDR and current (next) RX descriptors. When the next idle RX descriptor is acquired and data reception is started, the next idle RX descriptor is also the currently idle RX descriptor.
In the loop, the RX data transmission flow is continuously performed (ethernet data is continuously transmitted to the FPGA soft core), and the FPGA soft core needs to open multiple buffer spaces to retain the descriptor and descriptor information of the current (next) RX descriptor.
Step S241, according to the number of times of sending data through ethernet, the FPGA soft core receives and stores an RX descriptor (descriptor of the RX descriptor) and an actually received data length (byte accumulation) each time;
step S242, the FPGA soft core reads the data written in the data block corresponding to the current (next) RX descriptor of the DDR and the current RX descriptor one by one through forced refreshing according to the received and stored RX descriptor and the actually received data length.
Step S250, after the data reading is finished, sending the current RX descriptor to the FPGA soft core through a control register dmac _ control [31:16 ]; control position "1" of the current RX descriptor is set by control register dmac _ control [2 ]. Specifically, after the FPGA soft core finishes reading data, the descriptor of the current RX descriptor is sent to the FPGA through the control register dmac _ control [31:16], and meanwhile, the control position "1" of the current RX descriptor is sent through the control register dmac _ control [2], and the current RX descriptor is in an idle state at this time.
And step S260, the FPGA soft core judges whether unread data exist in the DDR according to the received and stored RX descriptor and the sequence of the data length, if so, the step S240 is executed, and if not, the RX data transmission flow is ended.
Specifically, the FPGA soft core determines whether there is unread (extracted) data in the DDR corresponding to the received RX descriptor according to the sequence of the received and stored RX descriptor and the actually received data length, if so, step S240 is executed, otherwise, the RX data transmission flow is ended.
The FPGA soft core starts to prepare for reading of the next (cached) data, that is, the FPGA soft core starts to prepare for reading data written in the data block corresponding to the next RX descriptor by the DDR in step S260. Step S240 → S250 → S260, and step S260 → S240 → S250 → S260, are repeated, during which the FPGA soft core reads all data written in the data block corresponding to the DDR and the next RX descriptor, so far that the RX data transfer flow ends.
In the above, step S210(S2400) and step S240 may be performed in synchronization.
Further, the embedded ethernet data processing method further includes an RX packet loss mechanism, that is, when the DMAC receives the ethernet data, a new (received) data packet is discarded without changing the control bit state of the descriptor ring. Wherein, the packet discarding includes the following conditions:
1) RX descriptor ring initialization is not complete;
2) RX status is busy;
3) DCACHE forced refresh or forced write back is being performed;
4) there is no idle RX descriptor.
The embedded ethernet data processing method based on FPGA of the embodiments of the present invention further includes an initialization process before an RX (receive) data transmission process and a TX (transmit) data transmission process, specifically:
step S010, the FPGA soft core sends the descriptor (TX descriptor and RX descriptor) which needs to be initialized currently in the TX descriptor ring and the RX descriptor ring to the DMAC through a descriptor register descriptor _ num [31:16] and a descriptor register descriptor _ num [15:0 ];
step S020, the FPGA soft core sequentially sends descriptor information such as descriptor control register descriptor _ ctrl [31:16] (TX), descriptor receiving start address descriptor _ txaddr, descriptor data length descriptor _ len [31:16] (TX), descriptor control register descriptor _ ctrl [15:0] (RX), descriptor receiving start address descriptor _ rxaddr, descriptor data length descriptor _ len [15:0] (RX) and the like corresponding to the current descriptor (TX descriptor and RX descriptor) to the DMAC;
step S030, the FPGA soft core sends data of a control register DMAC _ control [31:16] to the DMAC, and when the DMAC receives 2' b11, the TX descriptor ring and the RX descriptor ring simultaneously send initialization information; when the DMAC receives 2' b01, only the TX descriptor ring sends initialization information at this time; when the DMAC receives 2' b10, only the RX descriptor ring sends initialization information at the same time;
step S040, the DMAC completes the initialization configuration of the received descriptor according to the descriptor (descriptor) and descriptor information of the TX descriptor ring and/or RX descriptor ring received;
step S050, if all descriptors (descriptors) on the TX descriptor ring and/or the RX descriptor ring are not initialized completely, repeating step S01; if all the descriptors (descriptors) in the TX descriptor ring and/or RX descriptor ring are initialized, the initialization process is terminated, and the initial done is sent to the DMAC through the status register DMAC _ states [1 ].
In the embedded ethernet data processing method based on the FPGA of the embodiment of the present invention, during the process of sending/receiving data of the FPGA soft core and the ethernet, the DMAC is used to enable the ethernet and the off-chip storage device (e.g., DDR) to directly transmit a large amount of data without passing through the FPGA soft core, thereby overcoming the problem that the processing capability of the FPGA soft core is not sufficient to match the communication rate of the ethernet. Furthermore, when the Ethernet data is updated and the FPGA soft core data is written back, DCACHE forced refreshing and forced write back operation are synchronously matched, and the CACHE consistency problem is solved.
Referring to fig. 3 and fig. 4, an embodiment of the present invention further provides an embedded ethernet data processing system based on an FPGA, which includes an FPGA soft core, a DMAC, and a DDR, where the FPGA soft core communicates with the DMAC through an AHB bus, and the FPGA soft core controls the DMAC through the AHB bus; the DMAC and DDR communicate over an AXI bus. The FPGA soft core and the DMAC are arranged on the embedded SoC, and the embedded SoC also comprises a Dcache module.
The DMAC performs read-write operations of initialization and other registers through an AHB bus, and issues or uploads related initialization, control and state information; and the direct communication between the Ethernet (Ethernet) and the DDR is carried out by utilizing the register, and the conversion of the AXI4 bus interface and the Ethernet (Ethernet) interface and the AXI4 arbitration are simultaneously realized.
The DMAC adopts a full duplex mode and comprises a soft core control module, a DMA communication control module, a TX descriptor ring and an RX descriptor ring, wherein the hardware structures of the TX descriptor ring (TX ring) and the RX descriptor ring (RX ring) are independent and can be performed simultaneously.
The soft core control module is used for the FPGA soft core to control TX and/or RX of the DMAC, exchange of TX and/or RX actual data packet length, and initialization of TX descriptor ring and RX descriptor ring information reception. The DMA communication control module is used for DDR data and Ethernet (Ethernet) data caching, AXI4 address/byte count storage and AXI4 address/data format integration, and simultaneously utilizes descriptor control logic to initialize and state control a TX descriptor ring and an RX descriptor ring. The TX descriptor ring and the RX descriptor ring are used to store control bits, a linker, a packet address, and packet length information of the TX descriptor ring and the RX descriptor ring of the DMAC, respectively.
TX descriptor ring and RX descriptor ring (TX descriptor and RX descriptor) structure: { control bit (empty _ flag), chaining symbol (Link), packet start address, packet length }; wherein the control bit indicates whether the descriptor is empty; the linker represents the next descriptor; the starting address of the data packet represents the starting address of the buffer area corresponding to the descriptor; the packet length indicates the size of the buffer space corresponding to the descriptor.
Since TX (transmit) data is actively initiated for the FPGA soft core, in combination with the processing capability of the system, the TX descriptor ring in the embodiment of the present invention includes a level 2 TX descriptor, and TX sets a linker to be sequentially executed for TX descriptor 0 and TX descriptor 1, that is, TX is 0-1-0.
In order to match the rate of gigabit ethernet, in the embodiment of the present invention, the RX descriptor ring has at most 1024 levels of RX descriptors; RX sets the linker to sequential execution, i.e., RX is 0-1-2- … -1023-0.
The embedded Ethernet data processing system of the embodiment of the invention also comprises a series of registers, so that the DMAC and the FPGA soft core can carry out normal information interaction.
Specifically, the DMAC is divided into a series of registers by different AHB addresses, and as shown in table 1, the series of registers include: status register dmac _ states [1], control register dmac _ control [1:0], descriptor register descriptor _ num, descriptor control register descriptor _ ctrl, descriptor transmission start address descriptor _ txaddr, descriptor reception start address descriptor _ rxaddr, descriptor data length descriptor _ len.
TABLE 1 register List
The embedded ethernet data processing system according to the embodiment of the present invention further includes the above-mentioned embedded ethernet data processing method, which includes a TX (transmission) data transmission flow and an RX (reception) data transmission flow, and the repetition is not repeated.
The DMAC is used for TX (transmit) data transfer flow: under the control of the FPGA soft core (Cortex M1 is adopted in the example), data generated by the FPGA soft core is forcedly written back to a convention (corresponding to a descriptor) position in the DDR particle through DCACHE, and then the updated data in the DDR particle is sent to the Ethernet through the DMAC.
The DMAC is used for RX (receive) data transmission flow: under the control of the FPGA soft core (in this example, Cortex M1 is adopted), the data of the Ethernet is directly written into an appointed (corresponding to a descriptor) position in the DDR particle through the DMAC, and then the data of the Ethernet is read into the FPGA soft core for processing through DCACHE forced refreshing.
The embedded Ethernet data processing system of the embodiment of the invention realizes an FPGA soft core system with Ethernet DMAC in FPGA, so as to match the application requirement of Ethernet communication rate and provide hardware basis for LwIP and other communication protocol stacks; and, the embodiment of the invention establishes reasonable TX descriptor ring and RX descriptor ring structure and hardware packet loss mechanism, and prevents the system jam or error phenomenon caused by insufficient processing capacity of Ethernet DMAC.
While the foregoing is directed to embodiments of the present invention, it will be understood by those skilled in the art that various changes may be made without departing from the spirit and scope of the invention.
Claims (10)
1. A data processing method based on FPGA is characterized in that the data processing method is to send the data of Ethernet to FPGA soft core through DMAC, and comprises the following steps:
step S10, the DMAC obtaining the current idle descriptor;
step S20, according to the data receiving start condition, the DMAC writes the data of the ethernet into the data block corresponding to the current descriptor of the DDR,
step S30, according to the data reception end condition, the control position "0" of the current descriptor is set by the control register;
and step S40, the FPGA soft core reads the data written in the data block.
2. The FPGA-based data processing method of claim 1, wherein in step S20, the data reception starting condition is that a TSMAC _ rvald signal in a TSMAC IP user-side data interface is pulled high; in step S30, the data reception end condition is that the TSMAC _ rlast signal in the TSMAC IP user-side data interface is pulled high.
3. The FPGA-based data processing method of claim 1, wherein in step S20, writing the data of the ethernet into the data block corresponding to the current descriptor by the DMAC includes:
step S21, the DMAC writes the ethernet data into a data buffer register;
and step S22, writing the data written into the data buffer register into the DDR particles through a ping-pong structure.
4. The FPGA-based data processing method of claim 3, wherein step S40 is preceded by the DMAC obtaining a link of a current descriptor and performing step S20.
5. The FPGA-based data processing method of claim 1, wherein the step S40 is specifically,
step S41, the FPGA soft core receives the current descriptor and the data length;
and step S42, reading the data written into the data block by the FPGA soft core through forced refreshing.
6. The FPGA-based data processing method of claim 1, wherein after the step S40, the data processing method further comprises,
step S50, after data are read, sending the current descriptor to the FPGA through a control register; meanwhile, the control position of the current descriptor is '1' through the control register;
step S60, the DMAC obtains the link of the current descriptor, and the DMAC determines whether the control bit of the next descriptor is 0, and if the control bit is 0, executes step S40.
7. The FPGA-based data processing method of claim 1, further comprising the steps of:
step S01, the FPGA soft core sends the descriptor which needs to be initialized to the DMAC;
step S02, the FPGA soft core sends the descriptor information of the current descriptor to the DMAC;
step S03, the DMAC completes initialization configuration according to the received descriptor and the descriptor information;
step S04, if all the descriptors are not initialized, repeating the step S01; if all the descriptors are initialized completely, the initialization process is finished, and the initial done is sent to the DMAC through the state register.
8. A data processing system based on FPGA is characterized by comprising an FPGA soft core, a DMAC and a DDR, wherein the FPGA soft core is communicated with the DMAC through an AHB bus, and the DMAC is communicated with the DDR through an AXI bus; the DMAC includes an RX descriptor ring;
the data processing system further comprises the FPGA-based data processing method in any claim of 1 to 7 applied to the data processing system.
9. The FPGA-based data processing system of claim 8 wherein said RX descriptor ring comprises 1024 level RX descriptors.
10. The FPGA-based data processing system of claim 9 wherein said RX descriptors include control bits, chaining symbols, packet addresses and packet length information.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011016308.7A CN112347028A (en) | 2020-09-24 | 2020-09-24 | Data processing method and system based on FPGA |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011016308.7A CN112347028A (en) | 2020-09-24 | 2020-09-24 | Data processing method and system based on FPGA |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN112347028A true CN112347028A (en) | 2021-02-09 |
Family
ID=74358159
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011016308.7A Pending CN112347028A (en) | 2020-09-24 | 2020-09-24 | Data processing method and system based on FPGA |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112347028A (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1761222A (en) * | 2005-11-22 | 2006-04-19 | 华中科技大学 | Storage network adapter of supporting virtual interface |
| CN101198924A (en) * | 2005-02-03 | 2008-06-11 | Level5网络有限公司 | Including descriptor queue empty events in completion events |
| CN106210172A (en) * | 2016-07-25 | 2016-12-07 | 哈尔滨工业大学 | Ethernet data IP address high speed sorter |
| CN107341053A (en) * | 2017-06-01 | 2017-11-10 | 深圳大学 | The programmed method of heterogeneous polynuclear programmable system and its memory configurations and computing unit |
| CN109634881A (en) * | 2018-11-16 | 2019-04-16 | 中国航空工业集团公司洛阳电光设备研究所 | A kind of gigabit Ethernet DMA data transfer design device based on FPGA |
-
2020
- 2020-09-24 CN CN202011016308.7A patent/CN112347028A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101198924A (en) * | 2005-02-03 | 2008-06-11 | Level5网络有限公司 | Including descriptor queue empty events in completion events |
| CN1761222A (en) * | 2005-11-22 | 2006-04-19 | 华中科技大学 | Storage network adapter of supporting virtual interface |
| CN106210172A (en) * | 2016-07-25 | 2016-12-07 | 哈尔滨工业大学 | Ethernet data IP address high speed sorter |
| CN107341053A (en) * | 2017-06-01 | 2017-11-10 | 深圳大学 | The programmed method of heterogeneous polynuclear programmable system and its memory configurations and computing unit |
| CN109634881A (en) * | 2018-11-16 | 2019-04-16 | 中国航空工业集团公司洛阳电光设备研究所 | A kind of gigabit Ethernet DMA data transfer design device based on FPGA |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6115779A (en) | Interrupt management system having batch mechanism for handling interrupt events | |
| CN106155960B (en) | It is shaken hands the UART serial port communication method with EDMA based on GPIO | |
| JP4427214B2 (en) | Interface unit for transfer between host processor and digital signal processor in asynchronous transfer mode, and data processing system using the same | |
| US6581113B1 (en) | Apparatus and method for transferring frame data between a host system memory and a network interface buffer memory employing transmit descriptors without transmit status information | |
| KR101817932B1 (en) | Providing command queuing in embedded memories | |
| US6223305B1 (en) | Method and apparatus for resetting, enabling and freezing a communication device in a diagnostic process | |
| US6047001A (en) | Apparatus and method in a network interface device for storing a data frame and corresponding tracking information in a buffer memory | |
| US6970921B1 (en) | Network interface supporting virtual paths for quality of service | |
| US6345345B1 (en) | Data communications device and associated method for arbitrating access using dynamically programmable arbitration scheme and limits on data transfers | |
| CN111221759B (en) | Data processing system and method based on DMA | |
| US6434161B1 (en) | UART with direct memory access buffering of data and method therefor | |
| CN112347030A (en) | Data processing method and system based on FPGA | |
| US6154796A (en) | Apparatus and method in a network interface device for storing receiving frame status in a holding register | |
| CN109981431A (en) | A kind of CAN controller data storage circuitry and date storage method | |
| CN106959929B (en) | Multi-port access memory and working method thereof | |
| US7065582B1 (en) | Automatic generation of flow control frames | |
| CN111274173A (en) | ZYNQ-based multi-node SRIO communication design method and device | |
| JP3785373B2 (en) | Communication control circuit | |
| US6401142B1 (en) | Apparatus and method for selective bus transfer using master and slave modes | |
| US6061768A (en) | Apparatus and method in a network interface device for storing tracking information indicating stored data status between contending memory controllers | |
| US6516371B1 (en) | Network interface device for accessing data stored in buffer memory locations defined by programmable read pointer information | |
| US6061767A (en) | Apparatus and method in a network interface device for storing status information contiguous with a corresponding data frame in a buffer memory | |
| US6526370B1 (en) | Mechanism for accumulating data to determine average values of performance parameters | |
| CN103838694B (en) | FPGA high-speed USB interface data reading method | |
| WO1997041514A1 (en) | Qualified burst buffer |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20210209 |
|
| RJ01 | Rejection of invention patent application after publication |