CN112332808B - FPGA-based digital processing circuit for mixing integration and high-pass filtering - Google Patents
FPGA-based digital processing circuit for mixing integration and high-pass filtering Download PDFInfo
- Publication number
- CN112332808B CN112332808B CN202011237551.1A CN202011237551A CN112332808B CN 112332808 B CN112332808 B CN 112332808B CN 202011237551 A CN202011237551 A CN 202011237551A CN 112332808 B CN112332808 B CN 112332808B
- Authority
- CN
- China
- Prior art keywords
- floating
- point
- multiplier
- adder
- result
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H17/00—Networks using digital techniques
- H03H17/02—Frequency selective networks
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H17/00—Networks using digital techniques
- H03H17/02—Frequency selective networks
- H03H2017/0298—DSP implementation
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Mathematical Physics (AREA)
- Complex Calculations (AREA)
Abstract
The invention discloses a designed digital processing circuit mixing integration and high-pass filtering, which comprises a fixed-point floating-point converter, a floating-point subtracter, a FIFO, a first floating-point adder, a first floating-point multiplier, a second floating-point adder, a second floating-point multiplier, a first register, a second register, a first counter, a second counter, a parameter input selector and a control circuit. The invention can realize the integral filtering function of the lightning signal. The invention realizes the lightning signal processing by the mixed design of the integration function and the high-pass filtering function based on the DSP and the FPGA technology, and solves the problem of the distortion of the short-distance and high-strength lightning signal processing.
Description
Technical Field
The invention belongs to the technical field of lightning signal positioning (measurement), and particularly belongs to a digital processing circuit for mixing integration and high-pass filtering based on an FPGA (field programmable gate array).
Background
A signal front-end signal processing unit of a traditional lightning positioning system is constructed by an analog circuit, and the functions of the signal front-end signal processing unit sequentially comprise signal amplification, low-pass filtering, integration and high-pass filtering. The front-end signal processing unit built by the analog circuit avoids the problems of low signal-to-noise ratio caused by low strength of lightning electromagnetic field signals acquired by the antenna and high interference of background noise to a great extent. However, in the actual operation process of the analog circuit, when the lightning signal is close and the lightning electromagnetic field strength is large, the lightning signal entering the a/D conversion chip exceeds the input dynamic range thereof to cause signal distortion, and the requirements of a subsequent digital signal processing circuit cannot be met.
Disclosure of Invention
The invention aims to provide a digital processing circuit which is used for solving the technical defects of a signal front-end signal processing unit of a traditional thunder and lightning positioning system and is based on an FPGA (field programmable gate array) and used for mixing integration and high-pass filtering, and the digital processing circuit is used for replacing the integration and high-pass filtering unit for processing signals at the front end of the traditional thunder and lightning positioning system.
In order to achieve the purpose, the technical scheme adopted by the invention is as follows:
a digital processing circuit for mixing integration and high-pass filtering based on FPGA comprises a fixed point floating point converter, a floating point subtracter, a FIFO, a first floating point adder, a first floating point multiplier, a second floating point adder, a second floating point multiplier, a first register, a second register, a first counter, a second counter, a parameter input selector and a control circuit.
In the integrated and high-pass filtering function mixed digital processing circuit, input signals a (n) are subjected to integration
Obtaining a signal x (n), filtering the integrated signal x (n) to obtain a required digital signal y (n), wherein the filtering process adopts a Butterworth filtering method.
The integration and high-pass filtering function mixed digital processing method has the theoretical basis of a Butterworth filtering equation
The equation is an N-order differential equation of a direct network structure, wherein i is an order number and c isi、biX (n-i) is the integrated input signal a (n), y (n-i) is the output result,
selecting a second order butterworth high pass filter, at which time coefficient c01, the butterworth filter equation is developed to obtain the formula y (n) ═ c1y(n-1)+c2y(n-2)+b0x(n)+b1x(n-1)+b2x(n-2)，
The digital integral output signal can be expanded into a formula
Coefficient constant b when second order butterworth high pass filtering is used0＝1，b1＝-2，b31, second order butterworth high pass filter equation b0x(n)+b1x(n-1)+b2x(n-2)＝a(n)-a(n-1)，
Then the formula y (n) ═ c1y(n-1)+c2y(n-2)+a(n)-a(n-1)。
The fixed point and floating point converter is used for converting the number of the input fixed points into the number of the floating point, and the result is output to the floating point subtracter.
The floating-point subtracter is used for carrying out subtraction operation on Input signals and taking the result obtained by operation as the Input of a First Input First Output (FIFO);
the FIFO buffers the input signal and sequentially outputs the stored numerical values to the first floating-point adder under the control of the control circuit (counter).
The first floating-point adder is used for operating the results output by the FIFO and the first floating-point multiplier and outputting the operation result to the second floating-point adder.
And the second floating-point adder is used for operating the results output by the first floating-point adder and the second floating-point multiplier and outputting the results to the first register at the same time.
The first register is used for storing the result output by the second adder and outputting the result to the first multiplier and the second multiplier simultaneously.
The first multiplier is used for operating the first register and the parameter input result and outputting the operation result to the first adder.
And the second multiplier is used for operating the first register and the parameter input result and outputting the operation result to the second adder.
The control circuit mainly comprises two counters, a plurality of sequential logics and reset logics, and is used for controlling the working state of the whole integration high-pass hybrid circuit.
The first register is used for storing the final output result of the whole circuit.
The parameter selector is used for receiving a parameter setting command sent by the main controller and inputting the selected parameters into the first multiplier and the second multiplier respectively.
The main controller is a DSP (Digital Signal Processor).
Compared with the prior art, the technical scheme provided by the invention has the following beneficial effects: the invention mixes the digital integral and the Butterworth second-order high-pass filtering formula, thereby realizing the functions of integral and high-pass filtering and avoiding the problem of direct current bias caused by the adoption of accumulation summation to realize the digital integral function; the working frequency of the circuit is effectively reduced, and the difficulty that a Butterworth filter is very difficult to realize high-speed assembly line design is avoided; the use of a floating-point adder and a floating-point subtracter is reduced, and FPGA resources are saved; and fourthly, the defect that signal distortion is caused when the distance of the lightning signals is short and the strength of the lightning electromagnetic field is large due to integral operation in an analog circuit is overcome because the lightning signals entering the A/D conversion chip exceed the input dynamic range of the A/D conversion chip.
Drawings
FIG. 1 is a circuit diagram of an integrated high-pass filter hybrid design digital circuit according to the present invention.
FIG. 2 is an example of the amplitude-frequency characteristic of the integrated high-pass filter hybrid design digital circuit of the present invention.
Detailed Description
The terms "first," "second," "third," "fourth," and the like in the description and in the claims, as well as in the drawings, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order.
As shown in fig. 1, a digital signal processing circuit based on FPGA for implementing a hybrid design of integration and high-pass filtering functions includes a fixed-point floating-point converter, a floating-point subtractor, a FIFO, a first floating-point adder, a first floating-point multiplier, a second floating-point adder, a second floating-point multiplier, a first register, a second register, a first counter, a second counter, and a parameter input selector.
The integration and high-pass filtering function hybrid design circuit simultaneously realizes the integration and high-pass filtering functions.
Digital integral output signal
Where Δ t is the time interval.
Digital integration, filtering output signal y (n) ═ c1y(n-1)+c2y(n-2)+a(n)-a(n-1)。
FIG. 2 is a simulation result of amplitude-frequency characteristics based on MATLAB and shown as a formula, wherein c1The value is-1.9997778558, c2A value 0.9997778805, c given by the parameter selector as the cut-off frequency of the high-pass filter function varies in practical application1、c2The values are different, and the corresponding characteristics of the corresponding amplitude and frequency are correspondingly changed.
The fixed point floating point converter is used for converting an input 16-bit signed complementary binary format fixed point number into a 32-bit signed floating point number conforming to an IEEE754 format, and a result is output to the floating point subtracter so as to meet the requirement that the whole circuit adopts floating point operation.
The floating-point subtracter is used for carrying out subtraction operation on input signals to realize a (n) -a (n-1) part in the integration high-pass mixing type, and the operation result is used as the input of the FIFO.
The FIFO buffers input signals and sequentially outputs stored numerical values to the first floating-point adder under the control of the control circuit (counter), so that data interaction in different time domains is met.
The first floating-point adder is used for operating the results output by the FIFO and the first floating-point multiplier to realize c in the formula2Y (n-2) + a (n) -a (n-1), and outputs the operation result to the second floating-point adder.
The second floating-point adder is used for operating the results output by the first floating-point adder and the second floating-point multiplier to realize c in the formula1*y(n-1)+c2Y (n-2) + a (n) -a (n-1) and outputs the result to the first register simultaneously.
The first register is used for storing the result output by the second adder, and realizing the synchronous output of the result and the parameter of the parameter selector to the first multiplier and the second multiplier.
The first floating-point multiplier is used for operating the output numerical values of the first register and the parameter selector to realize c in the formula2Y (n-2) and outputs the operation result to the first adder.
The second floating-point multiplier is used for operating the output numerical values of the first register and the parameter selector to realize c in the formula1Y (n-1) and outputs the operation result to the second adder.
The control circuit mainly comprises two counters, a plurality of sequential logics and reset logics, and is used for controlling the output time of the FIFO result in the whole integration high-pass mixing circuit, the data input time of the first adder and the second adder, the extraction time of the calculated output result, and the reset and initialization time of the two adders. The control circuit also samples and extracts the calculation result of the second adder as the final output result of the whole circuit, namely y (n). The first register is used for storing the final output result y (n) of the whole circuit and meeting the requirement of data interaction in different time domains.
The parameter selector is used for receiving a parameter setting command sent by the main controller and inputting the selected parameters into the first multiplier and the second multiplier respectively.
The main controller is a Digital Signal Processor (DSP).
Those not described in detail in this specification are within the knowledge of those skilled in the art.
Claims (2)
1. A digital processing circuit for mixing integration and high-pass filtering based on FPGA is characterized in that the circuit comprises a fixed point floating point converter, a floating point subtracter, an FIFO, a first floating point adder, a first floating point multiplier, a second floating point adder, a second floating point multiplier, a first register, a second register, a first counter, a second counter, a parameter input selector and a control circuit;
in the integrated and high-pass filtering function mixed digital processing circuit, an input signal a (n) is integrated to obtain a signal x (n), the integrated signal x (n) is filtered to obtain a required digital signal y (n), and a Butterworth filtering method is adopted in the filtering process;
the fixed point and floating point converter is used for converting the number of the input fixed points into the number of the floating points, and the result is output to the floating point subtracter; the floating-point subtracter is used for carrying out subtraction operation on Input signals and taking the result obtained by operation as the Input of a First Input First Output (FIFO);
the FIFO buffers input signals and sequentially outputs stored numerical values to the first floating-point adder under the control of the control circuit;
the first floating-point adder is used for operating the results output by the FIFO and the first floating-point multiplier and outputting the operation result to the second floating-point adder; the second floating-point adder is used for operating the results output by the first floating-point adder and the second floating-point multiplier and outputting the results to the first register at the same time; the first register is used for storing the result output by the second adder and outputting the result to the first multiplier and the second multiplier simultaneously; the first multiplier is used for operating the first register and the parameter input result and outputting the operation result to the first adder; the second multiplier is used for operating the first register and the parameter input result and outputting the operation result to the second adder;
the control circuit comprises two counters, a plurality of sequential logics and reset logics and is used for controlling the working state of the whole integration high-pass hybrid circuit;
the first register is used for storing the final output result of the whole circuit;
the parameter selector is used for receiving a parameter setting command sent by the main controller and inputting the selected parameters into the first multiplier and the second multiplier respectively.
2. The FPGA-based digital processing circuit that combines integration and high-pass filtering according to claim 1, wherein a theoretical basis of a processing method of the processing circuit is a butterworth filter equation
The equation is an N-order differential equation of a direct network structure, wherein i is an order number and c isi、biX (n-i) is the integrated input signal a (n), y (n-i) is the output of the digital processing circuit,
selecting a second order butterworth high pass filter, at which time coefficient c01, the butterworth filter equation is developed to obtain the formula y (n) ═ c1y(n-1)+c2y(n-2)+b0x(n)+b1x(n-1)+b2x(n-2)，
The digital integral output signal can be expanded into a formula
Where at is the time interval between the start of the cycle,
coefficient constant b when second order butterworth high pass filtering is used0＝1，b1＝-2，b31, second order butterworth high pass filter equation b0x(n)+b1x(n-1)+b2x(n-2)＝a(n)-a(n-1)，
Then the formula y (n) c1y(n-1)+c2y(n-2)+a(n)-a(n-1)。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011237551.1A CN112332808B (en) | 2020-11-09 | 2020-11-09 | FPGA-based digital processing circuit for mixing integration and high-pass filtering |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011237551.1A CN112332808B (en) | 2020-11-09 | 2020-11-09 | FPGA-based digital processing circuit for mixing integration and high-pass filtering |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112332808A CN112332808A (en) | 2021-02-05 |
| CN112332808B true CN112332808B (en) | 2022-05-31 |
Family
ID=74315548
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011237551.1A Active CN112332808B (en) | 2020-11-09 | 2020-11-09 | FPGA-based digital processing circuit for mixing integration and high-pass filtering |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112332808B (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08162906A (en) * | 1994-11-30 | 1996-06-21 | Canon Inc | Digital signal processor |
| WO2001039032A1 (en) * | 1999-11-11 | 2001-05-31 | Voyan Technology | Method for design and implementation of fixed-point filters for control and signal processing |
| CN101253475A (en) * | 2005-08-31 | 2008-08-27 | 密克罗奇普技术公司 | Programmable digital filter |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7139146B2 (en) * | 2002-05-28 | 2006-11-21 | Sony Corporation | Signal processing apparatus and method, and digital data reproducing apparatus |
-
2020
- 2020-11-09 CN CN202011237551.1A patent/CN112332808B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08162906A (en) * | 1994-11-30 | 1996-06-21 | Canon Inc | Digital signal processor |
| WO2001039032A1 (en) * | 1999-11-11 | 2001-05-31 | Voyan Technology | Method for design and implementation of fixed-point filters for control and signal processing |
| CN101253475A (en) * | 2005-08-31 | 2008-08-27 | 密克罗奇普技术公司 | Programmable digital filter |
Non-Patent Citations (2)
| Title |
|---|
| ASIC design of IIR butterworth digital filter for electrocardiogram;Ranjeet Singh Chauhan;《2017 8th International Conference on Computing, Communication and Networking Technologies (ICCCNT)》;20171231;1-6 * |
| 基于DSP+FPGA技术的两点法非均匀校正模块设计;国网电力科学研究院武汉南瑞有限责任公司;《红外》;20041231;7-11 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN112332808A (en) | 2021-02-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| WO2018188228A1 (en) | High-precision frequency measuring system and method | |
| CN104467739B (en) | The adjustable digital filter of a kind of bandwidth, center frequency point and its implementation | |
| Liu et al. | Design and FPGA implementation of a reconfigurable digital down converter for wideband applications | |
| CN112332808B (en) | FPGA-based digital processing circuit for mixing integration and high-pass filtering | |
| JPH06244679A (en) | Digital filter circuit | |
| CN105187068B (en) | A kind of modulation circuit and modulator approach | |
| Li | Design and realization of FIR digital filters based on MATLAB | |
| CN101594159A (en) | A kind of method of digital front-end filtering and device | |
| CN204290909U (en) | The digital filter that a kind of bandwidth, center frequency point are adjustable | |
| CN106872948B (en) | Radar working channel acquisition system and method based on two-stage digital down-conversion | |
| CN103580647A (en) | Filter structure | |
| CN103916143B (en) | The non-contour step signal processing method of very low frequency long-wave transmitter and device | |
| CN111404513A (en) | CIC decimation filter and implementation method thereof | |
| CN113295917A (en) | Protection device sampling unit based on combination of Rogowski coil and LPCT | |
| CN201682468U (en) | Self-adaptive low-pass digital filter for variable frequency signals | |
| CN105578083B (en) | Low noise CCD image formation electronic system | |
| Madheswaran et al. | Implementation And Comparison Of Different CIC Filter Structure For Decimation | |
| RU2784002C1 (en) | Processor for digital quadrative separation | |
| CN113328749B (en) | Analog-to-digital conversion device | |
| DE20306564U1 (en) | Device for providing a multimode interface between a baseband receiver and high-frequency circuits | |
| CN111835314B (en) | Anti-interference extractor for extracting 1-2 times of any multiple and design method thereof | |
| CN202998021U (en) | Multichannel comb filter | |
| CN201497978U (en) | high-precision four-quadrant multiplier | |
| Peng et al. | Design of Multi-Rate Digital Filter for Sigma-Delta Adc in Digital Microphone | |
| CN108683414B (en) | Universal filter |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |