CN112329372A - Method for generating code pattern for signal integrity analysis - Google Patents
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- G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
Abstract
The invention discloses a method for generating a code pattern for signal integrity analysis, which comprises the steps of reading a signal full-link S parameter model, determining crosstalk sequencing of bit positions in each high-speed interface, and determining an attacked corresponding to each signal line according to the maximum number of the attacked of a victim signal; generating a PRBS seed code pattern to enable the PRBS seed code pattern to contain the worst intersymbol interference effect, and rewriting the PRBS seed code pattern into a code pattern a; generating a code pattern b containing crosstalk of each signal by taking the code pattern a as a seed code pattern; and reading an S parameter model or PDN impedance resonant frequency of the PDN link, and performing post-processing on the code pattern b to generate a code pattern c comprising worst power supply noise. The invention can simulate the worst result of PRBS code pattern theory, and can accurately simulate the signal quality of the high-speed interface full link, thereby solving the defects that the traditional method can not consider power supply noise and has precision problem, ensuring that the acceptance design basis of the high-speed interface full link is more reliable, avoiding over-design or under-design and saving the design cost.
Description
Technical Field
The invention discloses a method for generating a code pattern for signal integrity analysis, relates to a transistor-level simulation analysis code pattern of a high-speed interface circuit, and belongs to the technical field of electronics.
Background
Signal Integrity (SI) is a task of performing simulation analysis on a high-speed interface full link to evaluate whether Signal quality meets design requirements, generally, effects such as power supply noise, Signal link crosstalk, reflection, loss and the like need to be comprehensively considered, and finally, the width and height of an eye pattern after superposition are taken as a judgment basis.
High speed interface full link SI simulation may be performed based on a behavioral IBIS model of IO or a transistor level SPICE netlist. The IBIS model has the advantages of high speed, hidden design internal details and the like, but the IBIS model cannot process signal jitter caused by power supply noise, and meanwhile, because the IBIS model adopts a mode similar to table lookup according to edges in the circuit simulation tool processing, the IBIS model cannot correctly process signal input subjected to pre-emphasis processing. In addition, the IBIS model cannot effectively handle the influence of link feedback on IO performance like the transistor-level SPICE model. Therefore, SI simulation based on the IBIS model can be iterated quickly in the early design stage or in the design, but acceptance simulation is performed in the middle and later design stages, and the transistor-level SPICE model is still irreplaceable. The transistor-level SPICE model is the model which can most accurately simulate the actual working performance of a high-speed link, and the defects of the IBIS model can be overcome. However, since the transistor itself is a nonlinear device, it is time-consuming in simulation of SPICE circuit, especially in an iosspice netlist containing chip wiring parasitic parameters, the scale of netlist nodes can reach millions, the complexity is very high in multi-IO simulation, and the simulation efficiency is low.
Another major factor that results in poor SI simulation feasibility based on transistor-level SPICE netlists is the length of the simulation pattern. SI simulation needs to comprehensively consider the influence of power supply noise, crosstalk, ISI, etc., and needs to simulate a sufficiently long pattern to obtain the worst case. The short pattern is not representative and may make the result too optimistic. A typical 32-bit LPDDR4X interface uses a PRBS code pattern with a length of several thousand bits, a transistor-level SPICE netlist needs about one week when being simulated on a current mainstream server, the iteration efficiency is very low, and the chip design progress is seriously influenced if setting errors and other conditions occur. Thus, in high speed interface link SI simulation, although its accuracy is generally accepted as being the best, SI simulation based on transistor-level SPICE netlist is generally considered inefficient or very low feasible.
Disclosure of Invention
In order to solve the problems of low precision of the IBIS model and low efficiency of the transistor-level model, the invention provides a method for generating a code pattern for signal integrity analysis. The design of the code pattern comprehensively considers the superposition influence of factors such as intersymbol interference, crosstalk noise, power supply noise and the like on the signal quality, thereby ensuring that the worst simulation result is obtained by the shortest code pattern and greatly improving the integrity analysis efficiency of the high-speed interface full-link signal based on the transistor level.
In order to achieve the purpose, the technical scheme provided by the invention is as follows:
a method for generating a pattern for signal integrity analysis, comprising the steps of: firstly, reading a signal link S parameter model, determining the crosstalk sequencing of each bit of each high-speed interface, and determining an attacker corresponding to each signal line according to the maximum attacker number of the victim signals.
Next, a PRBS seed pattern is generated, and the pattern a is rewritten to include the worst intersymbol interference effect.
Then, a crosstalk pattern b of each signal is generated using the pattern a as a seed pattern. If only the eye pattern quality of a certain signal needs to be concerned, only a code pattern needs to be generated for the signal; if eye quality of all signals needs to be taken care of, then patterns need to be generated and concatenated for all signals.
And finally, reading an S parameter model or PDN impedance resonant frequency of the PDN link, and performing post-processing on the code pattern b to generate a code pattern c containing the worst power supply noise effect.
Compared with the traditional signal integrity simulation code pattern, the method has the following advantages:
1. the design of the code pattern comprehensively considers the superposition influence of factors such as intersymbol interference, crosstalk noise, power supply noise and the like on the signal quality, and ensures that the theoretically worst signal eye pattern quality of a given channel can be obtained by using the signal integrity simulation of the code pattern.
2. The code patterns provided by the invention need to be superposed and compiled in order to realize the superposition influence of factors such as intersymbol interference, crosstalk noise, power supply noise and the like, and the various effects are not simply cascaded or directly used by a PRBS long code pattern with a higher order like the traditional code pattern, so the length of the code pattern provided by the invention is short enough.
3. 1 and 2 are combined, the code pattern provided by the invention has the best code pattern in the aspects of checking and accepting design efficiency and quality, so that the transistor-level high-speed interface full-link signal integrity simulation checking and accepting design efficiency is greatly improved, and the feasibility is enhanced.
Drawings
In order to make the object, technical scheme and beneficial effect of the invention more clear, the invention provides the following drawings for explanation:
FIG. 1 is a flow chart of an embodiment of the present invention;
FIG. 2 is a schematic diagram of various types of simulation code patterns involved in the implementation of the present invention, where FIG. 2(a) is a PRBS code pattern, FIG. 2(b) is an ISI code pattern, FIG. 2(c) is an even-mode crosstalk code pattern, FIG. 2(d) is an odd-mode crosstalk code pattern, and FIG. 2(e) is a worst PDN code pattern;
FIG. 3 is an example of a complete emulation pattern proposed by the present invention;
fig. 4 is a block diagram of the code pattern proposed by the present invention for transistor-level high-speed interface full link signal integrity simulation acceptance.
Detailed Description
The embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
Referring to fig. 1 and 2, the detailed implementation steps of the present invention are as follows:
step 1, for each attacked signal, obtaining the crosstalk ordering of the attacking signal.
Firstly, reading in an S parameter model of a high-speed interface link, and for each signal, reading crosstalk of other signals to the signal and sequencing according to amplitude. The amplitude here can be selected as a single frequency point (generally, the nyquist frequency of a high-speed interface), or as a root mean square of crosstalk amplitude of a plurality of frequency points near the nyquist frequency, which mainly takes into account that possible resonance problems of a channel may cause errors in the method of a single frequency point.
The S parameter here is required to be an S parameter of a full link, and can be obtained by performing a cascade process on the S parameter of each module such as a package/PCB by a script tool or a business tool.
The crosstalk sequencing for acquiring the attack signal is very important for the code pattern design of some advanced DDR interfaces with DBI function, because the next one is under the DBI functionbyteThe number of signals switched simultaneously is 5 at most, so that the attack signal with the largest crosstalk is selected to carry out odd mode attack and even mode attack on the victim signal respectively, and the worst attack effect can be simulated by the shortest code pattern. For a multi-channel SERDES interface without DBI functionality, a pattern design similar to DBI can be used to reduce unnecessary pattern length, since crosstalk control for high-speed SERDES interfaces is generally more stringent and channel crosstalk away from victim signals is substantially negligible.
And 2, generating a PRBS seed code pattern, and rewriting the code pattern a to enable the code pattern to contain the worst intersymbol interference effect.
Fig. 2(a) shows a PRBS seed pattern a including intersymbol interference effect after overwriting. Because the code pattern design of the invention considers the effects of intersymbol interference, crosstalk noise, power noise and the like, the length requirement on the PRBS seed code pattern is lower, the PRBS5 is generally enough, and the PRBS6 or higher order can be selected when the intersymbol interference is more serious.
Exemplary intersymbol interference patterns are shown in fig. 2(b), and include ISI patterns, which generally include long 0 and long 1 patterns, and the specific length depends on the quality of the link channel and the rate of the high-speed interface, and can be determined by performing an impulse response simulation on the link channel. This pattern is modified based on the PRBS pattern to be embodied in the final pattern design.
And 3, generating a crosstalk code pattern b of each signal by taking the code pattern a as a seed code pattern.
For the crosstalk patterns, the odd and even patterns are two extreme attack patterns, as shown in fig. 2(c) and 2 (d). With three signals (DQ0,DQ1,DQ2) For example, combining the results of steps 1 and 2, the code pattern b of three signals can be generated as follows:
wherein the content of the first and second substances,
is the inversion of pattern a. The first column is even mode code type, the last three columns are respectively corresponding toDQ0、DQ1AndDQ2the odd mode pattern of (1).
Since the odd patterns of each signal are set and concatenated separately, limiting the number of attack signals of a signal directly contributes to reducing the pattern length. For a high-speed interface link, a relatively strict crosstalk control is generally performed, and 4-6 attack signals are selected to be basically close to the worst crosstalk noise.
And 4, reading an S parameter model or PDN impedance resonant frequency of the PDN link, and performing post-processing on the code pattern b to generate a code pattern c containing the worst power supply noise effect.
The pattern that can excite the worst PDN noise is a pattern that coincides with the resonant frequency of the PDN, as shown in fig. 2 (e). Therefore, at this step, the PDN system level S parameter model is firstly read and the resonant frequency of the PDN is analyzedf pdn Or directly inputting the known resonant frequency of the PDNf pdn 。
The resonant frequency of PDN in system level of general high-speed interface is far lower than the working frequency of high-speed interfacef op For example, the DDR interface is usually between 100MHz and 200 MHz. In order to superimpose the noise effect of the PDN on the intersymbol interference and crosstalk noise, there is a certain gap directly in the pattern b generated in step 3Constructing a pattern envelope coinciding with the resonant frequency of the PDN by inserting a certain number of bits "0" or "1" at intervals, the specific number depending onf op Andf pdn is rounded offM。
M=[f op /f pdn ]；
Taking LPDDR4X with 1866MHz operating frequency as an example, assuming that the PDN resonant frequency is 200MHz, M is 9. The method for rewriting the code pattern b into the code pattern c is to add 9 "0" or "1" every 9 bits.
Code pattern b0 b1 b2 … b9 b10 … b16 b17 b18 …
Code pattern c: b0 b1 b2 … b 9000000000 b10 … b16 b17 b 18000000000 …
FIG. 3 is an example of an emulation code pattern according to the present invention.
As shown in fig. 4, for simulation accuracy, especially in the design acceptance stage, TXIO preferably includes a transistor-level netlist with parasitic parameters for chip routing, which results in very high simulation complexity of the whole link, whereas if a conventional random code pattern is used as an excitation source, a relatively long simulation code pattern is needed to cover various possible bad code patterns, and the simulation efficiency is very low.
Table 1 shows the comparison of the proposed pattern with the pattern used in the conventional signal integrity simulation, where PRBS12 is a random sequence pattern and the concatenated pattern is a simple concatenation of a crosstalk pattern, an intersymbol interference pattern, and a power noise pattern. The code pattern efficiency provided by the invention is 4 times of that of the cascade code pattern and more than 7 times of that of the PRBS12 code pattern. From the simulation results, the PRBS12 pattern has a length of 4096 bits, but still fails to simulate a sufficiently bad situation. The concatenated pattern can be more closely matched to the present invention, but the worst signal quality still cannot be simulated because the superposition effect cannot be covered. The code pattern provided by the invention comprehensively considers various effects influencing the quality of the eye pattern and the superposition influence thereof, and both the eye height and the jitter are worst, so that the real worst condition of the high-speed interface design can be reflected.
Table 1:
| code pattern | Simulation time | Eye height (mV) | Dithering (ps) |
| PRBS12(4096) | 3days:22hrs | 208 | 12.6 |
| Cascade code type (2048) | 50hrs:27mins | 169 | 18.1 |
| The invention code type (512) | 13hrs:32mins | 155 | 23.8 |
Claims (9)
1. A method for generating a pattern for use in signal integrity analysis, the method comprising the steps of:
reading a signal full-link S parameter model, determining crosstalk sequencing of bits in each high-speed interface, and determining an attacked corresponding to each signal line according to the maximum attacker number of the attacked signals;
generating a PRBS seed code pattern to enable the PRBS seed code pattern to contain the worst intersymbol interference effect, and rewriting the PRBS seed code pattern into a code pattern a;
thirdly, generating a code pattern b containing crosstalk noise of each signal by taking the code pattern a as a seed code pattern;
and step four, reading an S parameter model or PDN impedance resonant frequency of the PDN link, and performing post-processing on the code pattern b to generate a code pattern c comprising worst power supply noise.
2. A method for generating patterns for use in signal integrity analysis as defined in claim 1, wherein: in the first step, when the high-speed interface is provided with a DBI function, the PRBS seed pattern is added with a setting corresponding to the DBI function, and when the high-speed interface does not have the DBI function, the maximum attack signal number of the victim signal is set to reduce the pattern length.
3. A method for generating patterns for use in signal integrity analysis as defined in claim 1, wherein: in the third step, when only the eye diagram quality of a certain signal needs to be concerned, only a code pattern needs to be generated for the signal; when eye quality of all signals needs to be taken into account, patterns are generated and concatenated for all signals.
4. A method for generating patterns for use in signal integrity analysis as defined in claim 1, wherein: the signal integrity analysis comprises a high-speed interface chip drive-end transistor level IO netlist or IBIS model or other forms of IO model, a packaging link model, a PCB link model and a receiving end chip packaging and IO model, wherein the model comprises a power supply and a signal link.
5. A method for generating patterns for use in signal integrity analysis as defined in claim 1, wherein: the envelope frequency of the power supply noise pattern is consistent with the anti-resonance frequency point of the power supply distribution network, and the worst theoretical noise can be excited.
6. A method for generating patterns for use in signal integrity analysis as defined in claim 1, wherein: and generating the worst intersymbol interference code pattern of each signal according to the impulse response obtained by the S parameter model of the signal link, wherein the intersymbol interference code patterns of the signals are the same or different.
7. A method for generating patterns for use in signal integrity analysis as claimed in claim 2, wherein: and for each bit, generating the code patterns of an odd mode and an even mode according to the crosstalk sequencing of the attack signals acquired from the S parameter of the full link and whether the attack signals have the DBI function or not so as to reflect the worst crosstalk noise influence.
8. A method for generating patterns for use in signal integrity analysis as claimed in claim 2, wherein: the DBI function means that 8-bit data is inverted at most 4 bits at the same time in a parallel interface, and if the 8-bit data exceeds 4 bits, the bit bits are inverted, so that the bit number of synchronous switching is controlled, and the noise and the power consumption of the synchronous switching are reduced.
9. A method for generating patterns for use in signal integrity analysis as defined in claim 1, wherein: the code pattern generation step is realized in a background mode or a visual interactive interface mode through a script language or a programming language.
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