CN110688815A - Memory interface circuit hybrid modeling simulation method based on memory access code pattern - Google Patents
Memory interface circuit hybrid modeling simulation method based on memory access code pattern Download PDFInfo
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Abstract
The invention provides a memory interface circuit hybrid modeling simulation method based on memory access code patterns, which relates to the technical field of simulation analysis and comprises the following steps: s1: establishing a memory access signal channel model containing a data group signal and an address group signal; s2: analyzing and defining the phase relationship between the data group signals and the address group signals; s3: adding proper excitation sources for data group signals and address group signals respectively; s4: obtaining key factors causing a Worst Case waveform through comparative analysis; s5: the key influencing factors are solved by the forward design, and steps S1 to S4 are repeatedly performed. The memory interface circuit hybrid modeling simulation method based on the memory access code type is beneficial to optimizing the memory access channel design of a memory system, is beneficial to optimizing DDR interface circuit parameter combination, can effectively avoid design risks at the initial stage of design, and is beneficial to actual memory control fault positioning at the operation stage.
Description
Technical Field
The invention relates to the technical field of simulation analysis,
in particular, the invention relates to a memory interface circuit hybrid modeling simulation method based on memory access code patterns.
Background
The important component of the computer system structure, the advanced storage system, has decisive influence on the performance index, the integration scale and the stable operation of the whole system. At present, a traditional high-speed parallel memory interconnect technology, ddr (double data rate) series memory, is widely used. Compared with DDR2 and DDR3, the memory access rate of the new generation DDR4 and the future DDR5 is greatly improved, and the more severe requirements on the memory access signal channel design capability are also provided. For DDR memory systems, the access signal channel includes address/control/command signals (clock sampling), data signals (data strobe sampling), etc., and is directly associated with an external power supply network through the chip internal circuitry. Under the conditions of increasing design complexity and increasing SI/PI design difficulty, a simulation method needs to be further improved, the high-speed signal transmission quality risk is effectively avoided at the initial stage of design, and the actual measurement waveform condition of a self-test code pattern or a copy engine problem code pattern can be simulated to a certain extent.
According to the conventional simulation analysis method, most cases only carry out some kind of simulation of the independent high-speed signal interface circuit, conditionally analyze the signal noise margin distribution condition and calculate the final residual noise margin. Wherein, crosstalk between signals of the same or different types is simulated, and synchronous switching noise of a power distribution network is simulated and used for signal noise margin distribution and final signal noise margin estimation. In this case, the excitation signal is usually selected to be PRBS or PULSE. The signal noise margin obtained by the simulation of the independent high-speed signal is subtracted from the signal swing distortion possibly caused by various external environment factors, and if a certain degree of signal noise tolerance can be obtained, the interconnection topology design of the high-speed signal interface circuit is feasible. At this time, the quantification of the influence of various external environmental factors is coarse, and the influence timing of the external environmental factors on the high-speed signal, such as interference to signal edges or a plateau level, cannot be accurately analyzed. Therefore, it is difficult for the conventional simulation analysis method to simulate the actual measurement waveform condition of the self-test pattern or the copy problem pattern.
Therefore, how to design a reasonable memory interface circuit hybrid modeling simulation method based on the memory access code pattern becomes a problem which needs to be solved urgently at present.
Disclosure of Invention
The invention aims to provide a memory interface circuit hybrid modeling simulation method based on an access code pattern, so as to effectively avoid the high-speed signal transmission quality risk at the initial design stage and simulate the actual measurement waveform in the test stage of a self-test code pattern or a copying machine subject code pattern copying machine in advance.
In order to achieve the purpose, the invention is realized by adopting the following technical scheme:
a memory interface circuit hybrid modeling simulation method based on memory access code patterns comprises the following steps:
s1: establishing a memory access signal channel model containing a data group signal and an address group signal;
s2: analyzing and defining the phase relationship between the data group signals and the address group signals;
s3: adding proper excitation sources for data group signals and address group signals respectively;
s4: obtaining key factors causing a Worst Case waveform through comparative analysis;
s5: the key influencing factors are solved by the forward design, and steps S1 to S4 are repeatedly performed.
Preferably, in step 1, the data group signal includes all or part of the data signal, and the address group signal includes all or part of the address, control and command signals.
Preferably, when step S1 is executed, the memory access signal channel model further covers a power distribution network matching the data group signal and the address group signal, and optionally other interference signals, where the other interference signals in the memory access signal channel model include interference signals causing crosstalk, loss, crosstalk, reflection, ripple observation, noise interference, injection signal, and the like of the Worst Case waveform.
Preferably, after the step S1 is executed, a post-simulation S parameter model of the memory system access signal channel is provided to improve the accuracy of the subsequent simulation test.
Preferably, when step S2 is executed, a simulation link for high-speed access signals of the storage system is built, timing constraints of data group and address group signals in a read operation or write operation stage are considered according to a working mechanism of a DDR series memory provided by the JEDEC standard, and a phase relationship between two types of access signals of the data group and address group signals is analyzed and defined.
Preferably, step S2 is performed using simulation tools including HSPICE and ADS circuit level simulation tools.
Preferably, in step S3, appropriate excitation sources are added to the data burst and address burst signals according to the self-test pattern and the copy problem pattern, and the timing constraints of the data burst and address burst signals during the read or write operation.
As a preferred aspect of the present invention, after step S3 is executed, the Worst Case excitation situation is searched and the simulation waveform is analyzed.
Preferably, in step S4, the key factors causing the Worst Case waveform are compared and determined for different code pattern combinations and different simulation waveforms.
Preferably, when step S5 is executed, the execution of steps S1 to S4 is stopped after obtaining a more ideal access signal waveform.
The memory interface circuit hybrid modeling simulation method based on the memory access code pattern has the advantages that: the memory interface circuit hybrid modeling simulation method based on the memory access pattern is convenient for effectively avoiding high-speed signal transmission quality risks at the initial design stage, can simulate the actual measurement waveform at the test stage of a self-test pattern or a copying machine subject pattern copying machine in advance, is beneficial to optimizing the memory access channel design of a memory system, is beneficial to optimizing DDR interface circuit parameter combination, can effectively avoid the design risks at the initial design stage, and is beneficial to actual memory control fault positioning at the operation stage.
Drawings
FIG. 1 is a schematic flow chart of a memory interface circuit hybrid modeling simulation method based on memory access code patterns according to the present invention.
Detailed Description
The following are specific examples of the present invention and further describe the technical solutions of the present invention, but the present invention is not limited to these examples.
Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that: the relative arrangement of the modules and steps set forth in these embodiments and steps do not limit the scope of the invention unless specifically stated otherwise.
Meanwhile, it should be understood that the flows in the drawings are not merely performed individually for convenience of description, but a plurality of steps are performed alternately with each other.
The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses.
Techniques, methods, and systems known to those of ordinary skill in the relevant art may not be discussed in detail, but are intended to be part of the specification where appropriate.
In the conventional simulation analysis method, the selected excitation signal is usually PRBS or PULSE, the quantization of the influence of various external environmental factors is coarse, and the influence timing of the external environmental factors on the high-speed signal, such as interference to signal edges or a stable level, cannot be accurately analyzed. Therefore, it is difficult for the conventional simulation analysis method to simulate the actual measurement waveform condition of the self-test pattern or the copy problem pattern.
Example one
As shown in fig. 1, which is only one embodiment of the present invention, the present invention provides a memory interface circuit hybrid modeling simulation method based on memory access patterns, including the following steps:
s1: establishing a memory access signal channel model containing a data group signal and an address group signal;
before simulation design, a memory access signal channel model needs to be accurately established, and the model must cover two types of key memory access signals: data group signals including all or part of the data signals, and address group signals including all or part of the address, control and command signals.
S2: analyzing and defining the phase relationship between the data group signals and the address group signals;
after the access signal channel model is established, a high-speed access signal simulation link for the storage system needs to be established, wherein an advanced simulation tool such as HSPICE or ADS or a common Multisim simulation tool is adopted for establishment, and the specific establishment process is as follows: according to the working mechanism of the DDR series memory provided by the JEDEC standard, the time sequence constraint of signals of a data group and an address group in a read operation or write operation stage is concerned, and the phase relation between two types of access signals of the data group and the address group is analyzed and defined.
The phase relation between two types of key access signals, namely data group signals and address group signals, is mainly analyzed and defined, and a proper excitation source is conveniently added.
S3: adding proper excitation sources for data group signals and address group signals respectively;
when step S3 is executed, appropriate excitation sources are added to the data set and address set signals according to the self-test pattern and code length, the copy problem pattern and code length, and the timing constraints of the data set and address set signals during the read or write operation.
S4: obtaining key factors causing a Worst Case waveform through comparative analysis;
the excitation source, namely the excitation port, is applied to the storage system, and response output is carried out on the high-speed memory access signal simulation link. After a plurality of experiments, the excitation condition of the Worst Case curve is found, and the simulation waveform is analyzed.
Of course, different simulation waveforms can be obtained according to different code pattern combinations of self-test code patterns and code lengths and copy engine subject code patterns and code lengths, the situation of the occurrence of the Worst Case curve is found out, and key factors of the Worst Case waveform caused by comparison and judgment are found out.
S5: the key influencing factors are solved by the forward design, and steps S1 to S4 are repeatedly performed.
The method has the advantages that key factor items under the condition that a Worst Case curve appears and the condition of a normal curve are compared, the key influence factors are solved through improvement, actual measurement waveforms after the key influence factors are solved are beneficial to optimizing memory access channel design of a storage system, optimizing DDR interface circuit parameter combination is facilitated, design risks can be effectively avoided at the initial stage of design, and actual memory control fault location is facilitated at the operation stage.
The memory interface circuit hybrid modeling simulation method based on the memory code type is based on the memory interface circuit hybrid modeling simulation method based on the memory code type, so that the high-speed signal transmission quality risk is effectively avoided at the initial design stage, the actual measurement waveform at the test stage of self-test code type or copying machine subject code type copying machine can be simulated in advance, the memory access channel design of a memory system is favorably optimized, the parameter combination of a DDR interface circuit is favorably optimized, the design risk can be effectively avoided at the initial design stage, and the actual memory control fault positioning is favorably realized at the operation stage.
Example two
Still as shown in fig. 1, it is still one embodiment of the present invention, and in order to make the memory interface circuit hybrid modeling simulation method based on the memory access code type more convenient in design and higher in accuracy of simulation design, the present invention further has the following designs:
first, when step S1 is executed, the memory access signal channel model further covers the power distribution network matched with the data group signal and the address group signal, and optionally other interference signals, where the other interference signals in the memory access signal channel model include interference signals causing crosstalk, loss, crosstalk, reflection, fluctuation observation, noise interference, injection signal, and the like of the Worst Case waveform.
The memory signal channel model has wide coverage range, and in the step S4, when the simulation waveform is generated, the found key factors causing the Worst Case waveform are more comprehensive, and the key influence factors are more conveniently solved.
Then, after step S1 is executed, a post-simulation S parameter model of the memory system access signal channel is provided to improve the accuracy of the subsequent simulation test.
And providing a post-simulation S parameter model of a memory access signal channel of the memory system, so that an excitation source is conveniently applied to the memory system in the step S3, response output is carried out on a high-speed memory access signal simulation link, and the precision of a subsequent simulation test can be effectively improved.
Finally, when step S5 is executed, after ensuring that a more ideal access signal waveform is obtained, the execution of steps S1 to S4 is stopped.
The method comprises the steps of simulating an actual measurement waveform in a test stage of a self-test code pattern or a copying code pattern copying machine in advance, developing multiple simulation tests to obtain different simulation waveforms, solving key influence factors, obtaining an ideal access signal waveform after outputting the ideal access signal waveform, ensuring that the more ideal access signal waveform is obtained, and repeatedly executing the steps S1 to S4.
The memory interface circuit hybrid modeling simulation method based on the memory code type is based on the memory interface circuit hybrid modeling simulation method based on the memory code type, so that the high-speed signal transmission quality risk is effectively avoided at the initial design stage, the actual measurement waveform at the test stage of self-test code type or copying machine subject code type copying machine can be simulated in advance, the memory access channel design of a memory system is favorably optimized, the parameter combination of a DDR interface circuit is favorably optimized, the design risk can be effectively avoided at the initial design stage, and the actual memory control fault positioning is favorably realized at the operation stage.
While certain specific embodiments of the present invention have been described in detail by way of illustration, it will be understood by those skilled in the art that the foregoing is illustrative only and is not limiting of the scope of the invention, as various modifications or additions may be made to the specific embodiments described and substituted in a similar manner by those skilled in the art without departing from the scope of the invention as defined in the appending claims. It should be understood by those skilled in the art that any modifications, equivalents, improvements and the like made to the above embodiments in accordance with the technical spirit of the present invention are included in the scope of the present invention.
Claims (10)
1. A memory interface circuit hybrid modeling simulation method based on memory access code patterns is characterized by comprising the following steps:
s1: establishing a memory access signal channel model containing a data group signal and an address group signal;
s2: analyzing and defining the phase relationship between the data group signals and the address group signals;
s3: adding proper excitation sources for data group signals and address group signals respectively;
s4: obtaining key factors causing a Worst Case waveform through comparative analysis;
s5: the key influencing factors are solved by the forward design, and steps S1 to S4 are repeatedly performed.
2. The memory interface circuit hybrid modeling simulation method based on memory code patterns according to claim 1, characterized in that:
in step S1, the data group signal includes all or part of the data signals, and the address group signal includes all or part of the address, control and command signals.
3. The memory interface circuit hybrid modeling simulation method based on memory code patterns according to claim 1, characterized in that:
in step S1, the memory access signal channel model further covers a power distribution network associated with the data group signal and the address group signal.
4. The memory interface circuit hybrid modeling simulation method based on memory code patterns according to claim 1, characterized in that:
after the step S1 is executed, a post-simulation S parameter model of the memory system access signal channel is provided to improve the precision of the subsequent simulation test.
5. The memory interface circuit hybrid modeling simulation method based on memory code patterns according to claim 1, characterized in that:
when step S2 is executed, a simulation link for high-speed access signals of the storage system is established, timing constraints of data group and address group signals in a read operation or write operation phase are concerned according to a working mechanism of a DDR series memory provided by the JEDEC standard, and a phase relationship between two types of access signals of the data group and address group signals is analyzed and defined.
6. The memory interface circuit hybrid modeling simulation method based on memory code patterns according to claim 1, characterized in that:
in executing step S2, simulation tools including HSPICE and ADS circuit level simulation tools are used.
7. The memory interface circuit hybrid modeling simulation method based on memory code patterns according to claim 1, characterized in that:
in step S3, appropriate excitation sources are added to the data set and address set signals according to the self-test pattern and the copy problem pattern, and the timing constraints of the data set and address set signals during the read or write operation.
8. The memory interface circuit hybrid modeling simulation method based on memory code patterns according to claim 1, characterized in that:
after step S3 is executed, the Worst Case excitation situation is searched, and the simulation waveform is analyzed.
9. The memory interface circuit hybrid modeling simulation method based on memory code patterns according to claim 1, characterized in that:
and when the step S4 is executed, aiming at different code pattern combinations and obtaining different simulation waveforms, comparing and judging key factors causing the WorstCase waveform.
10. The memory interface circuit hybrid modeling simulation method based on memory code patterns according to claim 1, characterized in that:
when step S5 is executed, after ensuring that a more ideal access signal waveform is obtained, the execution of steps S1 to S4 is stopped.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113392606A (en) * | 2021-06-11 | 2021-09-14 | 北京物芯科技有限责任公司 | Internal interface signal sampling method and device and computing equipment |
| WO2023164959A1 (en) * | 2022-03-02 | 2023-09-07 | 长鑫存储技术有限公司 | Signal eye pattern analysis system and method therefor |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20110307234A1 (en) * | 2010-06-09 | 2011-12-15 | Renesas Electronics Corporation | Circuit simulation method and circuit simulation device |
| CN107301270A (en) * | 2017-05-23 | 2017-10-27 | 东南大学 | The Analytic modeling method of DDR storage system Memory accessing delays |
-
2019
- 2019-09-12 CN CN201910864994.4A patent/CN110688815A/en not_active Withdrawn
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20110307234A1 (en) * | 2010-06-09 | 2011-12-15 | Renesas Electronics Corporation | Circuit simulation method and circuit simulation device |
| CN107301270A (en) * | 2017-05-23 | 2017-10-27 | 东南大学 | The Analytic modeling method of DDR storage system Memory accessing delays |
Non-Patent Citations (1)
| Title |
|---|
| 李川 等: "《DDR4并行互连传输串扰特性仿真与分析》", 《计算机工程与科学》 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113392606A (en) * | 2021-06-11 | 2021-09-14 | 北京物芯科技有限责任公司 | Internal interface signal sampling method and device and computing equipment |
| WO2023164959A1 (en) * | 2022-03-02 | 2023-09-07 | 长鑫存储技术有限公司 | Signal eye pattern analysis system and method therefor |
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Application publication date: 20200114 |