CN112313797A

CN112313797A - Semiconductor structure enhanced for high voltage applications

Info

Publication number: CN112313797A
Application number: CN201980040879.3A
Authority: CN
Inventors: 弗雷德里克·瓦龙; 拉里·比夫莱
Original assignee: Murata Manufacturing Co Ltd
Current assignee: Murata Manufacturing Co Ltd
Priority date: 2018-06-21
Filing date: 2019-06-19
Publication date: 2021-02-02

Abstract

Semiconductor structures enhanced for high voltage applications are disclosed. The structure includes a protruding wall structure formed by etching the substrate, the protruding wall structure extending from a base surface of the substrate. The corners of the protruding wall structures may be smoothed or rounded to reduce electrical stress within the structure. The protruding wall structure may be divided into a plurality of wall regions arranged along different directions of the substrate to reduce mechanical stress.

Description

Semiconductor structure enhanced for high voltage applications

Technical Field

The present invention relates to the field of integration, and more particularly, to electronic products, related semiconductor products, and methods of manufacturing the same.

Background

Increasing capacitance density is a key goal in the development of emerging capacitive components. In the case of silicon-integrated capacitors, one method of increasing the capacitance density includes increasing the specific surface of the capacitive structure by making the surface of the silicon wafer a 3D structure. This allows the die surface to be reduced and the capacitive technology of integrated silicon to reach a level of integration that matches the requirements for implementing low voltage applications.

However, in the area of emerging high voltage applications, controlled by the roadmap of integrated power supply technologies like GaN (gallium nitride) and SiC (silicon carbide), capacitive technology integration remains largely unexplored. In such applications, the operating electric field must be guaranteed with sufficient margin for the expected lifetime of the device in order to prevent early failure and/or premature wear of the capacitive device. One way to maintain the operating electric field is by increasing the thickness of the dielectric layer. However, existing silicon processing techniques for high voltage or high power applications (e.g., greater than 500 volts) are not compatible with large dielectric thicknesses.

For example, Gruenler et al ("High-voltage monolithic 3D capacitors based on through-silicon via technology"), IEEE International interconnect technology conference and IEEE advanced metallization materials conference, 5/18/21/2015, Greenobuler, et al propose 3D capacitors for High voltage applications. Fig. 1 shows an example 100 of a capacitor of Gruenler. As shown, capacitor 100 includes a substrate 102 having an array of cylindrical capillaries etched therein. The cylindrical capillary is filled with a capacitive structure consisting of semiconductor layer 104, dielectric layer 106, polysilicon layer 108 and metal layer 110. The semiconductor layer 104 and the metal layer 110 provide a bottom electrode and a top electrode, respectively, for the capacitive structure.

However, the 3D capacitor structure of Gruenler is not well suited for using large dielectric thicknesses. On the one hand, 3D structures have poor permeability to process gases, which complicates the process for etching cylindrical capillaries and depositing capacitive structures. On the other hand, once the cylindrical capillary is filled with the capacitive structure, the structure is subjected to high levels of mechanical stress. High mechanical stress results in a large amount of wafer warpage, further complicating subsequent process steps. Thicker dielectrics will exacerbate two of the drawbacks of the Gruenler structure, rendering capacitive integration even more complex. Furthermore, this will significantly increase the likelihood of defects (e.g., dielectric cracking or delamination) being created or occurring in the dielectric coating resulting in random device breakdown.

Accordingly, there is a need for an improved structure suitable for high voltage applications.

Disclosure of Invention

The present invention provides a structure comprising:

a substrate; and

a protruding wall structure formed by etching the substrate, the protruding wall structure extending upwardly from a base surface of the substrate, the protruding wall structure being continuous and forming at least a first wall region and a second wall region,

wherein the corners of the protruding wall structures are rounded.

For example, when forming electrical devices, such as capacitors, in the wall structures, the rounding of the corners of the protruding wall structures results in a more uniform distribution of the electrostatic field at the corners. This reduces electrical stress within the structure and enables it to better withstand the operating electric field of high voltage applications. Thus subsequently improving performance in terms of breakdown voltage, leakage, product reliability, and yield. The rounding of the corners also reduces mechanical stresses within the structure when the structure is coated with a dielectric layer. Typically, when the dielectric layer is placed on sharp edges or corners, high mechanical stresses are created in the dielectric layer. Rounding off the corners reduces this mechanical stress. Furthermore, rounding off the corners in terms of thickness results in a more uniform dielectric layer (i.e. less voids), which contributes to an improved performance of the dielectric layer.

The outstanding nature of the wall structure leads to several advantages. In fact, the open, protruding geometry makes the structure more favorable for gas circulation during etching and enhances its permeability to plasma. This results in easier (i.e., faster and more uniform) etch and oxide deposition processes, including easier access to rounded singularities (e.g., corners) of the structure to reduce electrical stress. The protruding geometry also translates into reduced mechanical stress and wafer bowing. This also facilitates subsequent processing and reduces the likelihood of defects occurring within the structure. All of these advantages contribute to the compatibility of the structure with the use of thicker dielectrics and thus to its suitability for high voltage applications.

In an embodiment, a multi-layer device is formed in the wall structure, at least one layer of the multi-layer device being deposited over the rounded corner. The multilayer device may include one or more of the following structures: a metal-insulator-semiconductor (MIS) structure, a semiconductor-insulator-semiconductor (SIS) structure, or a metal-insulator-metal (MIM) structure. One or more structures may be stacked in series.

In an embodiment, the electrodes of the multilayer device are provided by the substrate of the structure.

After forming the multilayer arrangement in the protruding wall structures, the spaces comprised between the protruding wall structures may be partially unfilled. This helps to further reduce mechanical stresses within the resulting structure.

In an embodiment, the radius of curvature of the rounded corners is proportional to the thickness of the multilayer device. In another embodiment, the radius of curvature of the rounded corner is greater than the thickness of the insulator layer of the multi-layer device. In yet another embodiment, the radius of curvature of the rounded corner is greater than twice the thickness of the insulator layers of the multilayer device.

In an embodiment, the spaces comprised between the protruding wall structures form a continuous pattern over the base surface of the substrate.

The first wall region and the second wall region comprise walls having a limited length. In an embodiment, the walls of the first wall region may be disposed along a first direction of the substrate, and the walls of the second wall region may be disposed along a second direction of the substrate. The first and second directions may form a defined angle with each other. The defined angle may be selected to reduce mechanical stresses within the structure. In an embodiment, the walls of the first wall region and the walls of the second wall region are symmetrically arranged to balance mechanical stresses along the first and second directions of the substrate, which helps to reduce wafer bowing.

The rounded corners of the protruding wall structures may fall in a plane perpendicular or parallel to the base surface of the substrate. In an embodiment, each corner in the protruding wall structure is rounded, whether in a plane perpendicular or parallel to the base surface of the substrate.

Drawings

Further features and advantages of the invention will become apparent from the following description of certain embodiments of the invention, given by way of illustration only and not by way of limitation, with reference to the accompanying drawings, in which:

FIG. 1 is a perspective view of a conventional integrated capacitor;

FIG. 2 shows the distribution of electrostatic field magnitude inside a silicon dioxide dielectric for different electrode geometries;

FIG. 3 is a cross-sectional view of a prior art trench structure;

FIG. 4 is a cross-sectional view of a structure according to an embodiment of the present invention;

FIG. 5 is a Scanning Electron Microscope (SEM) image of a structure formed by deep etching of a silicon wafer;

fig. 6 is an SEM image of a structure formed according to an embodiment of the present invention.

FIGS. 7A and 7B illustrate the effect of rounding on the breakdown field distribution;

FIG. 8 is a top view of a structure according to an embodiment of the present invention; and

fig. 9 is an SEM image of a structure according to an embodiment of the present invention.

Detailed Description

Embodiments of the present invention address the existing deficiencies of the prior art by providing a structure that is enhanced for high voltage applications.

In one aspect, the proposed geometry of the structure is adapted to reduce or prevent electric field concentrations within the structure. This reduces electrical stress within the structure and enables it to better withstand the operating electric field of high voltage applications. Thus subsequently improving performance in terms of breakdown voltage, leakage, product reliability and yield.

To illustrate the relationship between electrical stress within a structure and the geometry of the structure, fig. 2 shows the distribution of electrostatic field magnitude at 600 volts inside a silicon dioxide dielectric for different

example electrode geometries

202, 204, 206, and 208. The dielectric is sandwiched by opposing top and bottom electrodes (not shown in fig. 2).

The magnitude of the electrostatic field at a given point of electrode geometry is directly related to the local difference in charge density between opposing electrodes. Thus, where the electrode geometry is uniform, such as electrode geometry 202, the electrostatic field is uniformly distributed across the electrode geometry. As shown by curve 210, the electrostatic field magnitude is therefore kept constant across the electrode geometry.

However, when the electrode geometry contains irregularities, such as sharp corners in the electrode geometry 204, the length/surface difference between opposing electrodes at the irregularities causes a difference in charge density near the irregularities. For example, in the electrode geometry 204, the inner profile of the sharp corner has a smaller length/surface than the outer profile of the corner. Following the principle of overall electrostatic neutrality (i.e., the integral of the charge on the top electrode is equal to the integral of the charge on the bottom electrode), higher charge accumulation occurs at the corners of the bottom electrode (i.e., the inner electrode protruding into the dielectric) rather than at the corners of the top electrode (i.e., the outer electrode overlying the dielectric). Thus, at the sharp angle, the electrostatic field exhibits a peak in magnitude (magnitude) as shown by curve 212. In fact, the magnitude of the electrostatic field that peaks reflects the presence of a very high electrostatic field that may exceed the dielectric strength and thus lead to faster dielectric loss and/or earlier breakdown.

Embodiments of the present invention seek to reduce the concentration of local electrostatic fields in the structure by smoothing or rounding singularities (e.g., corners, peaks, etc.) in the geometry.

Example electrode geometries

206 and 208 illustrate this smoothing or rounding effect. The rounded electrode geometry 206 presents a smooth distribution of the magnitude of the electrostatic field, as shown by curve 214. For example, although the magnitude of the electrostatic field is not constant across the geometry, it does not exhibit a peak as in the case of electrode geometry 204. As in the electrode geometry 208, a further increase in the radius of curvature ensures a stronger match between the top and bottom electrode surfaces. This translates into a substantially constant electrostatic field magnitude, as shown by curve 216.

In an implementation, the rounding of the singularities is not a simple task. For example, the trench capacitor structure 300 shown in cross-section in fig. 3 illustrates a conventional capacitor structure disclosed by Tran et al (US 2013/0161792a 1). Trench capacitor structure 300 is obtained by etching a trench 304 into wafer 302. The top and/or bottom corners of the groove 304, such as corner 306, may be chamfered or rounded. In practice, however, implementing a Tran structure is challenging, for example, because the trench geometry does not facilitate the etch process required to round corners, particularly bottom corners such as corner 306. Therefore, the effect of smoothing or rounding is not optimal, if not negligible, in reducing electrical stress.

According to one aspect, embodiments of the present invention facilitate the rounding of singularities by employing structures that can better reach the corners by the etching process. In an embodiment, as shown in fig. 4, a mirror image of the trench structure is used. In particular, the resulting structure 400 is obtained by etching the substrate 402 to form protruding wall structures that extend upward from the base surface of the substrate 402. The protruding wall structure comprises a plurality of elongated walls 404 over and between which capacitive means may be deposited.

In an embodiment, a multi-layer device (not shown in fig. 4) may be formed in the protruding wall structure, wherein at least one layer of the multi-layer device is deposited over the rounded corners of the structure 400.

In an embodiment, the rounded corners may be configured to have a radius of curvature that is proportional to the thickness of the multilayer device. For example, the radius of curvature of the rounded corners may be configured to be greater than the thickness of the insulator or dielectric layers of the multilayer device. In another embodiment, the radius of curvature of the rounded corners may be configured to be greater than twice the thickness of the insulator or dielectric layers of the multilayer device.

The multilayer device may include one or more of the following structures: such as a metal-insulator-semiconductor (MIS) structure, a semiconductor-insulator-semiconductor (SIS) structure, or a metal-insulator-metal (MIM) structure. In an embodiment, one or more structures may be stacked in series. In an embodiment, the electrodes of the multilayer device may be provided by the substrate 402.

In an embodiment, the protruding wall structures of structure 400 may be partially unfilled after the multilayer device is formed therein. This helps to reduce mechanical stress within the resulting capacitive structure.

The large spacing between the walls 404 (as opposed to the narrow volume of the trench in the Tran structure) allows any corners of the structure 400 to be easily rounded. In an embodiment, the corners that fall in a plane perpendicular to the base surface of the substrate 402 may be rounded. Examples of such angles may be

angles

406 and 408 that fall in the plane of the figure.

In another embodiment, the corners that fall in a plane parallel to the base surface of the substrate 402 may be rounded. Such an angle may occur in the vertical side edges of the wall 404, i.e., the edges where the wall 404 rises from the base surface of the substrate 402.

In yet another embodiment, all corners of the structure 400 (whether in a plane perpendicular or parallel to the base surface of the substrate 402) may be rounded.

Typically, the rounding of the corners that fall in a plane parallel to the base surface of the substrate 402 may be controlled by the layout. For example, a hard mask pattern that results in those corners being rounded may be used to etch the substrate 402 to obtain protruding wall structures. In general, the process can be controlled easily and with high precision.

However, for corners that fall in a plane perpendicular to the base surface of substrate 402, such as

corners

406 and 408, control of the rounding may be more difficult. Typically, in silicon wafers, the shape of such corners is directly dependent on the etching process used. When a deep etch process through a silicon dioxide hard mask is used, the resulting corners are typically sharp or may have sharp ledges. This is shown, for example, in fig. 5, fig. 5 being a Scanning Electron Microscope (SEM) image of a structure formed by Deep Reactive Ion Etching (DRIE) of a silicon wafer. In addition, as shown in the enlarged view in fig. 5, a fan effect may be generated at a portion of the wall adjacent to the corner.

One method of achieving better corner rounding relies on isotropic dry etching to consume the sharp edges. However, while such an approach may be effective in controlling the rounding at the tip of the wall, it is less effective for the downwardly deeper portions of the wall and is also less effective in reducing the scalloping effect.

Another approach is based on a wet etch process that removes a sacrificial thermal oxide layer formed on the silicon surface. This method has the advantage of conformal growth along the profile of the corners and is therefore effective in reducing the scalloping effect.

Yet another approach is to use a high temperature anneal for silicon under low pressure hydrogen (e.g., 100 torr, 1100 ℃). An SEM image of a structure formed using this process according to an embodiment is shown in fig. 6. As shown, the structure exhibits well rounded corners and no scalloping. The radius of curvature of the corners according to the method is a function of the thermal budget and time. In particular, the rounding process is controlled by reducing the surface energy on the outer wall of the structure. This results in the process being self-limiting, i.e. producing a higher rounding rate in sharp regions compared to flat or pre-rounded regions. Thereby resulting in a more uniform structure.

The performance of the structure obtained according to this high temperature annealing method is shown in fig. 7A and 7B. Specifically, FIG. 7A is a Weibull plot of the percentage unreliability of breakdown voltage for an unrounded structure (the failure distribution is not subject to a normal (Gaussian) distribution, but rather to a Weibull distribution, since breakdown is a physical mechanism that depends on failure of the weakest element in the chain. the plot shown in FIG. 7A represents a linearization of experimental data on the Weibull plot). Fig. 7B shows the same diagram with respect to the rounding configuration. The percent unreliability represents the probability of failure of a structure (e.g., a capacitor) at the breakdown voltage.

As shown, the rounded structure exhibits a steeper breakdown voltage distribution than the unrounded structure. The steepness of the distribution (represented by its beta factor) reflects the dispersion of the breakdown voltage population (the higher the beta, the smaller the dispersion of the distribution). In other words, devices formed using rounded structures (e.g., capacitors) have more uniform breakdown voltage performance than devices formed using non-rounded structures (e.g., for a given stress voltage, the best and worst devices for a rounded structure population will have less life difference than the best and worst devices for a non-rounded structure population).

The rounded structure also exhibits a higher T63 than the unrounded structure. T63 for a Weibull distribution is equivalent to the mean of a normal distribution; in other words, T63 represents a position where the breakdown voltage distribution is concentrated. As shown in fig. 7A and 7B, T63 for the rounded structure is equal to 422V, compared to T63 for the unrounded structure, which is equal to 364V. This means that rounded structures have a higher average breakdown voltage than non-rounded structures.

On the other hand, the proposed geometry of the structure is adapted to reduce mechanical stresses within the structure. This feature reduces the likelihood of defects in the dielectric layer and makes the structure more amenable to increased dielectric thickness. Indeed, as mentioned above, in order to sustain high voltages, the dielectric layer needs to be deposited as a thick layer for high voltage applications. For example, for an oxynitride layer deposited by LPCVD (low pressure chemical vapor deposition), a dielectric thickness of greater than 1.5 microns is typically required for a breakdown voltage of 900 volts. Such thick dielectrics cause high mechanical stress when embedded in high aspect ratio structures, causing such things as layer cracking and delamination, dielectric cracking at sharp corners, and/or excessive bending of the silicon wafer, which prevents proper processing. For example, using the described dielectric layers, a wafer radius of curvature as low as 12m was observed in experiments. Without further steps to account for bow in the wafer, the resulting structure would be incompatible with conventional photolithography steps (e.g., defocus, processing, and/or chucking issues may arise).

The proposed structure reduces mechanical stress due to its open, protruding geometry. In fact, by being attached to the substrate only through its bottom surface, the proposed structure is free to adapt to stress along its height by bending, without transferring high strains to the substrate. In contrast, for example in a trench structure as shown in fig. 3, a narrow trench is defined from both the top and bottom by a rigid network of walls connected to the substrate. Therefore, the stress built up in the trench when depositing the capacitive device can only be transferred to the substrate.

By comparing the wafer bow of the two structures, the difference in built-in mechanical stress between the two structures can be easily determined. In practice, experiments have shown that for a given dielectric layer and equivalent geometry, the ratio of the wafer radius of curvature between the protruding wall structures and the conventional trench structures may be greater than 20 (e.g., in experiments, the radius of curvature of the protruding wall structures is greater than 250 meters, while the radius of curvature of the conventional trench structures is equal to 12 meters).

With lower mechanical stress, embodiments of the present invention can accommodate higher dielectric thicknesses than conventional structures, thereby achieving superior performance for high voltage applications. In an embodiment, the mechanical stress may be further reduced within the proposed structure by leaving the protruding wall structure partially unfilled after forming the capacitive means in the protruding wall structure.

On the other hand, by forming wall regions in the structure, which are arranged in different directions along the substrate, the mechanical stress in the proposed structure is further reduced. This aspect is illustrated in fig. 8, fig. 8 being a top view of a structure 800 according to an embodiment. For the sake of simplicity, the rounding of the corners is not shown in fig. 8.

As shown in fig. 8, the structure 800 includes a plurality of wall regions, such as a first wall region 802 and a second wall region 804. Each wall region includes a plurality of walls having a finite length. In an embodiment, the wall forming the wall region may be disposed along the first direction or the second direction of the substrate. In other embodiments, more than two directions may be used. For example, in structure 800, the walls of first wall region 802 are disposed along a first direction and the walls of second wall region 804 are disposed along a second direction.

The first and second directions may form a defined angle with each other. The defined angle may be selected to reduce mechanical stresses within the structure. In an embodiment, the first direction may be perpendicular to the second direction. However, embodiments are not limited to this implementation, and other angular relationships between the first and second directions (e.g., 10, 20, 30, 40, 60, and 120 degrees) may be used.

In an embodiment, the wall regions arranged along the first direction and the wall regions arranged along the second direction are symmetrically arranged to reduce mechanical stress along the first direction and the second direction. In an embodiment, the wall area arranged along the first direction is surrounded along its sides by the wall area arranged along the second direction, and vice versa.

Fig. 9 is an SEM image of a structure according to an embodiment of the present invention. As shown, according to this embodiment, all corners in the protruding wall structure are rounded. Additionally, the structure is divided into wall regions symmetrically disposed along the first vertical direction and the second vertical direction. Both electrical and mechanical stresses within the structure are greatly reduced, making it highly suitable for high voltage applications and for thicker dielectric layers.

On the other hand, the proposed structure features a 3D geometry, which facilitates the process of integrating the capacitive device therein. In fact, by having a protruding wall structure rather than a narrow trench, the structure is more conducive to gas circulation during etching and has better plasma permeability. This results in an easier (i.e., faster and more uniform) etch and oxide deposition process. This is especially true when DRIE is used to etch the wall structure and chemical vapor deposition (e.g., LPCVD) is used to deposit the dielectric. The open structure also makes rounding of the corners easier. In addition, lower mechanical stress and wafer bow facilitate subsequent processing.

Further variants

Although the invention has been described above with reference to certain specific embodiments, it will be understood that the invention is not limited to the features of the specific embodiments. Many variations, modifications and developments are possible in the above-described embodiments within the scope of the appended claims.

Claims

1. A structure, comprising:

a substrate; and

wherein the corners of the protruding wall structure are rounded.

2. The structure of claim 1, wherein the first and second wall regions comprise walls having a finite length.

3. A structure as claimed in claim 1 or 2, wherein the walls of the first wall region are arranged along a first direction of the substrate and the walls of the second wall region are arranged along a second direction of the substrate.

4. The structure of claim 3, wherein the first and second directions form a defined angle with each other, the defined angle being selected to reduce mechanical stress within the structure.

5. The structure of any one of claims 3 to 4, wherein the walls of the first wall region and the walls of the second wall region are symmetrically arranged to balance mechanical stresses along the first and second directions of the substrate.

6. The structure of any one of claims 1 to 5, wherein the rounded corners are in a plane perpendicular to the base surface of the substrate.

7. The structure of any one of claims 1 to 5, wherein the rounded corners are in a plane parallel to the base surface of the substrate.

8. The structure of any one of claims 1 to 7, further comprising:

a multi-layered device formed in the protruding wall structure, at least one layer of the multi-layered device being deposited over the rounded corner.

9. The structure of claim 8, wherein the multilayer device comprises one or more of the following structures: a metal-insulator-semiconductor (MIS) structure, a semiconductor-insulator-semiconductor (SIS) structure, or a metal-insulator-metal (MIM) structure.

10. The structure of claim 9, wherein the one or more structures are stacked in series.

11. The structure of any one of claims 8 to 11, wherein spaces comprised between the protruding wall structures are partially unfilled after the multilayer arrangement is formed in the protruding wall structures.

12. A structure according to any one of claims 8 to 11, wherein the electrodes of the multilayer device are provided by the substrate.

13. The structure of any one of claims 8 to 12, wherein a radius of curvature of the rounded corner is proportional to a thickness of the multi-layered device.

14. The structure of claim 13, wherein the radius of curvature of the rounded corner is greater than a thickness of an insulator layer of the multilayer device.

15. The structure of claim 13, wherein the radius of curvature of the rounded corner is greater than twice a thickness of an insulator layer of the multilayer device.