CN115699306A - Electronic component comprising a 3D capacitive structure - Google Patents

Abstract

An electronic component (1) comprising a 3D capacitive structure comprises: a substrate (2) having a contoured surface (2 a) comprising a plurality of wells (3) extending from a substrate surface into a substrate body; a dielectric (5) formed over and conforming to the shape of the contoured surface; and a first electrode (7) formed over the dielectric and conforming to the contoured surface shape. The substrate constitutes the second electrode, and the dielectric is interposed between the substrate and the first electrode. Portions of the dielectric are exposed through openings at the base of the contoured surface and are in contact with an insulating layer (10) formed below the substrate, thereby reducing an electrostatic field generated in the contacted portions of the dielectric when a potential difference is applied between the first and second electrodes. The opening at the bottom of the well is closed by a dielectric, the dielectric defines a blind hole within the well, and the first electrode is in the blind hole.

Description

Electronic component comprising a 3D capacitive structure

Technical Field

The present invention relates to the field of electronic components comprising three-dimensional (3D) capacitive structures, and more particularly to such components designed for use in high voltage applications.

Background

Increasing the capacitance density is a key goal in the development of emerging capacitive components. In the case of silicon integrated capacitors, one method of increasing the capacitance density includes increasing the specific surface of the capacitive structure by 3D structuring the surface of the silicon wafer. The 3D structuring may include forming a set of wells in a wafer, and conformally depositing a stack of electrodes and dielectric layers over surfaces of the set of wells. The 3D structuring may include forming a set of pillars or posts protruding from the wafer, and conformally depositing a stack of electrodes and dielectric layers over the surfaces of the set of pillars/posts. These technologies enable a reduction in chip surface (die surface) and silicon integrated capacitive technology to levels of integration that match the implementation requirements of low voltage applications.

However, capacitive technology integration remains a little studied in emerging high voltage application areas, guided by the roadmap of integrated power technologies like GaN (gallium nitride) and SiC (silicon carbide). In such applications, in order to prevent early failure and/or premature wear of the capacitive device, it is necessary to ensure that the operating electric field has sufficient margin for the expected lifetime of the device. One way to maintain the operating electric field is by increasing the thickness of the dielectric layer. However, existing silicon processing techniques for high voltage or power applications (e.g., greater than 500 volts) are not compatible with large dielectric thicknesses.

For example, gruenler et al ("High-voltage monolithic 3D capacitors based on through-silicon-via technology", IEEE International conference on interconnect technology and IEEE advanced metallization conference on 5 months 18 to 21 days 2015, greenburg) propose 3D capacitors for High voltage applications. An example 100 of a Gruenler capacitor is shown in FIG. 1. As shown, capacitor 100 includes a substrate 102, substrate 102 having an array of cylindrical capillaries etched in substrate 102. The cylindrical capillary is filled with a capacitive structure comprising a semiconductor layer 104, a dielectric layer 106, a polysilicon layer 108, and a metal layer 110. The semiconductor layer 104 and the metal layer 110 provide a bottom electrode and a top electrode, respectively, for the capacitive structure.

However, the 3D capacitor structure of Gruenler is not well suited for using large dielectric thicknesses. On the one hand, once the cylindrical capillary is filled with the capacitive structure, the 3D structure is subjected to high levels of mechanical stress. High mechanical stresses can lead to a large amount of wafer warpage, thereby complicating further subsequent processing steps. Thicker dielectrics will exacerbate this deficiency in the structure of Gruenler, making capacitive integration even more complex. Furthermore, it will significantly increase the probability of defects (e.g., dielectric cracking or delamination) being generated or occurring in the dielectric coating, leading to random device breakdown.

Furthermore, in high voltage applications, problems can arise in structures such as Gruenler due to the concentration of electrostatic charges. The applicant's co-pending application EP 18 305 789.2 describes a 3D capacitor structure on which a stack of electrodes and dielectric layers is formed over a set of pillars protruding from a substrate surface, and the pillars have rounded corners in order to reduce the concentration of electrostatic charges. For example, when forming an electrical device such as a capacitor in a wall structure, the rounding of the corners of the protruding wall structure results in a more uniform distribution of the electrostatic field at the corners. This reduces electrical stress within the structure and enables it to better withstand the operating electric field of high voltage applications. Thus subsequently improving performance in terms of breakdown voltage, leakage, product reliability and yield. The rounding of the corners also reduces mechanical stresses within the structure when the dielectric layer is used to coat the structure. Typically, high mechanical stresses occur in the dielectric layer when the dielectric layer is placed over sharp edges or corners. Rounding off the corners reduces this mechanical stress. Furthermore, rounding off the corners results in a more uniform dielectric layer (i.e., fewer voids) in terms of thickness, which is advantageous for improved dielectric layer performance.

To illustrate the relationship between electrical stress within a structure and the geometry of the structure, FIG. 2 shows the distribution of electrostatic field magnitude inside the silicon dioxide dielectric of different example electrode geometries 202, 204, 206, and 208 as calculated in the simulation. Simulation takes into account 1.3 μm thick SiO ₂ A dielectric layer is sandwiched by opposing top and bottom electrodes (not shown in fig. 2) and a potential difference of 1000V is applied between the electrodes. In FIG. 2, curves 210 and 216 show SiO ₂ The theoretical maximum field strength that can be tolerated. Some of these geometries may appear near the bottom of the well in a capacitive structure of a 3D profile, such as the capacitive structure of a 3D profile of Gruenler, and other geometries may appear at the base of the pillar protruding from the substrate in a capacitive structure of a 3D profile, such as the capacitive structure of a 3D profile of EP 18 305 789.2.

The magnitude of the electrostatic field at a given point of the electrode geometry is directly related to the local charge density difference between the opposing electrodes. Thus, where the electrode geometry is uniform, such as electrode geometry 202, the electrostatic field is uniformly distributed across the entire electrode geometry, and thus the electrostatic field magnitude remains constant across the entire electrode geometry.

However, when the electrode geometry contains irregularities such as sharp corners in the electrode geometry 204, the difference in length/surface between opposing electrodes at the irregularities causes a difference in charge density near the irregularities. For example, in the electrode geometry 204, the inner contour of a sharp corner has a smaller length/surface than the outer contour of the corner. Observing the overall electrostatic neutrality principle (i.e. the integral of the charge on the top electrode is equal to the integral of the charge on the bottom electrode), a higher charge density (in coulombs per unit area) occurs at the corners of the bottom electrode (i.e. the inner electrode protruding into the dielectric) than at the corners of the top electrode (i.e. the outer electrode covering the dielectric). Thus, at the sharp angle, the magnitude of the electrostatic field exhibits a peak, as shown by curve 212. In fact, the peak electrostatic field magnitude reflects the presence of a very high electrostatic field that may exceed the dielectric strength and thus lead to faster dielectric wear and/or earlier breakdown.

As is done in the structure proposed in EP 18 305 789.2, the local concentration of the electrostatic field in the structure can be reduced by smoothing or rounding off the singularities (e.g. corners, peaks, etc.) in the geometry. The effect of this smoothing or rounding is illustrated by example electrode geometries 206 and 208. The rounded electrode geometry 208 exhibits a smooth distribution of electrostatic field magnitude, as shown by curve 214. For example, although the electrostatic field magnitude is not constant across the geometry, it does not exhibit a peak as in the case of electrode geometry 204. As in the electrode geometry 208, a further increase in the radius of curvature ensures a stronger match between the top and bottom electrode surfaces.

In order to prevent early component breakdown due to a high electrostatic field, it is preferable to configure the radius of curvature of the rounded corner to be greater than the thickness of the dielectric layer, and it is more preferable that the radius of curvature of the rounded corner is equal to or greater than twice the thickness of the dielectric layer. However, in practice, it may be difficult to achieve a desired value of the radius of curvature. This problem can be better understood from a consideration of fig. 3A and 3B.

Fig. 3A is a Scanning Electron Microscope (SEM) image of a set of adjacent pillars in the 3D capacitor structure described in EP 18 305 789.2. Figure 3B is a schematic representation of a portion of the dielectric between the bases of two adjacent pillars in the structure of figure 3A.

Fig. 3B shows how the electrostatic field strength varies in the dielectric. More specifically, the intensity of the electrostatic field is highest towards the part shown in dark grey/black inside the bend in the dielectric. The field strength is still relatively high in the gray areas shown filling most of the dielectric "legs", decreasing in the light areas towards the bottom of the figure, and lowest at the bottom left and right of the figure.

In the example represented by fig. 3A and 3B, the capacitive structure includes a dielectric that is a laminated stack of alternating dielectric layers designed to withstand 1200V during use. Typically, the dielectric is deposited by a Low Pressure Chemical Vapor Deposition (LPCVD) process, and due to LPCVD conformality (which is typically between 50% and 90% when depositing a layer onto the profile surface), the dielectric is lower in thickness at the base of the pillar than it is on top of the pillar, and the profile is more sharply rounded at the base of the pillar. Thus, for example, at the base of the pillar, the thickness of the dielectric may be only 1.5 μm, while the radius of curvature of the dielectric may be 1 μm. This is far from the advantage that the radius of curvature is 2 or more times the dielectric thickness. The electrostatic field strength value in this region is high and can be greater than 15MV/cm.

A corresponding problem arises in the case where the capacitive stack is formed in a well/hole of the substrate, where an excessive electrostatic field strength value may occur in the dielectric near the bottom of the well.

The present invention has been made in view of the above problems.

Disclosure of Invention

Embodiments of the present invention provide a new technique aimed at reducing electrostatic field concentrations in dielectric layers in 3D capacitive structures, in particular in the region at the bottom of wells formed in the substrate.

The invention provides an electronic component comprising a capacitive structure, the component comprising:

a substrate having a contoured surface (surface) comprising a plurality of wells extending into the substrate from a substrate surface;

a dielectric formed over and conforming to the shape of the contoured surface of the substrate, some portion of the dielectric being exposed through an opening at the bottom of the well in the contoured surface of the substrate;

a first electrode of a capacitive structure formed over a dielectric and conforming to the shape of the contoured surface, the dielectric being interposed between the first electrode and a substrate constituting a second electrode of the capacitive structure; and

an insulating layer formed on a surface of the substrate remote from the contoured surface, the insulating layer in contact with the dielectric through the opening in the substrate;

wherein the opening at the bottom of the well is closed by a dielectric, whereby the dielectric defines a blind hole within the well and the first electrode is in said blind hole.

In the electronic component according to the present invention, the intensity of the electrostatic field generated in the dielectric when a potential difference is applied between the first electrode and the second electrode is reduced in a portion of the dielectric which is in contact with the insulating layer. In fact, the insulating layer, which is in contact with some part of the dielectric through the opening at the base of the contoured surface of the substrate, acts as a part of the dielectric and therefore as if the thickness of the dielectric increases locally (at the base of the contoured surface of the substrate) and the vertical component of the electrostatic field in the dielectric is here significantly reduced. This reduction in the strength of the electrostatic field allows capacitive structures in the electronic component to withstand higher operating voltages and/or to have reduced failures at a given operating voltage. Therefore, the electronic component can be well suited for high voltage applications.

In some embodiments of the invention, the third electrode of the capacitive structure is provided by forming a conductive layer on a surface of the substrate remote from the first electrode. Contacts (contacts) are provided to the first electrode, the second electrode, and the third electrode to apply the same potential to the first electrode and the third electrode, but to apply different potentials to the second electrode. For example, the capacitive structure may form a MIMIM capacitor structure. Since the dielectric portions at the base of the first and third electrodes are opposite each other across the contour structure, the strength of the electrostatic field is further reduced in these portions of the dielectric.

In the latter structure, a groove may be provided in the insulating layer at a position overlapping with a position of an adjacent portion of the first electrode (in plan view) in a surface thereof remote from the dielectric. By providing a conductive material in the groove, the intensity of the electrostatic field is further reduced in the portion of the dielectric at the base of the contoured surface of the substrate.

Also, one or more through holes may be provided through the insulating layer (instead of the above mentioned grooves), and by providing a conductive material in the through holes, the strength of the electrostatic field is reduced yet further in the portion of the dielectric at the base of the contoured surface of the substrate.

In the embodiment of the present invention including the third electrode, the thickness of the insulating layer is set to ensure that sufficient isolation is obtained in the planar region. More particularly, in embodiments including a third electrode, the reliability of the insulating layer when subjected to an electric field should be at least as good as the reliability of the dielectric. In case the insulating layer and the dielectric are made of the same material, the criterion involves setting the thickness of the insulating layer to be the same as or greater than the thickness of the dielectric layer. In case the insulating layer and the dielectric are made of different materials, the criterion involves setting the thickness of the insulating layer according to the ratio of the breakdown electric fields of the two materials.

The dielectric need not be a single layer of material. Instead, the dielectric may be comprised of a stack of layers of dielectric material.

The invention also provides a method of manufacturing an electronic component as described above as claimed in appended claim 8.

Drawings

Further characteristics and advantages of the present invention will become apparent from the following description of some embodiments thereof, given by way of illustration only and not of limitation, with reference to the accompanying drawings, in which:

fig. 1 is a schematic representation of a 3D capacitive structure known in the art;

FIG. 2 is a set of graphs showing how electrostatic field concentration varies with the shape of the dielectric layer;

fig. 3A and 3B show electrostatic field concentration in a known structure, in which:

FIG. 3A is a Scanning Electron Microscope (SEM) image of a capacitive stack formed on a set of posts protruding from a substrate, an

FIG. 3B is a schematic representation of the electrostatic field strength in the dielectric in the structure shown in FIG. 3B;

fig. 4 schematically shows a cross-section through an electronic component according to a first embodiment of the invention;

fig. 5 schematically shows a cross-section through an electronic component according to a second embodiment of the invention;

fig. 6 schematically shows a cross-section through an electronic component according to a third embodiment of the invention;

fig. 7A to 7F schematically represent results of simulations showing how the intensity of the electrostatic field in the dielectric varies when an insulating layer is added in contact with some portions of the dielectric and when the insulating layer and the dielectric are patterned to an increased extent, wherein:

figure 7A shows a comparative example in which no insulating layer contacts the dielectric,

figure 7B shows the dielectric in contact with the insulating layer,

figure 7C shows the case where the insulating layer is a patterned layer comprising recesses,

figure 7D shows the case where the insulating layer is a patterned layer comprising vias,

figure 7E shows the case where the dielectric is a patterned layer comprising recesses,

FIG. 7F shows a comparative example where the dielectric is a patterned layer including vias;

FIG. 8 is a flow chart representing steps of an exemplary method embodying the present invention for fabricating an electronic component in accordance with FIG. 6; and

fig. 9A to 9G show electronic components at various stages in the manufacturing method of fig. 8.

Detailed Description

Embodiments of the invention discussed below provide electronic components comprising 3D capacitive structures, in particular 3D capacitive structures designed to handle high operating voltages. However, it should be understood that the invention is more generally applicable to any 3D structure having 2 conductors separated by a dielectric sunk into the hole/well, where one conductor carries a high voltage (i.e. there is a high potential difference between the conductors) compared to the other conductor.

The principles of the present invention will become apparent from the following description of certain exemplary embodiments. Example embodiments relate to electronic components in which a 3D capacitive structure is formed in a well (hole, trench) in a substrate. Regardless of the shape of the well/trench, the invention applies: thus, for example, the invention may be applied to cylindrical wells or holes, elongated trenches, linear or meandering trenches, etc.

The structure of a first embodiment of an electronic component according to the invention is shown in a simplified manner in fig. 4.

The electronic component 1 shown in fig. 4 comprises a 3D capacitive structure. The component 1 may be a specific capacitive component, or it may comprise additional active and/or passive components in addition to the capacitive structure described below. The following description focuses on capacitive structures, but the skilled person will readily understand from common general knowledge how additional active and/or passive components may be added.

The 3D capacitive structure comprises a substrate 2 having a contoured surface 2a and a surface 2b remote from the contoured surface. In this example, the contoured surface is formed by a set of wells 3 in the substrate 2. The particular geometry of the well 3 (e.g. whether its cross-sectional shape is circular, elongate, etc.) is independent of the function described below, and any convenient geometry may be achieved.

The capacitive stack is formed on the contoured surface 2a and follows the shape of the contour. In view of manufacturing constraints, the conformality of the layers of the capacitive stack to the shape of the underlying contours may not be perfect, but the goal of the deposition process is to create a conformal layer. The capacitive stack includes a dielectric 5 formed over the underlying contoured surface 2a and substantially conforming to the shape of the underlying contoured surface 2 a. A conductive layer 7 is formed on the dielectric 5 and serves as a first electrode of the capacitive stack. In the example shown in fig. 4, the dielectric 5 is formed directly on the substrate 2, and the substrate serves as the second electrode. Thus, the dielectric 5 is interposed between the first electrode 7 and the second electrode 2. In use, a potential difference is established between the first and second electrodes.

There is an opening at the base of the contoured surface 2a of the substrate 2 and some portion of the dielectric 5 is exposed at the opening. An insulating layer 10 is formed on the support layer 12 on the rear surface 2b of the substrate. The insulating layer 10 is in contact with the dielectric 5 through an opening in the substrate. When a potential difference is applied to the first electrode 7 and the substrate/second electrode 2, the portions of the insulating layer 10 in contact with portions of the dielectric 5 behave as if the thickness of the dielectric 5 increases locally in the region close to the bottom of the well in the substrate. Because this locally thick dielectric region has been created, there is no (or very low amplitude) vertical component of the electric field in the dielectric in this region. This means that the charge is uniformly concentrated on the vertical walls, while there is almost no charge on the horizontal walls/tips of the inner electrodes. This means that although the geometry is close to the geometrical singularity, charge accumulation around the singularity is prevented and the situation is close to the ideal situation for a parallel plate capacitor. As can be seen from fig. 3B, this region is a position where the electrostatic field intensity tends to be maximum in the previously proposed structure. It will therefore be appreciated that the presence of the insulating layer 10 in contact with the dielectric 5 serves to reduce the electrostatic field in the most critical areas.

Substrate 2: may be a conductive material which may be any metal (e.g., al or Cu) or semiconductor material (e.g., si) having a medium to low resistivity. This can be achieved by surface or bulk doping to a dose from E19a/cm3 to E21a/cm 3. The substrate 2 may also be any insulating material (such as alumina or glass or epoxy) coated with a layer of a conductive material such as a metal (Al or Cu) or a semi-metal (TiN) or a semiconductor (such as polysilicon).

Insulating layer 10 and dielectric 5: can be made of any dielectric, preferably a high dielectric strength mineral dielectric such as silicon dioxide, or silicon nitride, or aluminum oxide, but can be any paraelectric material, for example. In another implementation, the dielectric is very thick (>1.5 μm), the insulating layer may be a high strength polymer such as p-xylene or polyetherimide. It may also be a layered composite layer combining a mineral dielectric and a polymer dielectric, or a layered composite layer comprising multiple layers of mineral dielectrics, or a layered composite layer comprising multiple layers of polymer dielectrics. In a dielectric composed of a plurality of stacked layers, the relative permittivity value (permittivity) epsilon of the material in the layer is determined by the relative permittivity _r To set the layer thickness, the concentration of the electric field in any particular layer can be avoided. The skilled person will readily understand that in such a case the relative permittivity value (permittivity) epsilon of each layer _r The thickness of each layer is set inversely proportional.

Conductive layers 7, 12: may be formed of any metal (e.g., al) or semi-metal (e.g., tiN) or semiconductor (e.g., polysilicon). In case a semiconductor is used, preferably the semiconductor is highly doped, and even more preferably degenerate.

The structure of a second embodiment of an electronic component 11 according to the invention is shown in a simplified manner in fig. 5. Elements identical or similar to those of the first embodiment are designated with the same reference numerals. To avoid repetition, only elements different from the first embodiment will be described below.

In the electronic component 11 according to the second embodiment of the present invention, the support layer 12 is a conductive layer which is a third electrode of the capacitive structure. A common potential Vs may be applied to the first and third electrodes (conductive layers 7 and 12), while a different potential V is applied _DD To the substrate/second electrode 2. As an example, the common potential Vs may be ground.

In the second embodiment of the present invention, in a region near the bottom of the well in the substrate where the electrostatic field is generally concentrated, the first electrode 7 and the third electrode 12 face each other, and the dielectric is sandwiched between the first electrode 7 and the third electrode 12. Since the first electrode 7 and the third electrode 12 are at the same potential, there is a further reduction in the electrostatic field strength in the dielectric in this region. More specifically, in effect, a back surface voltage biased to the same potential as the top electrode zeroes out the vertical component of the electric field.

The structure of an example of a third embodiment of an electronic component 21 according to the invention is shown in a simplified manner in fig. 6. Again, the same or similar elements as those of the first embodiment or the second embodiment are denoted by the same reference numerals, and only elements different from the first embodiment and the second embodiment will be described below.

At the rootIn the electronic component 21 according to the third embodiment of the present invention, the support layer 12 similarly provided below the insulating layer 10 is a conductive layer as a third electrode, a common potential Vs is applied to the first electrode and the third electrode, and different potentials V are applied _DD To the substrate/second electrode 2. Further, according to the third embodiment of the present invention, a groove or a through hole is provided in the insulating layer 10, and a conductive material is provided in the groove or the hole. It is convenient to use the same material for forming the conductive layer 12 and the conductive material present in the grooves or holes of the insulating layer 10, so that the total number of manufacturing steps can be reduced.

In the example shown in fig. 6, with respect to the middle well among the three wells shown in the figure, a via hole 10b is formed through the insulating layer 10 in the thickness direction of the insulating layer 10. The via 10b is under the region where the conductive layer/first electrode 7 is located at the bottom of the respective well. In this example, the conductive material fills the via hole 10b and actually reduces the distance between the first electrode 7 and the third electrode 12. Thus, the electrostatic field strength in the dielectric 5 at the bottom of the well is further reduced.

Although the example shown in fig. 6 shows the via hole 10b penetrating the entire thickness of the insulating layer 10, it may be sufficient to form the groove 10a penetrating a partial thickness of the insulating layer 10.

In the example shown in fig. 6, with respect to the right-hand well among the three wells shown in the drawing, not only the via hole 10b passing through the insulating layer 10 is formed, but also the groove 5a is formed in the dielectric in the thickness direction thereof. In this example, the recess 5a is substantially aligned with the via 10b through the insulating layer 10. In this example, a continuous column of conductive material 12d fills the via 10b and the recess 5a.

Fig. 7A to 7F show the effect on the electrostatic field strength achieved by patterning the insulating layer 10 and the optional dielectric 5 to include grooves or vias, and filling the grooves or vias with a conductive material. Fig. 7A to 7F are schematic diagrams showing results of simulations that model the intensity of electrostatic fields generated in various structures when a potential difference is applied to the first electrode and the third electrode of the general-type 3D capacitive structure shown in fig. 6.

Fig. 7A shows a comparative example in which the insulating layer 10 is not provided. As in the example shown in fig. 3B, there is a high electrostatic field concentrated in the portion of the dielectric that is located towards the inside of the bend in the dielectric.

Fig. 7B shows the electrostatic field intensity in the case where the insulating layer 10 is provided as in the first to third embodiments of the present invention. As can be seen from fig. 7B, the size of the dark gray region representing the highest electrostatic field intensity has decreased.

Fig. 7C shows a case where the insulating layer 10 is patterned to include a groove 10a, the groove 10a extending from a surface of the insulating layer away from the dielectric 5 toward the inside of the insulating layer 10. The recess 10a is substantially aligned with the central curved portion of the dielectric. A conductive material (not shown) fills the recess. As can be seen from fig. 7C, the dark gray region representing the highest electrostatic field intensity still has a continuously reduced size as compared to the comparative example. In addition, there is also some reduction in the electrostatic field strength in the "legs" on the left and right sides of the dielectric.

Fig. 7D shows a case where the insulating layer 10 is patterned to include the via hole 10b. The via 10b is substantially aligned with the central curved portion of the dielectric. A conductive material (not shown) fills the via hole 10b. As can be seen from fig. 7D, the size of the dark gray region representing the highest electrostatic field strength is further reduced. However, at the corner region C where the outermost part of the dielectric 5 is in contact with the insulating layer 10, there is a small region of high electrostatic field.

Fig. 7E shows a case where the dielectric 5 is patterned to include a groove 5a in a surface facing the third electrode 12 in a central portion thereof. A conductive material (not shown) fills the grooves 5a. In this case, although there is still a decrease in the electrostatic field strength in the central portion of the dielectric, the size of the high electrostatic field region at the angle C has increased.

Fig. 7F shows a comparative example in which the dielectric 5 is patterned to include the through-hole 5b in the central portion thereof. A conductive material (not shown) fills the through-hole 5b. In this case, although the electrostatic field strength in the dielectric has been greatly reduced, the size of the high electrostatic field region at the angle C has been further increased.

In the structure shown in fig. 7C, the geometry of the recess 10a follows that of the frontal groove. Thus, in case the well in the substrate is a cylindrical hole, the recess 10a is cylindrical, in case of a meander shaped trench, the recess 10a has the shape of a meander trench (defined by a continuous conductive vertical wall) or the like. The comments of this paragraph also apply to the through-hole 10b and the groove 5a in the configurations shown in fig. 7D, in the through-holes 10b, 7E.

It should also be noted that the width/diameter of the recess 10a should be set so as to leave a lateral thickness of the dielectric that matches or exceeds the thickness of the dielectric that is sunk into the 3D well. This is particularly important for the configuration shown in fig. 7E. In other words, the width of the groove 10a should not be larger than the tip of the inner conductor (indicated by reference numeral 7a in fig. 5 and 6).

It will be noted that in the structures shown in fig. 6 and 7B to 7E, the opening at the bottom of the well 3 is closed (blocked) by the dielectric 5, i.e. the dielectric layer is continuous across the opening. In other words, the dielectric 5 defines blind holes within the well and the first electrode 7 is within these blind holes. Thus, the first electrode layer 7 is prevented by the dielectric layer 5 from making electrical contact with the conductive layer 12 or with a conductive material that may be provided in the recesses 5a, 10a or in the through hole 10b.

In a currently preferred embodiment of the present invention, the insulating layer 10 is patterned and comprises a recess 10a or via 10b in which the conductive material is disposed, but the dielectric 5 is not patterned to comprise the recess 5a. It will be appreciated that such a currently preferred embodiment of the present invention includes a structure as shown in fig. 7C and 7D. On the other hand, the embodiments of fig. 7B, 7D, and 7E are preferable in view of convenience of manufacturing.

An example method of manufacturing the electronic component 41 based on the third embodiment will now be described with reference to fig. 8 and 9A to 9G. Fig. 8 is a flowchart showing a process included in the manufacturing method. Fig. 9A-9G illustrate component structures at various stages during the fabrication process. In the example shown in fig. 8 and 9A to 9G, the completed electronic component 41 has the insulating layer 10 patterned as in the example shown in fig. 7D to include the via holes 10b in the plurality of wells of the substrate 2.

In the example method illustrated by fig. 8, a silicon-on-insulator (SOI) wafer is used as a starting element.

In the example method illustrated by fig. 8, a silicon-on-insulator (SOI) wafer is used as a starting element, and the method begins with front side processing. In step S801, as illustrated in fig. 9A, a well 3 is formed in the substrate 2. This step may be performed in any convenient process, for example by etching. In some embodiments, the etching process is performed to stop on the Buried Oxide (BOX) of the SOI wafer, or the etching is performed to a depth determined by the etching time.

Next, as shown in fig. 9B, a dielectric layer 5 is deposited on the well walls and the bottom of the well (S802). Then, as shown in fig. 9C, a conductive layer 5 is deposited over the dielectric 5 (S803). The deposition of the dielectric layer 5 and the conductive layer 7 may be performed by well known processes, for example using an LPCVD process or a combination of an LPCVD process for the dielectric and an ALD process for the first electrode. The main advantage of these processes is that they are compatible with the deposition of layers within structures having a large aspect ratio. In the case of using a polymer dielectric as part of a MIM dielectric, convenient processes for depositing the dielectric layer include CVD or electrophoretic deposition. The benefit of using the latter process is that it produces a dielectric layer with a high degree of conformity with the underlying profile.

Next, the back surface of the wafer is processed. As shown in fig. 9D, the thickness of the substrate is reduced (S804). This may involve thinning the substrate 2 to the BOX of the SOI wafer or, if there is a large amount of substrate to remove, grinding of the back side may be performed followed by selective etching until the tips of the 3D structures are reached.

The grinding process is well known in the art and will not be described in detail herein, except as noted below. Typically, in the case of Si substrates, the grinding process approaches the tip of the BOX/3D structure at a distance of 10 μm to 15 μm. Final landing on the tip of the BOX/3D structure is by a wet etch stepOperated in a step, typically in a KOH bath. For example to SiO ₂ Or Al ₂ O ₃ The selectivity of the oxide is high and the etch will stop on these layers by itself.

The benefit of the two-stage process is that the rough grinding is a fast and low cost process established in many semiconductor manufacturing plants (fabs). However, this process generates mechanical defects (mainly dislocations) in the silicon, which may propagate over distances of several μm and may reach the interface of the oxide. Therefore, it is preferable to stop the mechanical grinding at a sufficient distance (10 μm to 15 μm) from the interface and complete the back surface exposure by a wet etching step without causing any mechanical stress.

In embodiments where the recess 5a is to be formed in the dielectric layer 5, the dielectric layer may be patterned from the back side to remove unwanted portions of the dielectric layer (S805).

As shown in fig. 9E, the insulating layer 10 is then formed (S806), and if necessary, the insulating layer 10 is patterned to form, for example, the groove 10a or the via hole 10b. As for the backside isolation layer 10, it may be formed as a BOX, for example, using direct oxide bonding, preferably at high temperature to enhance adhesion. The advantage of this solution is that the inherent quality of the buried oxide will be good, resulting in a high dielectric strength. In this case, the thickness of the insulating layer 10 will be of the order of the thickness of the MIM dielectric.

In the case of a backside post-treatment of the isolation layer 10, this layer may be formed using PECVD (in the case of oxides or nitrides) or CVD, spin-on coating or dry film lamination (in the case of polymers). Generally, the latter approach is currently less preferred because the dielectric strength of the resulting material is generally poor, making it necessary to increase the layer thickness to withstand the electric field.

In the case of a polymer dielectric for layer 10, good conformity of the deposited layer to the adjacent surface is achieved by using CVD or electrophoretic deposition.

Next, as shown in fig. 9F, a conductive layer 12 is deposited (S807). For the deposition of this planar layer, PVD is the preferred process because it is widely available in fabs and has limited cost.

To complete the capacitive structure, in step S808, as shown in fig. 9G, a contact portion (not shown) and a dedicated back end 15 are formed to enable application of electric potentials to the first electrode, the second electrode, and the third electrode.

The above description relates to a specific example method for manufacturing an electronic component according to the third embodiment of the present invention. However, the skilled person will readily understand from his common general knowledge how to adapt the described method for manufacturing the components according to the first and second embodiments.

Additional variants

Although the invention has been described above with reference to certain specific embodiments, it should be understood that the invention is not limited by the particulars of the specific embodiments. Many variations, modifications and developments of the above-described embodiments are possible within the scope of the appended claims.

Claims (13)

1. An electronic component (1/11/21) comprising a capacitive structure, the component (1) comprising:

a substrate (2) having a contoured surface (2 a) comprising a plurality of wells (3) extending into the substrate from the substrate surface;

a dielectric (5) formed over and conforming to the shape of the contoured surface (2 a) of the substrate, some portion of the dielectric being exposed through an opening at the bottom of the well (3) in the contoured surface of the substrate;

a first electrode (7) of the capacitive structure formed on the dielectric (5) and conforming to the shape of the contoured surface, the dielectric being interposed between the first electrode and the substrate (2) constituting a second electrode of the capacitive structure; and

an insulating layer (10) formed on a surface of the substrate remote from the contoured surface, the insulating layer being in contact with the dielectric (5) through the opening in the substrate;

wherein the opening at the bottom of the well (3) is closed by the dielectric (5), whereby the dielectric (5) defines a blind hole within the well and the first electrode (7) is in the blind hole.

2. The electronic component (11/21) of claim 1, comprising: a third electrode (12) formed on a surface of the insulating layer remote from the substrate; wherein contacts are provided to the first, second and third electrodes (7, 2, 12) to apply the same potential to the first and third electrodes (7, 12), but to apply different potentials to the second electrode (2).

3. The electronic component (21) according to claim 2, wherein the insulating layer (10) is a patterned layer having at least one groove (10 a) in its surface remote from the dielectric (5) at a position overlapping in plan view with a position of a proximal end portion (7 a) of the first electrode (7), and a conductive material is provided in the groove (10 a).

4. The electronic component (21) according to claim 3, wherein the insulating layer (10) is a patterned layer having at least one through-hole (10 b) at a position overlapping in a plan view with a position of a proximal end portion (7 a) of the first electrode (7) in a thickness direction thereof, and a conductive material is provided in the through-hole (10 b).

5. Electronic component (1/11/21) according to claim 2, wherein the insulating layer (10) and the dielectric (5) have the same composition and the thickness of the insulating layer (10) is the same as the thickness of the dielectric (5) or is larger than the thickness of the dielectric (5).

6. Electronic component (1/11/21) according to any of claims 1 to 5, wherein the dielectric (5) comprises a plurality of layers of dielectric material stacked on top of each other.

7. The electronic component (1/11/21) of claim 6, wherein the respective thicknesses of the layers of the stack are inversely proportional to the relative permittivity of the materials in the respective layers, thereby avoiding concentration of electric fields in any particular layer of the stack forming the dielectric (5).

8. A method of manufacturing an electronic component (1/11/21) comprising a capacitive structure, the method comprising:

providing a substrate having a contoured surface (2 a) comprising a plurality of wells (3) extending into the substrate from the substrate surface, the substrate (2) having an insulating layer (10) on its surface (2 b) remote from the contoured surface;

forming a dielectric (5) over the contoured surface (2 a) conforming to the shape of the contoured surface, portions of the dielectric (5) being exposed through an opening at the base of the well of the contoured surface of the substrate and in contact with the insulating layer (10) through the opening; and

-forming a conductive layer (7) over the dielectric (5) conforming to the shape of the contoured surface, the conductive layer (7) constituting a first electrode of the capacitive structure; wherein the dielectric (5) is interposed between the first electrode (7) and the substrate (2) constituting the second electrode of the capacitive structure; and

wherein the opening at the bottom of the well (3) is closed by the dielectric (5), whereby the dielectric (5) defines a blind hole within the well and the first electrode (7) is in the blind hole.

9. The manufacturing method according to claim 8, further comprising:

forming a conductive layer (12) on a surface of the insulating layer (10) remote from the substrate, the conductive layer (12) constituting a third electrode of the capacitive structure; and

forming contacts to the first, second and third electrodes (7, 2, 12) to apply the same potential to the first and third electrodes (7, 12), but to apply a different potential to the second electrode (2).

10. The manufacturing method according to claim 9, further comprising:

patterning the insulating layer (10) to form a groove (10 a) in a surface thereof remote from the dielectric (5) or a via hole (10 b) at a position overlapping in plan view with a position of a proximal end portion (7 a) of the first electrode (7); and

depositing a conductive material in the recess (10 a) or the via (10 b).

11. Manufacturing method according to any one of claims 8 to 10, wherein the insulating layer (10) and the dielectric (5) have the same composition and the thickness of the insulating layer (10) is the same as the thickness of the dielectric (5) or greater than the thickness of the dielectric (5).

12. The manufacturing method according to any one of claims 8 to 11, wherein the step of forming the dielectric includes: a plurality of dielectric material layers are formed stacked on top of each other.

13. The manufacturing method of claim 12, wherein the step of forming a plurality of dielectric material layers stacked on top of each other comprises: the thickness of the layers of the respective stack is set inversely proportional to the relative permittivity of the material constituting the respective layer, so as to avoid concentration of electric fields in any particular layer of the stack forming the dielectric (5).

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