JP2008084899A - Process for fabricating semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To form a sufficiently round shape at the upper edge of a trench and to suppress level difference in the vicinity of the trench when it is filled with an insulating material in the process for fabricating a semiconductor device forming an isolation region of STI structure. <P>SOLUTION: The process for fabricating a semiconductor device comprises a step for forming a trench 18 by etching a silicon substrate 11 using a sidewall insulating film 17 consisting of a laminate of at least a silicon oxide film 15 and a silicon nitride film 16 as a mask, a step for fomring a ringlike recess 19 in the sidewall of the trench 18 by etching the silicon oxide film 15 exposed from the silicon nitride film 16 in the trench 18, a step for forming a thermal oxidation film 20 by oxidizing the surface of the silicon substrate 11 exposed in the trench 18 including the recess 19, and a step for depositing an HDP-CVD film 21 on the entire surface including the trench 18. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a technique for forming an element isolation region having an STI (Sallow Trench Isolation) structure.

  A DRAM (Dynamic Random Access Memory) includes a memory cell as a unit of information storage. A memory cell is composed of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) formed on a surface portion of a silicon substrate and a capacitor connected to the MOSFET. By storing charges in the capacitor via the MOSFET, information is stored in the memory cell. To remember.

  In the surface portion of the silicon substrate, the element formation regions where the MOSFETs are formed are insulated from each other by the element isolation regions so that adjacent MOSFETs are not short-circuited. In recent years, with the miniaturization of DRAM, the area that one memory cell can occupy on a semiconductor substrate has been reduced. Accordingly, an element isolation region having an STI structure that can be formed with high dimensional controllability and a small occupation area is employed. The element isolation region having the STI structure is composed of a trench formed in the surface portion of the silicon substrate and an insulating material such as a silicon oxide film embedded in the trench.

  In forming an element isolation region having an STI structure, a mask pattern having a trench opening pattern is first formed on a silicon substrate, and then the silicon substrate is etched to a desired depth by dry etching using the mask pattern. Form. After an insulating material is deposited on the entire surface including the inside of the trench, the insulating material and the mask pattern deposited on the upper surface of the silicon substrate are removed.

  By the way, the trench formed by dry etching has a shape with a sharp upper edge. When the gate insulating film is formed on the element isolation region having such a shape, the gate insulating film is locally thinned in the vicinity of the upper edge of the trench, resulting in variations in gate capacitance and withstand voltage, or Defects such as electric field concentration occur in the thinned portion. Therefore, in order to prevent such thinning, thermal oxidation at a high temperature is performed prior to embedding the insulating material in the trench, and the viscous flow of the silicon oxide film (thermal oxide film) is used to A round shape is formed at the upper edge. This thermal oxidation process is generally called rounding oxidation.

  In order to form a round shape at the upper edge of the trench, it is necessary to expose the upper surface of the silicon substrate adjacent to the trench prior to rounding oxidation. 3 and 4 are cross-sectional views sequentially showing each manufacturing stage in a conventional manufacturing method for forming an element forming region having an STI structure. After a silicon oxide film 12 is formed on the silicon substrate 11 using a thermal oxidation method, a silicon nitride film 13 is deposited on the silicon oxide film 12 (FIG. 3A). The silicon oxide film 12 is formed for the purpose of relaxing the stress between the silicon substrate 11 and the silicon nitride film 13.

  After a resist pattern having an opening pattern corresponding to the shape of the element isolation region is formed on the silicon nitride film 13, the opening pattern 14 is formed in the silicon oxide film 12 and the silicon nitride film 13 by dry etching using this resist pattern. It forms (FIG.3 (b)). A thin silicon nitride film 17a is formed on the entire surface including the inside of the opening pattern 14 (FIG. 3C), and the silicon nitride film 17a on the silicon substrate 11 and the silicon nitride film 13 is removed by etch back, thereby opening the opening pattern. A side wall insulating film 17 is formed on the side surface of 14.

  Subsequently, using the same etching conditions, using the silicon nitride film 13 and the sidewall insulating film 17 as a mask, the silicon substrate 11 is etched to a desired depth to form a trench 18 in the surface portion of the silicon substrate 11 (FIG. 3D). )). The sidewall insulating film 17 is selectively removed to expose the upper surface of the silicon substrate 11 adjacent to the trench 18 (FIG. 4E). Next, a thermal oxide film 20 is formed on the surface of the silicon substrate 11 exposed in the trench 18 by rounding oxidation, and a round shape is formed at the upper edge of the trench 18.

A method for forming an element isolation region having an STI structure in which the sidewall portion of the mask pattern shown in FIGS. 3 and 4 is configured as the sidewall insulating film 17 is described in, for example, Patent Document 1.
Japanese Patent Laying-Open No. 2005-235986 (FIGS. 1 and 2)

  By the way, when forming an isolation region having an STI structure, a high density plasma chemical vapor deposition (HDP-CVD) method having a high burying property is generally used for embedding an insulating material in a trench. Used. In the HDP-CVD method, deposition is performed by applying a bias in a direction perpendicular to the substrate surface of the silicon substrate and accelerating ions toward the silicon substrate.

  However, in the manufacturing method shown in FIGS. 3 and 4, by removing the sidewall insulating film 17, the edge of the mask opening at the upper edge of the trench 18 and the thermal oxide film 20 are removed as shown in FIG. A step 31 is formed between the side surfaces of the two. However, ions accelerated to the silicon substrate 11 side by the HDP-CVD method have high straightness, so that they tend to adhere near the step 31.

  Therefore, when the insulating material is deposited inside the trench 18 using the HDP-CVD method, the insulating material is deposited in an overhang shape in the vicinity of the step 31, so that the opening of the trench 18 may be blocked. For this reason, as shown in FIG. 5, there is a problem that a void 32 is formed inside the trench 18.

  In recent years, with the miniaturization of semiconductor devices, the width of the trench 18 is being reduced to less than 100 nm. However, when the width of the trench 18 is less than 100 nm, ions adhering to the vicinity of the step 31 rapidly increase. The formation of 32 is rapidly promoted. Therefore, in order to achieve a reduction in the width of the trench 18 without degrading the reliability of the semiconductor device, a sufficient round shape can be formed at the upper edge of the trench 18 and the insulating material into the trench 18 can be formed. When embedding 21, it is necessary to suppress the step 31 in the vicinity thereof.

  In view of the above, the present invention is a method for manufacturing a semiconductor device in which an element isolation region having an STI structure is formed. The semiconductor device can form a sufficient round shape at the upper edge of a trench, and an insulating material is embedded in the trench. It is an object of the present invention to provide a method of manufacturing a semiconductor device that can suppress a step in the vicinity thereof.

In order to achieve the above object, a method for manufacturing a semiconductor device according to the present invention includes:
In a method for manufacturing a semiconductor device, a groove isolation region is formed on a silicon substrate.
Forming a first film on the upper surface of the silicon substrate;
Forming a mask having a groove pattern on the upper surface of the first film;
Forming a first opening through the first film and opening an upper surface portion of the silicon substrate by etching using the mask;
By sequentially depositing second and third films each made of an insulating material on the entire surface including the inside of the first opening and etching back the second and third films, the first and second films are etched back. Forming a sidewall made of the second and third films on the sidewall surface of the opening;
Etching the silicon substrate in the first opening using at least the sidewall as a mask to form a trench comprising the first opening and a second opening extending from the first opening;
Etching the second film exposed from the third film in the trench to form a ring-shaped recess in the sidewall portion of the trench;
Oxidizing the surface of the silicon substrate exposed in the trench including the recess to form a thermal oxide film;
Depositing an insulating film on the entire surface including the inside of the trench;
Removing the first film formed on the upper surface of the silicon substrate and the insulating film deposited above the lower surface of the first film by a planarization step. To do.

  According to the present invention, when the ring-shaped recess is formed, the upper surface of the silicon substrate adjacent to the trench can be exposed with a space corresponding to the increased film thickness when the thermal oxide film is formed. Therefore, when forming the thermal oxide film, the viscous flow of the silicon oxide film can be used to form a sufficiently rounded shape at the upper edge of the trench, and the inside of the recess is filled with the thermal oxide film, Can be suppressed.

  In a preferred aspect of the present invention, the first film includes a silicon oxide film and a silicon nitride film sequentially deposited on the upper surface of the silicon substrate. When etching the silicon substrate, high etch resistance can be obtained by the silicon nitride film. Further, the silicon oxide film can relieve stress generated between the silicon substrate and the silicon nitride film.

  In a preferred aspect of the present invention, the second film is a silicon oxide film, and the third film is a silicon nitride film. In forming the recess, the silicon oxide film can be selectively etched by utilizing the difference in etch rate between the silicon nitride film and the silicon oxide film.

  In a preferred aspect of the present invention, each of the second and third films has a thickness that is ½ of the thickness of the thermal oxide film. By making the height of the concave portion correspond to the increased film thickness due to rounding oxidation, the inside of the concave portion can be effectively filled with a thermal oxide film during rounding oxidation.

  In a preferred aspect of the present invention, the step of depositing the insulating film on the entire surface including the inside of the trench is performed by a plasma CVD method. An insulating film can be deposited with high embedding property. Since the plasma CVD method has high straightness of ions, if there is a step at the upper edge portion of the trench, the deposition is concentrated on the step portion, so that a void is easily formed. Therefore, it can be suitably applied to the present invention.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. 1 and 2 are cross-sectional views sequentially showing each manufacturing stage in a method for manufacturing a semiconductor device according to an embodiment of the present invention. First, using a thermal oxidation method, the substrate temperature is set to 850 ° C., and the silicon oxide film 12 is formed on the silicon substrate 11 to a thickness of 10 nm. Next, using a low pressure CVD method, the substrate temperature is set to 760 ° C., and a silicon nitride film 13 is deposited on the silicon oxide film 12 to a thickness of 120 nm (FIG. 1A). The silicon oxide film 12 is formed for the purpose of relaxing the stress between the silicon substrate 11 and the silicon nitride film 13.

A resist mask having an opening pattern corresponding to the element isolation region is formed on the silicon nitride film 13, and then dry etching is performed using the resist mask to form the opening pattern 14 on the silicon oxide film 12 and the silicon nitride film 13. Form. In dry etching, since the silicon substrate 11 is used as an etch stopper, the surface portion of the silicon substrate 11 is also slightly removed by over-etching. CF ₄ is used as an etching gas. Further, the resist mask is removed (FIG. 1B).

  Subsequently, using a low pressure CVD method, the substrate temperature is set to 680 ° C., and a silicon oxide film 15 is deposited to a thickness of 10 nm on the entire surface including the inside of the opening pattern 14 (FIG. 1C). By using the low pressure CVD method having high step coverage, a silicon oxide film 15 having a thickness of 10 nm can be deposited on the side surface of the opening pattern 14 as well as on the silicon substrate 11 and the silicon nitride film 13. The thickness of the silicon oxide film 15 is set to about half of the thickness of the thermal oxide film formed in the subsequent rounding oxidation.

  Next, using a low pressure CVD method, the substrate temperature is set to 680 ° C., and a silicon nitride film 16 is deposited on the silicon oxide film 15 to a thickness of 10 nm (FIG. 1D). The thickness of the silicon nitride film 16 is also set to about half of the thickness of the thermal oxide film formed in the subsequent rounding oxidation.

Subsequently, dry etching using CF ₄ is performed to etch back the stack of the silicon oxide film 15 and the silicon nitride film 16 on the silicon substrate 11 and the silicon nitride film 13, thereby stacking these stacks on the side surface of the opening pattern 14. The sidewall insulating film 17 is formed as it is. Subsequently, using the same etching conditions, using the silicon nitride film 13 and the sidewall insulating film 17 as a mask, the silicon substrate 11 is etched to a desired depth to form a trench 18 in the surface portion of the silicon substrate 11 (FIG. 2E )). Depending on the dry etching conditions, the formation of the sidewall insulating film 17 and the formation of the trench 18 may be performed in separate steps.

Next, wet etching is performed using buffered hydrofluoric acid having a liquid composition of HF 1.6%, NH ₄ F 38.7%, and H ₂ O 59.7%. Of these, the silicon oxide film 15 exposed in the trench 18 is retracted by 20 nm. If the etching rate of the silicon oxide film 15 by buffered hydrofluoric acid is 20 nm / min, it is performed for 60 seconds. Since the etching rate of the silicon nitride film 16 by buffered hydrofluoric acid is 0.5 nm / min or less, the silicon nitride film 16 is hardly etched during wet etching, and can function as a protective film for the silicon oxide film 15.

  As a result, a ring-shaped recess 19 having a height of 10 nm and a width of 20 nm is formed between the silicon substrate 11 and the sidewall insulating film 17 along the upper edge portion of the trench 18 (FIG. 2F). )). In addition, when the silicon oxide film 15 is excessively etched during wet etching, the silicon nitride film 16 may be lifted off. Therefore, the etching time is set carefully.

Subsequently, as a rounding oxidation, a silicon oxide film (thermal oxide film) 20 is formed to a thickness of 20 nm on the surface of the silicon substrate 11 exposed in the trench 18 using a thermal oxidation method (FIG. 2G). The rounding oxidation can be performed by steam oxidation using steam or dry oxidation using halogen or O ₂ radical. Prior to rounding oxidation, the surface of the silicon substrate 11 is exposed in the formed ring-shaped recess 19. For this reason, a sufficient round shape can be formed at the upper edge of the trench 18 by utilizing the viscous flow of the silicon oxide film.

  In the wet etching for forming the recess 19, the silicon nitride film 16 is left without being removed, so that the position of the side surface of the sidewall insulating film 17 and the position of the side surface of the thermal oxide film 20 are substantially aligned at the upper edge of the trench 18. I can do it. Further, since the recess 19 is formed to have a height and a width dimension corresponding to the film increase due to rounding oxidation, the recess 19 is almost completely filled with the thermal oxide film 20 during rounding oxidation. Therefore, the side surface of the sidewall insulating film 17 and the side surface of the thermal oxide film 20 are formed almost flat at the upper edge portion of the trench 18, and the step at the upper edge portion of the trench 18 is sufficiently suppressed.

  Next, a silicon oxide film (HDP-CVD film) 21 is deposited on the entire surface including the inside of the trench 18 by using the HDP-CVD method (FIG. 2H). When the HDP-CVD film 21 is deposited, the step at the upper edge of the trench 18 is sufficiently suppressed, so that no void is formed inside the trench 18. Subsequently, an element isolation region having an STI structure can be formed by performing a process such as removing a film deposited on the silicon substrate 11.

  According to the present embodiment, the sidewall insulating film 17 has a two-layer structure of the silicon oxide film 15 and the silicon nitride film 16, and only the silicon oxide film 15 is retracted by selective wet etching prior to rounding oxidation. By doing so, the step at the upper edge of the trench 18 after rounding oxidation can be made sufficiently small. Therefore, even when the trench 18 has a small width, voids can be suppressed when the HDP-CVD film 21 is embedded in the trench 18.

For embedding the insulating material inside the trench 18, in addition to the HDP-CVD method, an atmospheric pressure CVD method using O ₃ and TEOS or a coating method such as an SOG (Spin On Glass) method can also be used. . However, when these film forming methods are adopted, the film quality changes, so that it is necessary to change the subsequent process or the number of processes may be greatly increased. On the other hand, in the above-described embodiment, as compared with the manufacturing method of Patent Document 1, it is only necessary to increase the number of steps for depositing the silicon oxide film 15, so that an increase in manufacturing cost can be suppressed.

  As described above, the present invention has been described based on the preferred embodiments. However, the method for manufacturing a semiconductor device according to the present invention is not limited to the configuration of the above-described embodiment, and various modifications can be made from the configuration of the above-described embodiment. Modifications and changes are also included in the scope of the present invention.

FIG. 4 is a cross-sectional view sequentially showing each manufacturing stage in a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 2 is a cross-sectional view sequentially illustrating each manufacturing step subsequent to FIG. 1. It is sectional drawing which shows each manufacturing step sequentially about the conventional manufacturing method. FIG. 4 is a cross-sectional view sequentially illustrating each manufacturing step subsequent to FIG. 3. It is sectional drawing which shows the problem of the conventional manufacturing method.

Explanation of symbols

11: silicon substrate 12: silicon oxide film 13: silicon nitride film 14: opening pattern 15: silicon oxide film 16: silicon nitride film 17: sidewall insulating film 17a: silicon nitride film 18: trench 19: recess 20: thermal oxide film 21: HDP-CVD film (insulating material)
31: Step 32: Void

Claims (4)

In a method for manufacturing a semiconductor device, a groove isolation region is formed on a silicon substrate.
Forming a first film on the upper surface of the silicon substrate;
Forming a mask having a groove pattern on the upper surface of the first film;
Forming a first opening through the first film and opening an upper surface portion of the silicon substrate by etching using the mask;
By sequentially depositing second and third films each made of an insulating material on the entire surface including the inside of the first opening and etching back the second and third films, the first and second films are etched back. Forming a sidewall made of the second and third films on the sidewall surface of the opening;
Etching the silicon substrate in the first opening using at least the sidewall as a mask to form a trench comprising the first opening and a second opening extending from the first opening;
Etching the second film exposed from the third film in the trench to form a ring-shaped recess in the sidewall portion of the trench;
Oxidizing the surface of the silicon substrate exposed in the trench including the recess to form a thermal oxide film;
Depositing an insulating film on the entire surface including the inside of the trench;
Removing the first film formed on the upper surface of the silicon substrate and the insulating film deposited above the lower surface of the first film by a planarization step. A method for manufacturing a semiconductor device.   The method of manufacturing a semiconductor device according to claim 1, wherein the first film includes a silicon oxide film and a silicon nitride film sequentially deposited on an upper surface of a silicon substrate.   The method of manufacturing a semiconductor device according to claim 1, wherein the second film is a silicon oxide film, and the third film is a silicon nitride film.   The method of manufacturing a semiconductor device according to claim 1, wherein each of the second and third films has a thickness that is ½ of a thickness of the thermal oxide film.

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