CN112309835A - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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CN112309835A
CN112309835A CN201910701233.7A CN201910701233A CN112309835A CN 112309835 A CN112309835 A CN 112309835A CN 201910701233 A CN201910701233 A CN 201910701233A CN 112309835 A CN112309835 A CN 112309835A
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mask layer
organic
substrate
mask
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CN112309835B (en
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郑二虎
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H01L21/0276—Photolithographic processes using an anti-reflective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0332—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7853—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the body having a non-rectangular crossection
    • H01L29/7854—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the body having a non-rectangular crossection with rounded corners

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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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Abstract

A semiconductor structure and a forming method thereof are provided, wherein the forming method comprises the following steps: providing a substrate, wherein the substrate comprises an initial substrate, and a device mask layer and a pseudo mask layer which are positioned on the initial substrate; forming an organic pattern layer exposing the pseudo mask layer on the initial substrate, wherein the material of the organic pattern layer contains carbon and oxygen, and the ratio of the mole percent of the oxygen to the mole percent of the carbon in the organic pattern layer is more than or equal to 1.25; removing the exposed pseudo mask layer by taking the organic graphic layer as a mask; removing the organic graphic layer after removing the pseudo mask layer; and after removing the organic pattern layer, etching the initial substrate by taking the device mask layer as a mask layer to form the substrate and the fin part positioned on the substrate. The oxygen content in the organic pattern layer is higher, so that the hardness of the organic pattern layer is higher, the damage of the organic pattern layer is smaller in the process of removing the pseudo mask layer, the mask layer of a device is not easy to be subjected to false etching, the quality of the formed fin part is higher, and the improvement of the electrical performance of a semiconductor structure is facilitated.

Description

Semiconductor structure and forming method thereof
Technical Field
Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same.
Background
With the continuous improvement of the integration level of the integrated circuit, the integrated circuit is rapidly developed to the submicron and deep submicron directions, the line width of the pattern of the integrated circuit is thinner and thinner, and the higher requirement is provided for the semiconductor process. Therefore, it is an urgent subject to study how to realize fine line width patterns to meet new requirements of semiconductor processes.
Photolithography (Lithograph) is a key process technology for implementing integrated circuit patterns. In the photolithography technique, a photosensitive material (photoresist) is coated on a thin film of a substrate, light of a wavelength band corresponding to the photosensitive characteristic of the photoresist is adopted, the light is irradiated to the surface of the photoresist through a mask plate with a specific pattern, and a photoresist pattern corresponding to the pattern on the mask plate is formed after development. In the subsequent process of the integrated circuit, the photoresist pattern is used as a barrier layer to selectively etch the film below the photoresist pattern, so that the pattern on the mask plate can be completely transferred to the film on the substrate.
Photoresists, antireflective coatings and organic materials in the lithographic process have a tremendous impact on the accuracy of pattern transfer in lithography.
Disclosure of Invention
The embodiment of the invention provides a semiconductor and a forming method thereof, and aims to improve the electrical performance of a device.
To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a base, wherein the base comprises a device area and an isolation area, the base comprises an initial substrate and a substrate mask layer positioned on the initial substrate, the substrate mask layer positioned on the device area is a device mask layer, and the substrate mask layer positioned on the isolation area is a pseudo mask layer; forming an organic pattern layer exposing the pseudo mask layer on the initial substrate, wherein the material of the organic pattern layer contains carbon and oxygen, and the molar percentage ratio of the oxygen to the carbon in the organic pattern layer is greater than or equal to 1.25; taking the organic graphic layer as a mask, and removing the exposed pseudo mask layer; removing the organic pattern layer after removing the pseudo mask layer; and after removing the organic pattern layer, etching the initial substrate by taking the device mask layer as a mask layer to form a substrate and a fin part positioned on the substrate.
Correspondingly, an embodiment of the present invention further provides a semiconductor structure, including: the substrate comprises an initial substrate and a substrate mask layer positioned on the initial substrate; the substrate mask layer positioned on the device area is a device mask layer, and the substrate mask layer positioned on the isolation area is a pseudo mask layer; and the organic graphic layer is positioned on the initial substrate, covers the device mask layer and exposes the pseudo mask layer, the material of the organic graphic layer contains carbon and oxygen, and the ratio of the mole percent of the oxygen to the mole percent of the carbon in the organic graphic layer is greater than or equal to 1.25.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
the organic graphic layer of the embodiment of the invention exposes the pseudo mask layer, the ratio of the mole percent of oxygen to the mole percent of carbon in the organic graphic layer is more than or equal to 1.25, the organic pattern layer has a higher oxygen content than a Spin On Carbon (SOC) material, so that the organic pattern layer has a higher hardness, therefore, in the process of removing the pseudo mask layer, compared with the scheme of adopting a spin-coating carbon material, the etching rate of the organic pattern layer is smaller, so that the damage of the organic pattern layer is smaller, correspondingly, after the pseudo mask layer is removed, the roughness of the side wall of the organic pattern layer is small, so that the mask layer of the device is not easy to expose, and then the device mask layer is not easy to be subjected to error etching, so that the quality of a fin part formed by etching the initial substrate by taking the device mask layer as a mask is higher, and the improvement of the electrical property of the semiconductor structure is facilitated.
Drawings
Fig. 1 to 6 are schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure;
fig. 7 to 15 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Detailed Description
The devices formed at present still have the problem of poor performance. The reason for the poor performance of the device is analyzed in combination with a method for forming a semiconductor structure.
Fig. 1 to 6 are schematic structural diagrams corresponding to respective steps in a method for forming a semiconductor structure.
As shown in fig. 1, a base is provided, the base including an isolation region I and a device region II, the base including an initial substrate 1 and a core layer 2 on the initial substrate 1.
As shown in fig. 2 and 3, conformally covering a side wall material layer 3 on the core layer 2 and the initial substrate 1 exposed from the core layer 2 (as shown in fig. 2); removing the side wall material layer 3 on the core layer 2 and on the initial substrate 1, and using the remaining side wall material layer 3 on the side wall of the core layer 2 as a side wall layer 4, wherein the side wall layer 4 on the device region II is used as a device mask layer 42, and the side wall layer 4 on the isolation region I is used as a pseudo mask layer 41; after the side wall layer 4 is formed, the core layer 2 is removed.
As shown in fig. 4, forming an organic material layer 5 covering the sidewall layer 4; an anti-reflection coating 6 and a photoresist layer 7 on the anti-reflection coating 6 are formed on the organic material layer 5, and the photoresist layer 7 exposes the anti-reflection coating 6 above the dummy mask layer 41.
As shown in fig. 5, the photoresist layer 7 is used as a mask to etch and remove the dummy mask layer 41.
As shown in fig. 6, removing the organic material layer 5 (as shown in fig. 5); and after removing the organic material layer 5, etching the initial substrate 1 by using the device mask layer 42 as a mask to form a substrate 8 and a fin part 9 on the substrate 8.
The organic material layer 5 is generally made of Spin On Carbon (SOC), the content of oxygen in the spin on carbon is low, the molar percentage of oxygen is usually in a range of 4.4% to 15%, the hardness of the spin on carbon is low, the organic material layer 5 is easily etched in the process of removing the pseudo mask layer 41, so that the organic material layer 5 is easily exposed out of the device mask layer 42, the device mask layer 42 is easily mistakenly etched, correspondingly, the fin portion 9 formed by subsequently etching the initial substrate 1 by using the damaged device mask layer 42 as a mask is poor in quality, and the electrical performance of the semiconductor structure is reduced.
In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a base, wherein the base comprises a device area and an isolation area, the base comprises an initial substrate and a substrate mask layer positioned on the initial substrate, the substrate mask layer positioned on the device area is a device mask layer, and the substrate mask layer positioned on the isolation area is a pseudo mask layer; forming an organic pattern layer exposing the pseudo mask layer on the initial substrate, wherein the material of the organic pattern layer contains carbon and oxygen, and the molar percentage ratio of the oxygen to the carbon in the organic pattern layer is greater than or equal to 1.25; taking the organic graphic layer as a mask, and removing the exposed pseudo mask layer; removing the organic pattern layer after removing the pseudo mask layer; and after removing the organic pattern layer, etching the initial substrate by taking the device mask layer as a mask layer to form a substrate and a fin part positioned on the substrate.
The organic graphic layer of the embodiment of the invention exposes the pseudo mask layer, the ratio of the mole percent of oxygen to the mole percent of carbon in the organic graphic layer is more than or equal to 1.25, the organic pattern layer has a higher oxygen content than a Spin On Carbon (SOC) material, so that the organic pattern layer has a higher hardness, therefore, in the process of removing the pseudo mask layer, compared with the scheme of adopting a spin-coating carbon material, the etching rate of the organic pattern layer is smaller, so that the damage of the organic pattern layer is smaller, correspondingly, after the pseudo mask layer is removed, the roughness of the side wall of the organic pattern layer is small, so that the mask layer of the device is not easy to expose, and then the device mask layer is not easy to be subjected to error etching, so that the quality of a fin part formed by etching the initial substrate by taking the device mask layer as a mask is higher, and the improvement of the electrical property of the semiconductor structure is facilitated.
In order to make the aforementioned objects, features and advantages of the embodiments of the present invention comprehensible, specific embodiments accompanied with figures are described in detail below.
Fig. 7 to 15 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Referring to fig. 7 to 9, a base is provided, where the base includes an isolation region I and a device region II, the base includes an initial substrate 100 and a substrate mask layer 101 (shown in fig. 9) located on the initial substrate 100, the substrate mask layer 101 located on the device region II is a device mask layer 1011 (shown in fig. 9), and the substrate mask layer 101 located on the isolation region I is a dummy mask layer 1012 (shown in fig. 9).
The substrate provides a process foundation for subsequently forming the semiconductor structure.
The present embodiment takes the formed semiconductor structure as a fin field effect transistor (FinFET) as an example.
In this embodiment, the material of the initial substrate 100 is silicon. In other embodiments, the substrate material may also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.
The device mask layer 1011 serves as a mask layer for subsequent etching of the initial substrate 100 to form a fin portion.
Specifically, the material of the device mask layer 1011 includes one or more of titanium oxide, silicon nitride, and silicon. In this embodiment, the mask layer 1011 of the device is made of silicon nitride.
In this embodiment, the device mask layer 1011 and the dummy mask layer 1012 are made of the same material. In other embodiments, the device mask layer and the dummy mask layer may be made of different materials.
The step of forming the substrate mask layer 101 includes: as shown in fig. 7, a core layer 104 is formed on the initial substrate 100; as shown in fig. 8, conformally covering a side wall material layer 105 on the core layer 104 and the initial substrate 100 exposed from the core layer 104; as shown in fig. 9, the side wall material layer 105 on the core layer 104 (shown in fig. 8) and on the initial substrate 100 is removed, the remaining side wall material layer 105 on the core layer 104 is used as the substrate mask layer 101, and after the substrate mask layer 101 is formed, the core layer 104 is removed.
In this embodiment, the sidewall material layer 105 is formed by an Atomic Layer Deposition (ALD) process. The ald process includes performing a plurality of ald cycles to form a sidewall material layer 105 of a desired thickness. By selecting the atomic layer deposition process, the thickness uniformity of the side wall material layer 105 is improved, so that the thickness of the side wall material layer 105 can be accurately controlled; in addition, the atomic layer deposition process has good gap filling performance and step coverage, and accordingly conformal coverage capability of the side wall material layer 105 is improved. In other embodiments, other deposition processes may be further used to form the side wall material layer, for example: chemical vapor deposition processes, and the like.
The substrate further comprises: a first masking material layer 102 located between the initial substrate 100 and the substrate masking layer 101; a second masking material layer 103 is located between the first masking material layer 102 and the substrate masking layer 101.
In the subsequent formation process of the semiconductor structure, the device mask layer 1011 is used as a mask to etch the first mask material layer 102 and the second mask material layer 103, so as to form a first mask layer and a second mask layer.
The etching rate of the second mask material layer 103 is less than the etching rate of the sidewall material layer 105 (as shown in fig. 8). The second mask material layer 103 is used as an etching stop layer in the process of forming the substrate mask layer 101, so that the forming rates of the substrate mask layers 101 on the second mask material layer 103 are easy to be consistent.
The first mask material layer 102 is etched at a rate less than that of the second mask material layer 103. In the subsequent process of etching the second mask material layer 103 to form the second mask layer, the first mask material layer 102 is used as an etching stop layer, so that the etched rates of the second mask material layer 103 at various positions on the first mask material layer 102 are consistent. Therefore, in the subsequent process of etching the initial substrate 100 to form the fin portion by using the first mask layer and the second mask layer as masks, the uniformity of the height of the fin portion is favorably ensured to be good.
The material of the first mask material layer 102 and the second mask material layer 103 each include one or more of silicon nitride, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the first mask material layer 102 is made of silicon nitride, and the second mask material layer 103 is made of silicon oxynitride.
It should be noted that the substrate further includes: a buffer layer 106 between the first masking material layer 102 and the initial substrate 100.
The difference between the thermal expansion coefficients of the first mask material layer 102 and the initial substrate 100 is large, and if the first mask material layer 102 is directly formed on the initial substrate 100, the first mask material layer 102 is prone to crack and even fall off. The buffer layer 106 is used for reducing stress between the initial substrate 100 and the first mask material layer 102, so as to improve adhesion of the substrate mask layer 101.
In this embodiment, the buffer layer 106 is made of silicon oxide.
Referring to fig. 10 to 12, an organic pattern layer 107 (as shown in fig. 12) exposing the dummy mask layer 1012 is formed on the initial substrate 100, the material of the organic pattern layer 107 includes carbon and oxygen, and a ratio of mole percentages of oxygen and carbon in the organic pattern layer 107 is greater than or equal to 1.25.
The ratio of the mole percentages of oxygen and carbon in the organic patterning layer 107 is greater than or equal to 1.25, the higher molar percentage of oxygen in the organic pattern layer 107, as compared to a Spin On Carbon (SOC) material, results in a higher hardness of the organic pattern layer 107, therefore, during the subsequent removal of the dummy mask layer 1012, compared to the solution of spin-coating a carbon material, the etched rate of the organic pattern layer 107 is smaller, so that the damage of the organic pattern layer 107 is smaller, and accordingly, after the dummy mask layer 1012 is removed, the side wall roughness of the organic pattern layer is small, so that the device mask layer 1011 is not easily exposed, furthermore, the device mask layer 1011 is not prone to being etched by mistake, so that the fin portion formed by etching the initial substrate 100 with the device mask layer 1011 as a mask is high in quality, and the improvement of the electrical performance of the semiconductor structure is facilitated.
The organic pattern layer 107 exposes the dummy mask layer 1012 in preparation for subsequent removal of the dummy mask layer 1012.
In this embodiment, the material of the organic pattern layer 107 is oxidized amorphous carbon (a-COx).
In this embodiment, the ratio of the mole percentages of oxygen and carbon in the organic pattern layer 107 is greater than or equal to 1.25.
If the molar percentage ratio of oxygen to carbon in the organic pattern layer 107 is too small, the hardness of the organic pattern layer 107 is easily low, the damage of the organic pattern layer 107 is large in the subsequent process of removing the pseudo mask layer 1012, and correspondingly, in the process of removing the pseudo mask layer 1012, the roughness of the side wall of the remaining organic pattern layer 107 is large, the device mask layer 1011 is easily exposed, the device mask layer 1011 is easily subjected to false etching, so that the quality of a fin portion formed by subsequently etching the initial substrate 100 by using the device mask layer 1011 as a mask is poor.
In this embodiment, the ratio of the mole percentages of oxygen and carbon in the organic pattern layer 107 is less than or equal to 5.
If the ratio of the mole percentages of oxygen and carbon in the organic pattern layer 107 is too large, the filling property of the oxidized amorphous carbon is poor in the process of forming the organic pattern layer 107, so that voids are easily formed in the organic pattern layer 107, and in the subsequent process of removing the pseudo mask layer 1012, the etching selectivity of the pseudo mask layer 1012 and the organic pattern layer 107 is low, so that the device mask layer 1011 is exposed from the organic pattern layer 107, and the device mask layer 1011 is easily damaged.
Therefore, in this embodiment, the ratio of the mole percentages of oxygen and carbon in the organic pattern layer 107 is greater than or equal to 1.25 and less than or equal to 5. For example: the ratio of the mole percentages of oxygen and carbon in the organic pattern layer 107 is 2, 3, 4, or 5, etc.
Specifically, the step of forming the organic pattern layer 107 includes:
as shown in fig. 10, an organic material film 108 is formed to cover the substrate mask layer 101.
In this embodiment, the organic material film 108 is formed by a Physical Vapor Deposition (PVD) process. The physical vapor deposition process has the advantages of low deposition temperature (usually below 550 ℃), high deposition speed, controllable components and structure of a deposition layer, simple operation, high efficiency and low cost, and the physical vapor deposition process has high compatibility with the existing machine and process flow.
Specifically, the physical vapor deposition process is a Sputtering process (Sputtering), the organic material film 108 is formed by using the Sputtering process, and the Sputtering process includes the steps of: introducing O into the reaction chamber in the sputtering process2。
During sputtering, the O2For providing oxygen in the organic material film 108.
Specifically, the process parameters of the sputtering process include: the material of the target comprises graphite; the sputtering power is 300W to 1000W; o is2The flow rate of (2) is 10sccm to 200 sccm; the chamber pressure is 5 to 50 ubar.
It should be noted that the sputtering power is not too high nor too low. If the sputtering power is too high, a void may be easily formed in the organic material film 108, so that the organic pattern layer 107 may be damaged in the subsequent etching process for removing the pseudo mask layer 1012 by using the organic pattern layer 107 as a mask, and the organic pattern layer 107 may be exposed out of the device mask layer 1011, thereby causing the device mask layer 1011 to be damaged. If the sputtering power is too low, it takes too much process time to form the organic material film 108. In this embodiment, the sputtering power is 300W to 1000W.
In addition, the above-mentioned O is2The flow rate should not be too large or too small. If said O is2Too high flow rate of the organic pattern layer is likely to cause too high mole percentage of oxygen in the formed oxidized amorphous carbon, the filling property of the corresponding oxidized amorphous carbon is poor, and voids are likely to exist in the organic pattern layer 107, and in the subsequent process of removing the pseudo mask layer 1012, the etching selectivity of the pseudo mask layer 1012 and the organic pattern layer 107 is low, so that the organic pattern layer 107 is exposed out of the device mask layer 1011, and the device mask layer 1011 is likely to be damaged. If said O is2Too low flow rate, which tends to result in too low mole percentage of oxygen in the formed organic material film 108, resulting in insufficient hardness of the organic material film 108, and during the subsequent removal of the dummy mask layer 1012, the organic pattern layer 107 tends to expose the device mask layer 1011, thereby causing the device mask layer 1011 to be easily damaged. In this example, the O2The flow rate of (b) is 10sccm to 200 sccm.
It should be noted that the chamber pressure is not too high nor too low. If the chamber pressure is too high, process controllability and reaction rate uniformity may be reduced, which may easily cause voids in the organic material film 108. If the chamber pressure is too low, it may result in excessive process time being required to form the organic material film 108. In this embodiment, the chamber pressure is 5 to 50 ubar.
It is to be noted that the graphite usually contains a part of hydrogen element. In the process of bombarding the graphite target to form the oxidized amorphous carbon, the oxidized amorphous carbon contains hydrogen elements.
However, the molar percentage of hydrogen in the material of the organic material film 108 is not preferably too high. The energy of the hydrogen is relatively large, and the hydrogen ions easily break the C — C bond during the formation of the organic material film 108, resulting in a lower hardness of the organic pattern layer 107 being formed. Therefore, if the mole percentage of hydrogen in the organic material film 108 is too high, the hardness of the formed organic pattern layer 107 is low, and correspondingly, in the process of removing the pseudo mask layer 1012, the roughness of the side wall of the organic pattern layer 107 is large, so that the device mask layer 1011 is easily exposed, the device mask layer 1011 is easily subjected to false etching, and the quality of a fin portion formed by subsequently etching the initial substrate 100 by using the device mask layer 1011 as a mask is poor. In the present embodiment, the mole percentage of hydrogen in the organic material film 108 is less than or equal to 3%.
In the present embodiment, by using the sputtering process, it is also easy to control the mole percentage of hydrogen in the material of the organic material film 108 in a low range.
As shown in fig. 11 and 12, the organic material film 108 is etched by a partial thickness, a recess 109 exposing the top of the dummy mask layer 1012 is formed in the organic material film 108 (as shown in fig. 12), and the remaining organic material film 108 serves as the organic pattern layer 107 (as shown in fig. 12).
The recess 109 exposes the top of the dummy mask layer 1012 in preparation for subsequent removal of the dummy mask layer 1012. By forming the groove 109, on one hand, the etching amount of the organic material film 108 is small, and the probability that the device mask layer 1011 is exposed from the organic pattern layer 107 after the groove 109 is formed is low, and on the other hand, when the pseudo mask layer 1012 is subsequently etched by using a dry etching process, polymer impurities are generated and formed on the side wall of the groove 109, so that the device mask layer 1011 covered by the organic pattern layer 107 is not easily etched by mistake.
As shown in fig. 11, the step of forming the organic pattern layer 107 further includes: after the organic material film 108 is formed and before the organic material film 108 is etched to the partial thickness, an anti-reflective coating 110 and a photoresist layer 111 on the anti-reflective coating 110 are formed on the organic material film 108, and the photoresist layer 111 exposes the anti-reflective coating 110 above the dummy mask layer 1012.
In the step of forming the groove 109, the anti-reflective coating layer 110 and the organic material film 108 having a partial thickness are etched using the photoresist layer 111 as a mask, so that the groove 109 is formed.
In this embodiment, the organic pattern layer 107 is formed by etching the organic material film 108 with a partial thickness by a dry etching process. The dry etching process is an anisotropic etching process, has good etching profile controllability, is beneficial to enabling the top of the pseudo mask layer 1012 to be exposed out of the groove 109, and the device mask layer 1011 is not exposed out of the groove, and can accurately control the removal thickness of the organic material film 108 and reduce damage to other film structures by taking the top of the pseudo mask layer 1012 as an etching stop position in the dry etching process. In addition, the antireflective coating 110 and the organic material film 108 can be etched in the same etching apparatus by replacing the etching gas, simplifying the process steps.
In this embodiment, the material of the organic material film 108 is amorphous carbon, and correspondingly, the etching gas for the dry etching includes a first reaction gas and a second reaction gas, where the first reaction gas includes one or more of fluorocarbon gas, hydrofluorocarbon gas, and hydrocarbon gas, and the second reaction gas includes CO, CO2、COS、SO2And O2The flow rate of the first reactant gas is greater than the flow rate of the second reactant gas.
The second reactive gas has a higher etching rate for the organic material film 108, and the carbon content in the first reactive gas is high, so that by making the flow rate of the first reactive gas larger than that of the second reactive gas, more polymer impurities are generated in the process of forming the groove 109 by etching, the polymer impurities are easily formed on the sidewall of the groove 109, and the included angle between the sidewall of the formed groove 109 and the normal of the substrate 100 is smaller, so that the device fin 1011 is not easily etched by mistake in the subsequent process of removing the dummy fin 1012.
Referring to fig. 13, the exposed dummy mask layer 1012 is removed using the organic pattern layer 107 as a mask.
The dummy mask layer 1012 is removed in preparation for subsequent fin formation by etching the initial substrate 100 using the device mask layer 1011 as a mask.
In the process of removing the dummy mask layer 1012 exposed on the organic pattern layer 107, the etching rate of the dummy mask layer 1012 is greater than that of the organic pattern layer 107.
In this embodiment, the dummy mask layer 1012 exposed by the groove 109 is removed by a wet etching process. The dummy mask layer 1012 is made of silicon nitride, and correspondingly, the etching solution of the wet etching process is phosphoric acid solution. In other embodiments, when the material of the dummy mask layer is silicon oxide, the etching solution of the wet etching process is a hydrogen fluoride solution.
In other embodiments, the dummy mask layer exposed by the groove may be removed by a dry etching process. The pseudo mask layer is made of silicon nitride, and correspondingly, the etching gas of the dry etching process is one or more of fluorocarbon gas, fluorocarbon gas and hydrocarbon gas.
Because the organic pattern layer 107 covers the device mask layer 1011, the device mask layer 1011 is not easily damaged in the process of removing the dummy mask layer 1012, and the formation quality of the formed fin portion is better when the initial substrate 100 is etched by using the device mask layer 1011 as a mask.
Referring to fig. 14, after removing the dummy mask layer 1012, the organic pattern layer 107 is removed (as shown in fig. 13).
In this embodiment, the organic pattern layer 107 is removed by a dry etching process.
In this embodiment, the ratio of the mole percentages of oxygen and carbon in the organic pattern layer 107 is greater than or equal to 1.25 and less than or equal to 5.
Correspondingly, the etching gas of the dry etching process comprises the following components: a first reaction gas and a second reaction gas, wherein the first reaction gas comprises one or more of fluorocarbon gas, fluorocarbon gas and hydrocarbon gas, and the second reaction gas comprises CO and CO2、COS、SO2And O2The flow rate of the first reaction gas is smaller than that of the second reaction gasDepending on the flow rate of the gas.
The second reaction gas has a higher etching rate on the organic pattern layer 107, the organic pattern layer 107 can be removed faster by enabling the flow rate of the first reaction gas to be smaller than that of the second reaction gas, and the damage to the device fin portion 1011 during the process of removing the organic pattern layer 108 is reduced, so that the quality of the subsequently formed fin portion is good.
Referring to fig. 15, after removing the organic pattern layer 107, the initial substrate 100 is etched using the device mask layer 1011 (shown in fig. 14) as a mask layer, so as to form a substrate 112 and a fin 113 located on the substrate 112.
In this embodiment, the device mask layer 1011 is used as a mask, and the initial substrate 100 is etched by a dry etching process (as shown in fig. 14), so as to form the substrate 112 and the fin portion 113 located on the substrate 112. The dry etching process is an anisotropic etching process, has good etching profile controllability, is favorable for enabling the appearance of the fin portion 113 to meet the process requirements, and is also favorable for improving the forming efficiency of the fin portion 113. And the fin portion 113 is formed by etching the initial substrate 100 by using a dry etching process, which is beneficial to accurately controlling the removal thickness of the material of the initial substrate 100, namely, the height of the fin portion 113 can be accurately controlled.
The method for forming the semiconductor structure further includes: before the initial substrate 100 is etched by taking the device mask layer 1011 as a mask, the first mask material layer 102 and the second mask material layer 103 are also etched by taking the device mask layer 1011 as a mask, so that a first mask layer 114 and a second mask layer 115 on the first mask layer 114 are formed.
In the process of forming the fin portion 113, the device mask layer 1011 is easily lost, and the first mask layer 114 and the second mask layer 115 continue to serve as etching masks for etching the initial substrate 100 to form the fin portion 113, so that the roughness of the side wall surface of the formed fin portion 113 is small, and the electrical performance of the semiconductor structure is improved.
It should be noted that, the first mask material layer 102 and the second mask material layer 103 are etched by using a dry etching process to form a first mask layer 114 and a second mask layer 115 on the first mask layer 114. The dry etching process is an anisotropic etching process, has good etching profile controllability, is favorable for making the roughness of the side walls of the first mask layer 114 and the second mask layer 115 smaller, and is favorable for reducing the surface roughness of the side walls of the fin portions 113 in the process of etching the fin portions 113 formed on the initial substrate 100 by using the first mask layer 114 and the second mask layer 115 as masks.
It should be noted that, in the process of etching to form the fin portion 113, the buffer layer 106 is also etched, and the detailed process is not described herein again.
Correspondingly, the embodiment of the invention also provides a semiconductor structure. Referring to fig. 12, a schematic structural diagram of an embodiment of a semiconductor structure of the present invention is shown.
The semiconductor structure includes: the substrate comprises a device area II and an isolation area I, and comprises an initial substrate 100 and a substrate mask layer 101 positioned on the initial substrate 100; the substrate mask layer 101 on the device region is a device mask layer 1011, and the substrate mask layer 101 on the isolation region is a pseudo mask layer 1012; and the organic pattern layer 107 is positioned on the initial substrate 100, the organic pattern layer 107 covers the device mask layer 1011 and exposes the pseudo mask layer 1012, the material of the organic pattern layer 107 contains carbon and oxygen, and the ratio of the mole percent of the oxygen to the mole percent of the carbon in the organic pattern layer 107 is greater than or equal to 1.25.
The organic pattern layer 107 exposes the dummy mask layer 1012, the ratio of the mole percentages of oxygen and carbon in the organic pattern layer 107 is greater than or equal to 1.25, and compared with materials such as Spin On Carbon (SOC), the organic pattern layer 107 has a higher oxygen content, so that the hardness of the organic pattern layer 107 is higher, therefore, in the subsequent process of removing the dummy mask layer 1012, compared with a scheme of using a spin on carbon material, the etching rate of the organic pattern layer 107 is lower, so that the damage of the organic pattern layer 107 is smaller, correspondingly, in the process of removing the dummy mask layer 1012, the roughness of the side wall of the organic pattern layer 107 is smaller, so that the device mask layer 1011 is not easily exposed, and further the device mask layer 1011 is not easily subjected to false etching, so that the quality of a fin portion formed by subsequently etching the initial substrate 100 by using the device mask layer 1011 as a mask is higher, the method is favorable for improving the electrical property of the semiconductor structure.
The substrate provides a process foundation for subsequently forming the semiconductor structure.
In the present embodiment, the semiconductor structure is exemplified by forming a fin field effect transistor (FinFET).
In this embodiment, the material of the initial substrate 100 is silicon. In other embodiments, the substrate material may also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.
The device mask layer 1011 serves as a mask layer for subsequent etching of the initial substrate 100 to form a fin portion.
Specifically, the material of the device mask layer 1011 includes one or more of titanium oxide, silicon nitride, and silicon. In this embodiment, the mask layer 1011 of the device is made of silicon nitride.
In this embodiment, the device mask layer 1011 and the dummy mask layer 1012 are made of the same material. In other embodiments, the device mask layer and the dummy mask layer may be made of different materials.
The substrate further comprises: a first masking material layer 102 located between the initial substrate 100 and the substrate masking layer 101; a second masking material layer 103 is located between the first masking material layer 102 and the substrate masking layer 101.
In the subsequent formation process of the semiconductor structure, the device mask layer 1011 is used as a mask to etch the first mask material layer 102 and the second mask material layer 103, so as to form a first mask layer and a second mask layer.
In the process of forming the substrate mask layer 101, the second mask material layer 103 serves as an etching stop layer.
The second mask material layer 103 is etched at a rate less than that of the first mask material layer 102. In the subsequent process of etching the second mask material layer 103 to form a second mask layer, the first mask material layer 102 is used as an etching stop layer, so that the etched rates of the second mask material layer 103 at various positions on the first mask material layer 102 are consistent. Therefore, in the subsequent process of etching the initial substrate 100 to form the fin portion by using the first mask layer and the second mask layer as masks, the uniformity of the height of the fin portion is favorably ensured to be good.
It should be noted that the substrate further includes: a buffer layer 106 between the first masking material layer 102 and the initial substrate 100.
The difference between the thermal expansion coefficients of the first mask material layer 102 and the initial substrate 100 is large, and if the first mask material layer 102 is directly formed on the initial substrate 100, the first mask material layer 102 is prone to crack and even fall off. The buffer layer 106 is used for reducing stress between the initial substrate 100 and the first mask material layer 102, so as to improve adhesion of the substrate mask layer 101.
In this embodiment, the buffer layer 106 is made of silicon oxide.
The organic pattern layer 107 exposes the dummy mask layer 1012 in preparation for subsequent removal of the dummy mask layer 1012 using the organic pattern layer 107 as a mask.
In this embodiment, the material of the organic pattern layer 107 is oxidized amorphous carbon.
In this embodiment, the ratio of the mole percentages of oxygen and carbon in the organic pattern layer 107 is greater than or equal to 1.25.
If the molar percentage ratio of oxygen to carbon in the organic pattern layer 107 is too small, the hardness of the organic pattern layer 107 is easily low, the damage of the organic pattern layer 107 is large in the subsequent process of removing the pseudo mask layer 1012, and correspondingly, in the process of removing the pseudo mask layer 1012, the roughness of the side wall of the remaining organic pattern layer 107 is large, the device mask layer 1011 is easily exposed, the device mask layer 1011 is easily subjected to false etching, so that the quality of a fin portion formed by subsequently etching the initial substrate 100 by using the device mask layer 1011 as a mask is poor.
In this embodiment, the ratio of the mole percentages of oxygen and carbon in the organic pattern layer 107 is less than or equal to 5.
If the ratio of the mole percentages of oxygen and carbon in the organic pattern layer 107 is too large, the filling property of the oxidized amorphous carbon is poor in the process of forming the organic pattern layer 107, so that voids are easily formed in the organic pattern layer 107, and in the subsequent process of removing the pseudo mask layer 1012, the etching selectivity of the pseudo mask layer 1012 and the organic pattern layer 107 is low, so that the device mask layer 1011 is exposed from the organic pattern layer 107, and the device mask layer 1011 is easily damaged.
Therefore, in this embodiment, the ratio of the mole percentages of oxygen and carbon in the organic pattern layer 107 is greater than or equal to 1.25 and less than or equal to 5. For example: the ratio of the mole percentages of oxygen and carbon in the organic pattern layer 107 is 2, 3, 4, or 5, etc.
It should be noted that the hydrogen content in the material of the organic pattern layer 107 is not excessively high. However, the hydrogen content in the material of the organic pattern layer 107 is not preferably too high. The energy of the hydrogen is relatively large, and hydrogen ions are likely to break C-C bonds during the process of forming the organic pattern layer 107, resulting in a lower hardness of the formed organic pattern layer 107. Therefore, if the hydrogen content in the organic pattern layer 107 is too high, the hardness of the formed organic pattern layer 107 is low, and accordingly, in the process of removing the pseudo mask layer 1012, the roughness of the side wall of the organic pattern layer 107 is large, so that the device mask layer 1011 is easily exposed, the device mask layer 1011 is easily subjected to false etching, and the quality of a fin portion formed by subsequently etching the initial substrate 100 by using the device mask layer 1011 as a mask is poor. In this embodiment, the mole percentage of hydrogen in the organic pattern layer 107 is less than or equal to 3%.
In this embodiment, the material of the organic pattern layer 107 is oxidized amorphous carbon.
In this embodiment, a groove 109 is formed in the organic pattern layer 107, and the bottom of the groove 109 exposes the top of the dummy mask layer 1012.
The recess 109 exposes the top of the dummy mask layer 1012 in preparation for subsequent removal of the dummy mask layer 1012. By forming the groove 109, on one hand, the etching amount of the organic material film 108 is small, and the probability that the device mask layer 1011 is exposed from the organic pattern layer 107 after the groove 109 is formed is low, and on the other hand, when the pseudo mask layer 1012 is subsequently etched by using a dry etching process, polymer impurities are generated and formed on the side wall of the groove 109, so that the device mask layer 1011 covered by the organic pattern layer 107 is not easily etched by mistake.
The semiconductor structure of this embodiment may be formed by the formation method described in the foregoing embodiment, or may be formed by other formation methods. For a detailed description of the semiconductor structure in this embodiment, reference may be made to the corresponding description in the foregoing embodiments, and details of this embodiment are not repeated herein.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (20)

1. A method of forming a semiconductor structure, comprising:
providing a base, wherein the base comprises a device area and an isolation area, the base comprises an initial substrate and a substrate mask layer positioned on the initial substrate, the substrate mask layer positioned on the device area is a device mask layer, and the substrate mask layer positioned on the isolation area is a pseudo mask layer;
forming an organic pattern layer exposing the pseudo mask layer on the initial substrate, wherein the material of the organic pattern layer contains carbon and oxygen, and the molar percentage ratio of the oxygen to the carbon in the organic pattern layer is greater than or equal to 1.25;
taking the organic graphic layer as a mask, and removing the exposed pseudo mask layer;
removing the organic pattern layer after removing the pseudo mask layer;
and after removing the organic pattern layer, etching the initial substrate by taking the device mask layer as a mask layer to form a substrate and a fin part positioned on the substrate.
2. The method of claim 1, wherein a ratio of mole percent of oxygen to mole percent of carbon in the organic patterning layer is less than or equal to 5.
3. The method of claim 1, wherein the material of the organic patterning layer further comprises hydrogen, and wherein the mole percentage of hydrogen in the organic patterning layer is less than or equal to 3%.
4. The method for forming a semiconductor structure according to any one of claims 1 to 3, wherein a material of the organic pattern layer is oxidized amorphous carbon.
5. The method of forming a semiconductor structure according to any one of claims 1 to 3, wherein the step of forming the organic pattern layer comprises:
forming an organic material film covering the substrate mask layer;
and etching the organic material film with partial thickness, forming a groove exposing the top of the pseudo mask layer in the organic material film, and taking the residual organic material film as the organic pattern layer.
6. The method for forming a semiconductor structure according to any one of claims 5, wherein the organic material film is formed by a physical vapor deposition process.
7. The method of forming a semiconductor structure according to claim 6, wherein the organic material film is formed using a sputtering process, the sputtering process including: introducing O into the reaction chamber in the sputtering process2。
8. The method of forming a semiconductor structure of claim 7, wherein the process parameters of the sputtering process comprise: the sputtering power is 300W to 1000W; o is2The flow rate of (2) is 10sccm to 200 sccm; the chamber pressure is 5 to 50 ubar.
9. The method of forming a semiconductor structure of claim 5, wherein the step of forming the organic patterning layer further comprises: after forming the organic material film and before etching the organic material film with the partial thickness, forming an anti-reflection coating and a photoresist layer on the anti-reflection coating on the organic material film, wherein the photoresist layer exposes the anti-reflection coating above the pseudo mask layer;
the step of forming the groove includes: and etching the anti-reflection coating and the organic material film with partial thickness by taking the photoresist layer as a mask.
10. The method for forming a semiconductor structure according to claim 5, wherein the organic pattern layer is formed by etching a part of the organic material film by a dry etching process.
11. The method of claim 10, wherein the etching gas of the dry etching process comprises a first reactive gas and a second reactive gas, the first reactive gas comprises one or more of a fluorocarbon gas, a hydrofluorocarbon gas and a hydrocarbon gas, and the second reactive gas comprises CO, CO2、COS、SO2And O2The flow rate of the first reactant gas is greater than the flow rate of the second reactant gas.
12. The method of forming a semiconductor structure according to any of claims 1 to 3, wherein a material of the substrate mask layer comprises one or more of titanium oxide, silicon nitride, and silicon.
13. The method of forming a semiconductor structure of claim 12, wherein removing the exposed dummy mask layer comprises: and performing dry etching on the exposed pseudo mask layer by adopting one or more of fluorocarbon gas, fluorocarbon gas and hydrocarbon gas.
14. The method for forming a semiconductor structure according to any one of claims 1 to 3, wherein the organic pattern layer is removed by a dry etching process, and an etching gas of the dry etching process includes: a first reaction gas and a second reaction gas, wherein the first reaction gas comprises one or more of fluorocarbon gas, fluorocarbon gas and hydrocarbon gas, and the second reaction gas comprises CO and CO2、COS、SO2And O2The flow rate of the first reactant gas is less than the flow rate of the second reactant gas.
15. A semiconductor structure, comprising:
the substrate comprises an initial substrate and a substrate mask layer positioned on the initial substrate, the substrate mask layer positioned on the device area is a device mask layer, and the substrate mask layer positioned on the isolation area is a pseudo mask layer;
and the organic graphic layer is positioned on the initial substrate, covers the device mask layer and exposes the pseudo mask layer, the material of the organic graphic layer contains carbon and oxygen, and the ratio of the mole percent of the oxygen to the mole percent of the carbon in the organic graphic layer is greater than or equal to 1.25.
16. The semiconductor structure of claim 15, wherein a ratio of mole percent of oxygen to mole percent of carbon in the organic patterning layer is less than or equal to 5.
17. The semiconductor structure of claim 15, wherein a hydrogen content in the organic patterning layer is less than or equal to 3%.
18. The semiconductor structure of any one of claims 15 to 17, wherein a material of the organic pattern layer is oxidized amorphous carbon.
19. The semiconductor structure of claim 15, wherein a recess is formed in the organic pattern layer, a bottom of the recess exposing a top of the dummy mask layer.
20. The semiconductor structure of claim 15, wherein a material of the substrate mask layer comprises one or more of titanium oxide, silicon nitride, and silicon.
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Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1332472A (en) * 2000-06-22 2002-01-23 三菱电机株式会社 Fine graphic forming method and method for making semiconductor device using the same
US8753940B1 (en) * 2013-03-15 2014-06-17 Globalfoundries Inc. Methods of forming isolation structures and fins on a FinFET semiconductor device
CN105826193A (en) * 2015-01-07 2016-08-03 中芯国际集成电路制造(上海)有限公司 Formation method of semiconductor device
US20170146908A1 (en) * 2014-08-22 2017-05-25 Fujifilm Corporation Pattern forming method and method for manufacturing electronic device using same
CN108962990A (en) * 2017-05-23 2018-12-07 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof
CN109478022A (en) * 2016-06-08 2019-03-15 东京毅力科创株式会社 There is machine mandrel's guard method
US20190198398A1 (en) * 2017-12-27 2019-06-27 International Business Machines Corporation Simplified block patterning with wet strippable hardmask for high-energy implantation

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1332472A (en) * 2000-06-22 2002-01-23 三菱电机株式会社 Fine graphic forming method and method for making semiconductor device using the same
US8753940B1 (en) * 2013-03-15 2014-06-17 Globalfoundries Inc. Methods of forming isolation structures and fins on a FinFET semiconductor device
US20170146908A1 (en) * 2014-08-22 2017-05-25 Fujifilm Corporation Pattern forming method and method for manufacturing electronic device using same
CN105826193A (en) * 2015-01-07 2016-08-03 中芯国际集成电路制造(上海)有限公司 Formation method of semiconductor device
CN109478022A (en) * 2016-06-08 2019-03-15 东京毅力科创株式会社 There is machine mandrel's guard method
CN108962990A (en) * 2017-05-23 2018-12-07 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof
US20190198398A1 (en) * 2017-12-27 2019-06-27 International Business Machines Corporation Simplified block patterning with wet strippable hardmask for high-energy implantation

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