CN112306767A - Automatic testing method for chip signal connection relation - Google Patents

Abstract

The invention discloses an automatic testing method for a chip signal connection relation, and belongs to the field of chip verification. The automatic testing method comprises the steps of automatically setting up a general verification environment, processing a signal connection relation form by a script, automatically updating relevant verification environment codes, driving excitation into a chip input signal in a specific mode, and automatically comparing the correctness of the signal connection of the chip by the script. The relation of iterative signal connection is recorded through the form, so that the method is clear, strong in readability, easier in problem positioning, convenient for later maintenance and capable of reducing communication cost of designers and verifiers; the script automation process greatly reduces the time and labor cost of the verification personnel when updating the verification environment and improves the code accuracy; the script automatically tests the correctness of the chip signal connection, greatly shortens the verification period, avoids the risks brought by verification and comparison by naked eyes, and improves the reliability, the sufficiency and the accuracy of verification.

Description

Automatic testing method for chip signal connection relation

Technical Field

The invention belongs to the field of chip verification, relates to the fields of MCU (micro program controller), digital ASCI (application specific integrated circuit) and SoC (system on chip), and particularly relates to an automatic test method for chip signal connection relation.

Background

For a chip, time to market is one of the most important factors in determining whether it can succeed. To win the market, it is only the basic condition that the chips with quality passing through are provided on time, and products with superior quality can be released within a specified time range, so that the market can be won. With the continuous development of integrated circuit technology and design capability, chips become more and more complex, and in order to realize high-quality chips with the increasingly complex structure and the increasing size, a large amount of design and verification work time is needed, and the verification work almost occupies 70% or more of the whole workload in the development process of the chips, so that the quality of the verification work directly influences whether the chips can occupy the market or not. How to improve the chip verification efficiency, shorten the verification time and improve the verification quality is the most critical link in chip development.

In the traditional verification process, the verification sufficiency is guaranteed by the experience of verification personnel to a great extent, along with the fact that the chip scale is larger and larger, even if verification engineers with abundant experience are used in a lot of verification work, the verification work is difficult to easily deal with, and the verification of the signal connection relation of the chip is just the work. In terms of verification, although verification of the signal connection relationship seems to be functionally not difficult, the verification is very complicated, and by adopting the traditional verification method, because the existing chip has a huge number of signals, the chip is very time-consuming and very easy to make mistakes, and meanwhile, the correctness of the chip signal connection relationship directly influences the success or failure of the chip, which is also an indispensable and crucial verification work, how to improve the efficiency and quickly and accurately perform the verification work on the chip signal connection verification work becomes a topic of great concern in the industry. The traditional verification method focuses more on the verification of the function points, the verification of the function points occupies more than 70% of the verification workload, and the verification which does not contain many function points and is extremely complicated, such as the correctness of chip signal connection, is lack of attention and research.

When the size of the previous chip is not large, the number and complexity of corresponding chip connection signals are not large, and the verification work can be completed by using a traditional verification method. With the increasing scale of chips, signals of many chips reach thousands of signals, and at this time, the difficulty of verifying the connection correctness of each signal by adopting a traditional verification mode is very huge.

In the past decade, the verification methodology has undergone a major change, systemveilog has become the major verification language, and UVM has also become the mainstream verification methodology through the fusion of various dynamic verification methodologies. At present, most verification engineers develop verification work based on SystemVerilog and UVM. The working idea of verifying the correctness of the chip signal connection by adopting SystemVerilog and UVM is as follows: and (4) establishing a verification environment, driving in excitation for signals, monitoring the reaction of all signals, and comparing the connectivity in the scoreboard. In the process, excitation, monitoring signals and scoreboard comparison are input, verification personnel manually inputs and processes all signals, but chip signals are changed with development of design codes at any time, if the change is not recorded in detail by the design personnel, the verification personnel is used for comparison and search and then manually modify, the process is a very complicated and error-prone process, the change of each signal at least relates to modification of sequences, drivers, detectors, scoreboards and the like, the situation that omission and error modification are almost necessary occurs, the difficulty in comparison of connection results after final simulation is finished is also huge, and the verification work of the correctness of chip signal connection is often regarded as 'twice as a half work' because simulation record files reach hundreds of thousands of millions of lines and the labor time cost of debugging and positioning is huge.

Disclosure of Invention

Aiming at the defects in the prior art, the invention aims to solve the problems of high error probability, high time and high labor cost during the process of manually modifying chip signals and verifying the correctness of signal connection, and provides an automatic test method for the connection relation of the chip signals.

In order to achieve the above purpose, the present invention adopts the following technical scheme.

An automatic test method for chip signal connection relation comprises the following steps:

step one, automatically building a general verification environment;

secondly, processing a signal connection relation form by a script;

step three, automatically updating the relevant verification environment codes;

inputting excitation;

and step five, automatically comparing the correctness of the chip signal connection by the script.

Preferably, the second step specifically comprises the following steps:

the script automatically reads the form information and pre-processes the read information.

Preferably, the third step specifically includes the following steps:

storing the data after form information preprocessing into a database;

the script automatically generates the data in the database into the code involved in the verification environment.

Preferably, in step four, the input stimulus is given by: in turn, each input signal input stimulus is applied at each clock cycle, and the corresponding signal connected with the root signal responds at the corresponding clock cycle to form a paired signal connection relationship.

Preferably, the step five specifically includes the following steps:

and the script tool automatically processes the record file after the simulation is finished, extracts paired signal connection information, extracts the signal connection relation in the form for automatic comparison, and compares whether the signal connection has omission or errors.

Preferably, the recording file formed after the simulation is finished records paired input signals and output signals at a certain time to show the connection relationship between the signals, and includes the following information: simulation time, input and output signals in the distinguishing connection relation, corresponding signal instantiation names and the setting condition of the signals at the current simulation time.

Preferably, the script processes the record file and extracts effective information, wherein the effective information comprises chip signals at the same simulation time;

and judging to obtain a signal connection relation according to the effective information, and automatically comparing the signal connection relation with the original connection relation in the form.

Preferably, the automatic comparison process is:

firstly, signal omission errors are checked, and then the cyclic checking is carried out until all signal connection relations generated by design simulation meet the connection requirements of an original form, so that the test is judged to be passed.

Preferably, the pre-treatment comprises: names are treated as being in a form that conforms to the convention of designing code, and/or special symbols are removed, and/or case-unified, and/or prefix-suffixes are added as needed.

Preferably, the verification environment comprises an input agent, an output agent, and a scoreboard;

the input agent is provided with a sequence generator, a driver and a detector, and is used for generating excitation and monitoring output signals;

the output agent is provided with a detector for monitoring the output signal;

a scoreboard in the environment is used to print the incoming and outgoing information into a log file in a format that facilitates scripting.

Compared with the prior art, the invention has the following remarkable technical effects:

the invention realizes the automatic generation of the general verification environment and carries out the automatic test aiming at the specific verification scene of the correctness of the signal connection of the chip. Extracting chip signals according to the form providing the chip signal connection relation and automatically generating codes related to chip connection signal parts required in the verification environment, so that the problems that manual processing of the codes of the parts is troublesome and error is easy to occur are solved; the input signal of the chip is excited in a specific mode, the recorded file after the simulation is finished is processed by using the script, the correctness of the signal connection is automatically checked, the manual inspection process is omitted, and the reliability is higher. Specifically, the beneficial effects of the three aspects can be summarized as follows:

firstly, record the relation of iteration signal connection through the form, it is clear, readability is strong, and the problem is fixed a position more easily, makes things convenient for later maintenance, reduces designer and verifier's communication cost. Secondly, the script automation process greatly reduces the time and labor cost of the verification personnel when updating the verification environment and improves the accuracy of the codes. Thirdly, the script automatically tests the correctness of the chip signal connection, greatly shortens the verification period, avoids the risks brought by the verification and comparison by naked eyes, and improves the reliability, the sufficiency and the accuracy of the verification.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required to be used in the embodiments of the present invention will be briefly described below, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

FIG. 1 is a flow chart of the automated testing of the signal connection of the chip of the present invention;

FIG. 2 is a diagram of a verification environment of the present invention;

FIG. 3 is a simulation results record;

fig. 4 is a signal connection detection result record.

Detailed Description

Features and exemplary embodiments of various aspects of the present invention will be described in detail below, and in order to make objects, technical solutions and advantages of the present invention more apparent, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not to be construed as limiting the invention. It will be apparent to one skilled in the art that the present invention may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present invention by illustrating examples of the present invention.

The invention uses a technical scheme, can use a script tool to read the updated chip signal connection form, automatically generates the corresponding verification environment code, and automatically compares the correctness of the signal connection relation by using the script, thereby overcoming the defects mentioned in the background technology, greatly saving the labor cost, shortening the verification period and improving the accuracy and the reliability of the verification.

The technical scheme comprises the following steps:

step 1, automatically building a universal verification environment;

step 2, processing a signal connection relation form by a script;

step 3, automatically updating the relevant verification environment codes;

step 4, driving excitation into a chip input signal in a specific mode;

and 5, automatically comparing the correctness of the chip signal connection by the script.

In the step 1, generating a general verification environment by using a script, and forming a verification environment suitable for the current design to be tested on the basis;

in step 2, for large-scale chip design, before chip connection design, a form is used for recording the connection relation of signals, so that the signal connection relation and subsequent iteration are convenient to clear. The script may automatically read the information in the form.

In step 3, after the form data is read by the script, the form data is processed and stored in the database, and the relevant codes of the verification environment are automatically generated according to the preprocessed data in the database, so that the verification environment can be quickly and correspondingly upgraded after each form modification, and the risk of manually modifying the verification environment is reduced.

In step 4, aiming at the verification of the signal connection relation of the chip, the technical scheme adopts a specific mode to drive excitation into the design to be tested, namely, one input signal is driven into the excitation in each clock period, and the corresponding signal connected with the signal responds in the corresponding clock period to form a paired signal connection relation.

In step 5, the script tool can automatically process the recording file after the simulation is finished, extract paired signal connection information, extract the signal connection relation in the form for automatic comparison, and compare whether the signal connection of the chip design file has omission and errors with the design requirement.

Example one

Fig. 1 is a flowchart of an automated testing method for chip signal connection according to an embodiment of the present invention, which realizes automation of a process from reading signal information from a form to update a verification environment code to automatically compare the correctness of signal connection. As shown in fig. 1, the method comprises 5 steps: the method comprises the steps of automatically generating a general verification environment, processing a signal connection relation form by a script, automatically updating a relevant verification environment code, inputting an excitation in a specific mode and automatically comparing the signal connection correctness of a chip by the script.

Step 1: the script automatically generates a general verification environment, only comprises basic components of the verification environment and ensures the compilation correctness. And adding verification codes required by verifying the design to be tested on the basis of the verification codes.

Step 2: the script processes the signal connection relation form. The designer fills chip signal connection information into the form, clears the connection relation, and uses iterative form information as a record for modifying the signal connection relation, and the script automatically reads the form information and preprocesses the read data, for example, the signal name is in a character string format, the name needs to be processed into a form conforming to the habit of design codes, special symbols are removed, case and case are unified, and prefix and suffix are added according to requirements, for example, the following table 1 is a signal connection form style in a standard format.

Table 1 signal connection form styles

As shown in the style of table 1, the form for recording the signal connection information has a standard format, table 1 only gives an example of a partial style, and in the example, it can be seen that there are two signals PE3 and PE4, where PE3 is connected to the TRACED0 when the function is selected, and is connected to the TIM1_ CH1 when the function is selected, and similarly, the connection relationship of PE4 needs to verify whether the connection relationship in the final design code is correct.

And step 3: the relevant verification environment code is automatically updated. The chip signal connection relation can be modified along with the development of design codes, particularly in large-scale chip design, signals needing to be connected on the top layer are thousands of signals, and for verification personnel, after the verification environment is built, the modification of the design signals can bring many difficulties to verification. For example, when there is no detailed design modification record, the verifier needs to find out which signals have been modified, which is a very time-consuming and labor-consuming process, and then modifies the corresponding verification environment part, which generally includes testing top-level signal connections, sequence parts, monitors, drivers, interfaces and other verification components, and which needs to be updated, and is also a very tedious and error-prone process. According to the technical scheme, the form information is automatically read, the data after the form information is preprocessed are placed into the database, then the data in the database automatically generate codes related to the verification environment by using the script, iterative updating of the original verification environment is achieved, time cost of the step can be greatly reduced, and meanwhile reliability is improved. For example, if the signal of traced2 is added to the function signal corresponding to the signal PE3 in the form information, components such as top-level instantiations, drivers, sequencers, monitors, comparators, etc. in the corresponding verification environment need to update the relevant codes of the signal of traced 2.

And 4, step 4: the specific mode drives in excitation to the chip input signal. The technical scheme of the invention is to verify the signal connection of the chip, and mainly verifies whether the paired connection between the signals is correct or not, compared with whether the signals in the design to be tested are omitted or not according to the design requirement. According to the technical scheme, when the design to be tested is excited, the traditional excitation mode is not adopted, and excitation is sequentially input into each input signal in each clock period. As shown in fig. 2, the UVM verification environment in this embodiment mainly includes an input agent, an output agent, and a scoreboard, the input agent includes a sequencer, a driver, and a detector for generating an excitation and monitoring output signal, the output agent includes a detector for monitoring the output signal, and the scoreboard in the environment is used for printing the input and output information into a recording file in a format convenient for script processing.

And 5: and the script automatically compares the correctness of the connection relation of the chip signals. After the simulation is finished, a recording file with a specific format is generated, as shown in fig. 3, the recording file needs to include the following main information: simulation time, input and output signals in the distinguishing connection relation, corresponding signal instantiation names and the setting condition of the signals at the current simulation time. By recording paired input signals and output signals at a certain moment, no matter how complex the logic of design codes is, the connection relation between the signals is clearly shown, the script processes the record file, further extracts effective information, and extracts chip signals at the same simulation time, as shown in fig. 3, when 16885000ns, the input signal tracked 0_ dout is excited, and at the same time, three output signals, namely, umode _ pe3_ dout, umode _ pc1_ dout and umode _ pg13_ dout, are correspondingly pulled up, so that the tracked 0_ dout and the other three signals are judged to be in a corresponding relation in pairs. Because most of the designs of chip connection relation only contain combinational logic, the input and output time is the same, if the design contains sequential logic, the input simulation time is different from the output simulation time, but the input simulation time and the output simulation time are regular, and the corresponding processing can be carried out.

And automatically comparing the extracted signal connection relation with the original connection relation in the form, firstly checking signal omission errors, and performing cycle check until all signal connection relations generated by design simulation meet the original form connection requirement and can not pass the original form connection requirement. As shown in table 1, the input/output port signal is PE3, PE3 is instantiated as umode _ PE3_ dout in the design to be tested, and the signal having traced0 connected to PE3 is instantiated as traced0_ dout in the design. It is required to compare whether signals filled in the form are omitted in the design to be tested, the second half part in fig. 4 is the pair signals ('tracked 0_ dout', 'mode _ pe3_ dout') further extracted from the record file in fig. 3, and the first half part is the pair information ('pe 3', 'tracked 0') extracted from the form, and by comparing the core keywords 'pe 3' and 'tracked 0', it is determined that the signals are not omitted and are connected correctly. If the connection relation is missing, the connection missing error is directly printed and the traversal comparison is quitted, and the signal of the design to be tested, which is compared with the missing signal in the original form, can be quickly positioned according to the printing information and the quitting position. This procedure saves labor cost greatly because it can ensure the accuracy and reliability of signal connection relationship verification, and the comparison result is shown in fig. 4.

The verification environment in this embodiment may be implemented using a language other than systemvverilog and UVM, such as Verilog.

The scripting tool may be written in Python, Perl, etc. languages by those skilled in the art according to the description of the present embodiment.

It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

The above description is only an example of the present application and is not intended to limit the present application. Various modifications and changes may occur to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.

Claims (10)

1. An automated testing method for chip signal connection relationship, the method comprising:

step one, automatically building a general verification environment;

secondly, processing a signal connection relation form by a script;

step three, automatically updating the relevant verification environment codes;

inputting excitation;

and step five, automatically comparing the correctness of the chip signal connection by the script.

2. The method according to claim 1, wherein the second step specifically comprises the steps of:

the script automatically reads the form information and pre-processes the read information.

3. The method according to claim 1, wherein the third step specifically comprises the steps of:

storing the data after form information preprocessing into a database;

the script automatically generates the data in the database into the code involved in the verification environment.

4. The method of claim 1, wherein:

in step four, the input excitation mode is as follows: in turn, each input signal input stimulus is applied at each clock cycle, and the corresponding signal connected with the root signal responds at the corresponding clock cycle to form a paired signal connection relationship.

5. The method according to claim 4, wherein the step five specifically comprises the steps of:

and the script tool automatically processes the record file after the simulation is finished, extracts paired signal connection information, extracts the signal connection relation in the form for automatic comparison, and compares whether the signal connection has omission or errors.

6. The method of claim 5, wherein:

recording the paired input signals and output signals at a certain moment by a recording file formed after the simulation is finished so as to show the connection relation between the signals, wherein the recording file comprises the following information: simulation time, input and output signals in the distinguishing connection relation, corresponding signal instantiation names and the setting condition of the signals at the current simulation time.

7. The method of claim 5, wherein:

processing the record file by the script, and extracting effective information, wherein the effective information comprises chip signals at the same simulation time;

and judging to obtain a signal connection relation according to the effective information, and automatically comparing the signal connection relation with the original connection relation in the form.

8. The method of claim 7, wherein:

the automatic comparison process comprises the following steps:

firstly, signal omission errors are checked, and then the cyclic checking is carried out until all signal connection relations generated by design simulation meet the connection requirements of an original form, so that the test is judged to be passed.

9. The method of claim 2, wherein:

the pretreatment comprises the following steps: names are treated as being in a form that conforms to the convention of designing code, and/or special symbols are removed, and/or case-unified, and/or prefix-suffixes are added as needed.

10. The method according to one of claims 1 to 9, characterized in that:

the verification environment comprises an input agent, an output agent and a scoreboard;

the input agent is provided with a sequence generator, a driver and a detector, and is used for generating excitation and monitoring output signals;

the output agent is provided with a detector for monitoring the output signal;

a scoreboard in the environment is used to print the incoming and outgoing information into a log file in a format that facilitates scripting.

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