CN112306728A - Inverse processing fault-tolerant method based on monitoring pair architecture - Google Patents
Inverse processing fault-tolerant method based on monitoring pair architecture Download PDFInfo
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- CN112306728A CN112306728A CN202011227055.8A CN202011227055A CN112306728A CN 112306728 A CN112306728 A CN 112306728A CN 202011227055 A CN202011227055 A CN 202011227055A CN 112306728 A CN112306728 A CN 112306728A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
- G06F11/0721—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment within a central processing unit [CPU]
- G06F11/0724—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment within a central processing unit [CPU] in a multiprocessor or a multi-core unit
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/008—Reliability or availability analysis
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/079—Root cause analysis, i.e. error or fault diagnosis
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Abstract
The application provides a reverse processing fault-tolerant method based on a monitoring pair framework, which is applied to a monitoring pair framework fault-tolerant computer platform and comprises the following steps: the signal source respectively sends signal source DATA to a signal processing front end A and a signal processing front end B, and the signal source DATA is processed to obtain DATA DATAIN(ii) a The signal processing front-end A converts the input DATA DATAINSending it to CPU _ A, which applies a control law algorithm to the input DATA DATAINProcess f (DATA)IN) Obtaining a processing result A: rA(x) And processing the result RA(x) Sending to CPU _ B; CPU _ B compares the processing result R with the processing result RA(x) Carrying out a reverse treatment f－1(RA(x) Obtaining an inverse processing result R)B(x) The inverse processing result R is usedB(x) And said DATA DATAINAnd comparing, if the comparison is consistent, the CPU _ A will process the result RA(x) Transfusion systemAnd (6) discharging.
Description
Technical Field
The invention relates to the field of control system design, in particular to an inverse processing fault-tolerant method based on a monitoring pair framework.
Background
In order to ensure the reliability and safety of a highly reliable and highly safe control system, a fault-tolerant design method based on a monitoring pair concept is often adopted. In terms of hardware, the monitoring pair architecture comprises 2 sets of hardware realizing the same function, such as 2 sets of receiving circuits for receiving external signals, 2 Central Processing Units (CPUs) for data calculation/processing, 2 sets of buses and peripherals for result output and the like; in terms of software, the monitoring runs the same software to 2 CPUs in the architecture, and in parallel, i.e.: the other CPU is not visible to the software. Based on the characteristics, the general monitoring framework can only detect hardware faults and cannot detect software faults.
Disclosure of Invention
In order to solve the technical problem, the application provides a reverse processing fault-tolerant method based on a monitoring pair framework, which can detect software and hardware faults simultaneously.
The application provides a fault-tolerant method of inverse processing based on a monitoring pair framework, wherein a monitoring pair framework fault-tolerant computer platform comprises a signal source, a signal processing front end A, a signal processing front end B, a central processing unit CPU _ A and a CPU _ B; the signal source is respectively connected with a signal processing front end A and a signal processing front end B, the signal processing front end A is connected with a CPU _ A, the signal processing front end B is connected with a CPU _ B, and the CPU _ A is connected with the CPU _ B; the method is applied to a monitoring architecture fault-tolerant computer platform and comprises the following steps:
the signal source respectively sends signal source DATA to a signal processing front end A and a signal processing front end B, and the signal source DATA is processed to obtain DATA DATAIN；
The signal processing front end A converts the DATA DATA intoINSending it to CPU _ A, CPU _ A processing said DATA DATA according to a control law algorithmINProcess f (DATA)IN) Obtaining a processing result A: rA(x) And processing the result RA(x) Sending to CPU _ B;
CPU _ B compares the processing result R with the processing result RA(x) Carrying out a reverse treatment f－1(RA(x) Obtaining an inverse processing result R)B(x) The inverse processing result R is usedB(x) And said input DATA DATAINAnd comparing, if the comparison is consistent, the CPU _ A will process the result RA(x) And (6) outputting.
Preferably, the method further comprises: the inverse processing result R is obtainedB(x) And said input DATA DATAINAnd comparing, and if the comparison is inconsistent, performing hardware and software fault processing on the CPU _ A.
Preferably, if the comparison is consistent, the CPU _ a outputs the processing result a, specifically including:
CPU _ A converts the processing result RA(x) Stored in a latch;
CPU _ B enables the output tri-state gate to output the processing result R in the latchA(x) And (6) outputting.
Preferably, if the comparison is inconsistent, detecting a hardware and software failure of the CPU _ a specifically includes:
and the CPU _ B forbids the three-state gate, realizes fault isolation and enters fault processing.
Preferably, the input DATA DATA obtained by the signal processing front-end A is comparedINAnd DATA obtained by the signal processing front end BIN；
If the comparison is consistent, the signal processing front end A will process the DATA DATAINAnd transmits the data to CPU _ A. So as to carry out data processing;
preferably, the method further comprises:
if the contrast is not consistent, CPU _ A and CPU _ B will use the DATA DATAINAnd (5) isolating, and restarting the architecture fault-tolerant computer platform by monitoring.
Preferably, said CPU _ A processes said DATA DATA according to a control law algorithmINProcess f (DATA)IN) Obtaining a processing result RA(x) The method specifically comprises the following steps:
CPU _ A performs fast Fourier transform on the DATA DATAINProcess f (DATA)IN) Obtaining a processing result RA(x)。
Preferably, CPU _ B compares the processing result R with the processing result RA(x) Carrying out a reverse treatment f－1(RA(x) Obtaining an inverse processing result R)B(x) The method specifically comprises the following steps:
CPU _ B performs inverse fast Fourier transform on the processing result RA(x) Carrying out a reverse treatment f－1(RA(x) Obtaining an inverse processing result R)B(x)。
In summary, the inverse processing fault-tolerant method based on the monitoring pair architecture provided by the invention can detect the software fault while realizing the hardware fault detection. Different software is sequentially and singly operated in a single process by 2 CPUs, the CPU _ B performs inverse processing (calculation and the like), and the processing (calculation and the like) of the CPU _ A is verified, so that the detection and isolation of the hardware fault and the software fault of the CPU are realized, and the reliability and the safety of a control system are improved.
Drawings
FIG. 1 is a block diagram of a monitoring-based architecture inverse processing fault tolerance provided by an embodiment of the present invention;
fig. 2 is a flow chart of a system provided by an embodiment of the invention.
Detailed Description
Aiming at the characteristics of a monitoring-to-architecture fault-tolerant computer in a high-reliability and high-safety control system, a reverse processing fault-tolerant method based on a monitoring-to-architecture is provided, the defect that software faults cannot be detected in the general monitoring-to-architecture is overcome, and the fault detection rate of the system is improved.
In a general monitoring pair architecture, 2 CPUs run the same software and run in parallel, that is: for software, the other CPU is invisible, so the structure can only detect hardware faults and cannot detect software faults. The reverse processing fault-tolerant method is improved in that 2 CPUs sequentially run in a single process, 2 CPUs run different software, one CPU performs reverse processing on the result of the other CPU, and then comparison and verification are performed. The hardware fault detection is realized, and simultaneously, the software fault can be detected. Moreover, thanks to the rapid development of the microelectronic technology, the single-core processing capacity of the CPU reaches GHz level, and the strong processing capacity of the CPU ensures that the real-time performance of the control system is not influenced after parallel operation is improved into sequential single-process operation.
Example one
As shown in fig. 1, a reverse processing fault-tolerant method based on monitoring for an architecture, in which 2 CPUs run different software, one CPU performs reverse processing on the result of another CPU, and then compares and verifies the result, and according to the comparison result, the hardware and software faults of the CPU can be detected, and the process is as shown in fig. 2, the fault-tolerant method includes the following steps:
monitoring 2 channels in the architecture fault-tolerant computer to respectively carry out signal front-end processing (modulation, demodulation and the like) on the input signal, and the processing results of the signal front-end processing A and the signal front-end processing B are transmitted into a CPU _ A and a CPU _ B in a cross mode to be compared, so that the fault is detected, and the data input fault detection is realized;
if the comparison of the processing results of the signal front-end processing A and the signal front-end processing B is correct, the processing (calculation and the like) stage is started, and if the comparison is wrong, the tri-state gate is forbidden, the fault isolation is realized, and the fault processing is started;
when the comparison is correct, the comparator enables the output of the tri-state gate, and the CPU _ A receives the input DATA DATAINPerforming processing (calculation, etc.) f (x), e.g. software implementing functions: and outputting a result by performing fast Fourier transform on the input value. The result R of the processing (calculation, etc.)A(x)，RA(x)＝f(DATAIN) The latch is latched by the latch and transmitted to CPU _ B. Output tri-state gates are disabled by default;
CPU _ B to RA(x) Performing an inverse process (solution, etc.) f－1(x) I.e. the software process of CPU _ a is executed in reverse, e.g. the software implements the functions: and the output result is that the input value is divided to carry out inverse fast Fourier transform. The result RB(x)，RB(x)＝f－1(RA(x) And DATA)INComparing, and detecting faults of CPU hardware and software;
if the comparison is correct, the tri-state gate is enabled to output the processing (calculation and the like) result in the latch, and if the comparison is wrong, the tri-state gate is prohibited to realize fault isolation and enter fault processing;
the application architecture and application capabilities of the inverse processing fault tolerant approach to architecture based monitoring are limited.
Preferably, the application architecture and the application capability of the fault-tolerant method for monitoring the architecture are limited, and the fault-tolerant method is applied to a computer platform for monitoring the fault-tolerance of the architecture, and the application capability is as follows: the parallel operation of the 2 CPUs is improved into the sequential single-process operation, and the real-time performance of the tasks is not influenced.
Preferably, the CPU _ B executes an inverse process (solution or the like) f－1(x) The process (calculation, etc.) of CPU _ A is reversed, and the output result of CPU _ A is used to perform the reverse process on CPU _ B to obtain the input data.
Preferably, the monitoring counter-process to the framework is characterized in that after CPU _ a processes (calculates, etc.) the input data, CPU _ B reversely executes the software function of CPU _ a, which is called "counter-process" (solution, etc.).
Example two
The present invention is described in further detail below.
As shown in fig. 1, a typical component of a monitoring-to-architecture fault tolerant computer includes: 2 are used for receiving the receiving circuit of external signal, 2 Central Processing Units (CPU) used for data calculation/processing, 2 are used for the bus and peripheral equipment of result output, etc.. In a general monitoring pair architecture, 2 CPUs run the same software and run in parallel, that is: for software, the other CPU is invisible, so the structure can only detect hardware faults and cannot detect software faults. The adoption of the inverse processing fault-tolerant method based on the monitoring pair framework can realize the detection of the faults of the CPU hardware and software according to the comparison result. The core part of the inverse processing fault-tolerant method based on the monitoring-based architecture is 2 CPUs (central processing units) sequentially execute processing (computing and the like) software and inverse processing (resolving and the like) software, and the specific flow is shown in FIG. 2.
In the comparison, regarding the analog quantity, the analog quantity meeting a certain tolerance range is determined to be equal, and the discrete quantity and the digital quantity are compared in a consistent manner.
In summary, the present invention provides a reverse processing fault-tolerant method based on a monitoring pair architecture, aiming at the defect that a general monitoring pair architecture cannot detect a software fault. The fault-tolerant method provided by the invention improves the mode of monitoring the parallel operation of 2 CPUs in a framework into the mode that the 2 CPUs sequentially operate in a single process, the 2 CPUs operate different software, one CPU performs inverse processing on the result of the other CPU, and then the comparison and verification are performed. The hardware fault detection is realized, and simultaneously, the software fault can be detected. Moreover, thanks to the rapid development of the microelectronic technology, the single-core processing capacity of the CPU reaches GHz level, and the strong processing capacity of the CPU ensures that the real-time performance of the control system is not influenced after parallel operation is improved into sequential single-process operation.
Claims (8)
1. A fault-tolerant method of inverse processing based on monitoring pair framework is characterized in that a monitoring pair framework fault-tolerant computer platform comprises a signal source, a signal processing front end A, a signal processing front end B, a central processing unit CPU _ A and a CPU _ B; the signal source is respectively connected with a signal processing front end A and a signal processing front end B, the signal processing front end A is connected with a CPU _ A, the signal processing front end B is connected with a CPU _ B, and the CPU _ A is connected with the CPU _ B; the method is applied to a monitoring architecture fault-tolerant computer platform and comprises the following steps:
the signal source respectively sends signal source DATA to a signal processing front end A and a signal processing front end B, and the signal source DATA is processed to obtain DATA DATAIN；
The signal processing front end A converts the DATA DATA intoINSending it to CPU _ A, CPU _ A processing said DATA DATA according to a control law algorithmINProcess f (DATA)IN) Obtaining a processing result A: rA(x) And processing the result RA(x) Sending to CPU _ B;
CPU _ B performs inverse processing f on the processing result A－1(RA(x) Obtaining an inverse processing result R)B(x) The inverse processing result R is usedB(x) And said DATA DATAINAnd comparing, if the comparison is consistent, the CPU _ A will process the result RA(x) And (6) outputting.
2. The method of claim 1, further comprising:
the inverse processing result R is obtainedB(x) And said DATA DATAINAnd comparing, and if the comparison is inconsistent, performing hardware and software fault processing on the CPU _ A.
3. The method of claim 1, wherein if the comparison is consistent, the CPU _ a outputs a processing result a, specifically comprising:
CPU _ A converts the processing result RA(x) Stored in a latch;
CPU _ B enables the output tri-state gate to output the processing result R in the latchA(x) And (6) outputting.
4. The method of claim 3, wherein detecting hardware and software failures of the CPU _ A if the comparisons are inconsistent comprises:
and the CPU _ B forbids the three-state gate, realizes fault isolation and enters fault processing.
5. Method according to claim 1, characterized in that the DATA obtained by the signal processing front-end a are comparedINAnd DATA obtained by the signal processing front end BIN；
If the comparison is consistent, the signal processing front end A will process the DATA DATAINAnd transmits the data to CPU _ A. For data processing.
6. The method of claim 5, further comprising:
if the contrast is not consistent, CPU _ A and CPU _ B will use the DATA DATAINAnd (5) isolating, and restarting the architecture fault-tolerant computer platform by monitoring.
7. The method of claim 1, wherein said CPU _ A applies said DATA DATA according to a control law algorithmINProcess f (DATA)IN) Obtaining a processing result A: rA(x) The method specifically comprises the following steps:
CPU _ A performs fast Fourier transform on the signalInput DATA DATAINProcess f (DATA)IN) Obtaining a processing result A: rA(x)。
8. The method of claim 7, wherein CPU _ B performs inverse processing f on the processing result A＿1(RA(x) Obtaining an inverse processing result R)B(x) The method specifically comprises the following steps:
CPU _ B performs inverse fast Fourier transform on the processing result RA(x) Carrying out a reverse treatment f－1(RA(x) Obtaining an inverse processing result R)B(x)。
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| US5243607A (en) * | 1990-06-25 | 1993-09-07 | The Johns Hopkins University | Method and apparatus for fault tolerance |
| CN105550053A (en) * | 2015-12-09 | 2016-05-04 | 中国航空工业集团公司西安航空计算技术研究所 | Redundancy management method for improving availability of monitoring pair based fault tolerant system |
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