CN112305966A

CN112305966A - Digital electronic control device of gas turbine generator set

Info

Publication number: CN112305966A
Application number: CN202011180426.1A
Authority: CN
Inventors: 高昆; 李争超; 陈方; 刘敏; 王山峰; 李明; 袁伟
Original assignee: AECC South Industry Co Ltd
Current assignee: AECC South Industry Co Ltd
Priority date: 2020-10-29
Filing date: 2020-10-29
Publication date: 2021-02-02
Anticipated expiration: 2040-10-29
Also published as: CN112305966B

Abstract

The invention discloses a digital electronic control device of a gas turbine generator set, which is used for controlling the working state of each accessory of the gas turbine generator set by acquiring and processing signals such as a rotor rotating speed signal, an air inlet temperature signal, an exhaust temperature signal, an oil temperature signal, a switching value signal and the like of the gas turbine generator set, thereby realizing digital control, monitoring the running state of the gas turbine generator set in real time and improving the safety and reliability of the gas turbine generator set. And the program memory and the data memory circuit are arranged to store the main program and the temporarily loaded operation data when the single chip microcomputer operates, so that the data storage space is increased, a large amount of collected data can be processed and stored in time, the receiving and sending of the data of the single chip microcomputer and the read-write control of the two program memories are realized through the bus transceiving and memory control circuit, and the free and quick switching between the two program memories can be realized.

Description

Digital electronic control device of gas turbine generator set

Technical Field

The invention relates to the technical field of control of gas turbine generator sets, in particular to a digital electronic control device of a gas turbine generator set.

Background

The gas turbine generator set mainly comprises a centrifugal compressor, a combustion chamber, a turbine, a speed reducer, a generator set, electronic accessories, cables and the like. The main working principle is that compressed air and fuel oil are mixed and combusted to drive a gas turbine to rotate and then drive a generator set to operate, so that 400Hz and 220V alternating currents are output and supplied to various electric equipment. In order to ensure the normal operation of the gas turbine generator set, the gas turbine generator set must be accurately and stably controlled, meanwhile, in order to ensure the safety of the gas turbine generator set and accessories thereof, the working state of the gas turbine generator set must be monitored, and once a fault occurs, the fault can be isolated. The control device of the existing gas turbine generator set cannot meet the requirements of control precision and working state monitoring. In addition, the processing circuit of the current gas turbine generator set control device generally realizes control and data storage management through a single chip microcomputer circuit, and the data storage space and the program storage space of the single chip microcomputer circuit are limited, so that a large amount of data cannot be processed and stored in time, and the requirement of monitoring the omnibearing working state cannot be met.

Disclosure of Invention

The invention provides a digital electronic control device of a gas turbine generator set, which aims to solve the technical problems that the existing control device of the gas turbine generator set cannot meet the control precision requirement and the working state monitoring requirement, and the storage space of a processing circuit is limited so that a large amount of data cannot be processed and stored.

According to one aspect of the invention, a digital electronic control device of a gas turbine generator set is provided, which comprises a conversion board assembly, a main board assembly, a bus transceiving board assembly, an output interface board assembly and a power board assembly, wherein the conversion board assembly is used for collecting signals of a lubricating oil temperature sensor, an intake air temperature sensor, an exhaust temperature thermocouple and a rotating speed sensor, converting the signals and transmitting the signals to the main board assembly for processing, and is also used for converting digital quantity signals output by the main board assembly into analog quantity signals to control the current flowing through a fuel regulator, the main board assembly is used for operating and processing input signals and outputting corresponding control signals, the bus transceiving board assembly is used for converting six groups of externally input switching quantity signals into digital quantity signals and transmitting one group of the digital quantity signals to the main board assembly for processing, the output interface board assembly is used for converting the 8-bit digital quantity signal output by the mainboard assembly into a switching value signal to be output so as to control each accessory of the gas turbine generator set, and the power board assembly is used for converting an external power voltage into a working voltage required by each assembly;

the mainboard assembly comprises a singlechip, a clock circuit, a power-on reset and watchdog circuit, a program memory, a data memory circuit, a bus transceiving and memory control circuit and an expansion bus circuit, wherein the power-on reset and watchdog circuit and the bus transceiving and memory control circuit are all connected with the singlechip and the clock circuit, the bus transceiving and memory control circuit is also respectively connected with the expansion bus circuit, the program memory and the data memory circuit, the power-on reset and watchdog circuit is used for monitoring the operation condition of the singlechip, the singlechip is reset once the singlechip has an error in operation, the program memory and the data memory circuit are used for storing a main program and temporarily loaded operation data when the singlechip operates, the bus transceiving and memory control circuit is used for receiving and sending the data of the singlechip and performing read-write control on two program memories, the expansion bus circuit is used for data exchange between the mainboard component and the outside.

Further, the power-on reset and watchdog circuit comprises a capacitor C, a resistor R, a phase inverter D, an OR gate D, a trigger D, a NAND gate D, a phase inverter D, a OR gate D, a counter D, and a counter D, wherein the positive terminal of the capacitor C is connected with the power panel assembly, the negative terminal of the capacitor C is respectively connected with the first terminal of the resistor R, the input terminal of the phase inverter D, and the set terminal of the trigger D, the second terminal of the resistor R is grounded, the output terminal of the phase inverter D is connected with the input terminal of the phase inverter D, the output terminal of the phase inverter D is respectively connected with the input, the output end of the inverter D17 is connected with the set end of the flip-flop D19 and the other input end of the or gate D18, the output end of the or gate D18 is connected with the second end of the resistor R37, the R end of the counter D28, the R end of the counter D29 and the R end of the counter D30, the reset end of the flip-flop D20 is connected with the Q end of the counter D29, the E end of the counter D29 is connected with the Q end of the counter D28, the E end of the counter D30 is connected with the Q end of the counter D29, the inverting output end of the flip-flop D20 is connected with the input end of the nand gate D21 and the input end of the nand gate D22, the other input end of the counter D30 is connected with the Q end of the counter D30, the output end of the nand gate D21 is connected with the other input end of the nand gate D22, the output end of the nand gate D22 is connected with the reset signal input end of the nand gate D38, the first end of the single chip, The input end of an inverter D26 is connected, the first end of a resistor R39 is connected with a power panel assembly, the second end of a resistor R39 is connected with the output end of a NAND gate D22, the first end of a resistor R40 is connected with the power panel assembly, the second end of a resistor R40 is connected with the input end of an inverter D23 and the output end of an inverter D25 respectively, the output end of an inverter D23 is connected with the first end of a resistor R41, the second end of a resistor R41 is connected with the input end of an inverter D24 and the first end of a capacitor C40 respectively, the output end of an inverter D24 is connected with the first end of a resistor R42, the second end of a resistor R42 is connected with the second end of a capacitor C40 and the input end of an inverter D25 respectively, the output end of an inverter D25 and the output end of an inverter D26 are connected with the two input ends of an OR gate D27 respectively, or the; when the power is on, a high-level pulse is generated on the resistor R36, the inverter D16 outputs a high level, the OR gate D18 outputs a high level, the counters D28, D29 and D30 are all reset, the flip-flop D20 is set, the inverted output end of the flip-flop D20 outputs a low level, the NAND gate D22 outputs a high level to the reset signal input end of the single chip microcomputer, the single chip microcomputer is reset, when the power is on and the reset pulse is reduced, the inverter D23, the resistor R41, the inverter D24, the capacitor C40, the resistor R42 and the inverter D25 form a ring oscillator with RC delay, a clock signal generated by the ring oscillator is input to the clock input end of the counter D28, the watchdog is formed by the counter D28, the counter D29 and the counter D30, a P1.0 port of the watchdog is used for outputting a feeding instruction, and the low-level pulse realizes zero clearing of the timer through the inverter D17 and the counter D18.

Further, the capacitance value of the capacitor C39 is 6.8 μ F, the resistance value of the resistor R36 is 8.2k Ω, the resistance values of the resistors R37, R38, R39 and R40 are 1.2k Ω, the resistance values of the resistors R41 and R42 are 620 Ω, the models of the inverters D15, D16, D17 and D26 are 564 n/p 2v, the models of the inverters D23, D24 and D25 are 1533 n/n 2, the models of the gates D18 and D27 are 1533 n/n 2, the models of the flip-flops D19 and D20 are 564TM2B, the models of the nand gates D21 and D22 are 533 n/a 13, and the models of the counters D28, D29 and D30 are 564 v10 v.

Furthermore, the program memory and data memory circuit comprises a program memory D31, a program memory D32 and a data memory D33, wherein the program memories D31 and D32 are OTPROMs of 8K 8, the two program memories D31 and D32 share an address bus and a data bus, but independent chip selection control lines are provided, a chip selection signal is effective in low level, the data memory D33 is a RAM with the capacity of 2K 8, an address line is 11 bits, and the chip selection control signal lines, the output enable control lines and the read-write control signal lines are provided.

Further, the bus transceiver and memory control circuit comprises a two-wire bus transceiver D34, a latch D35, a latch D36, A3-wire-8-wire decoder D37, a resistor R37, a resistor bank R37, an and gate D37, a not gate D37, an or gate D37, an and gate D37, a resistor R37, wherein the two-wire bus transceiver D37 is respectively connected with a single chip microcomputer and the latch D37, the latch D37 is connected with the single chip microcomputer, the 8-bit address bus a 37-a 37 is output from the single chip microcomputer to the two-way bus transceiver D37, then output from the two-way bus D37 to the latch D37 and latched at an output end of the latch D37, the 5-bit address bus a 37-a 37 is output to the latch D37 by the two-wire bus transceiver D37, the two-way bus D37 is output of the two-way bus, the two-way bus transceiver D37 is first output port of the two-wire bus transceiver D37, then the signal is sent to an A port of a dual-wire bus transceiver D34 and finally sent to a single chip microcomputer, an input end of a 3-wire-8-wire decoder D37 is connected with the single chip microcomputer, an output end of the 3-wire-8-wire decoder D37 is respectively connected with an input end of an OR gate D46, an input end of an OR gate D42, an input end of an NOT gate D41, an input end of an OR gate D43 and an input end of an OR gate D47, a first end of a resistor in a resistor bank R44 is connected with a power panel assembly, a second end of the resistor bank R44 is respectively connected with a Y0 end, a Y1 end and a Y2 end of a 3-wire-8-wire decoder D37, a first end of a resistor R43 is connected with the power panel assembly, a second end of the resistor R43 is respectively connected with a G1 end of the 3-wire-8-wire decoder D37 and an input end of a latch D36, a Q5 end of a latch D36 is connected with an input end of an AND gate D84, the Q7 of the latch D36 is connected to the other input of the OR gate D42 and the other input of the OR gate D46, the output of the AND gate D39 is connected to the input of the AND gate D44, the output of the NOT gate D40 is connected to the other input of the AND gate D44, the output of the NOT gate D41 is connected to the input of the AND gate D45, the outputs of the OR gate D42 and the OR gate D43 are floating, the first end of the resistor R45 and the first end of the resistor R46 are connected to the power board assembly for +5V supply voltage, the second end of the resistor R11 is connected to the outputs of the AND gate D39 and the AND gate D45, the second end of the NAND gate R46 is connected to the output of the D40, the output of the AND gate D44 is connected to the program memory D31, the output of the AND gate D45 is connected to the program memory D32, the outputs of the OR gate D46 and the gate D47 are connected to the address bus D33, the A-015-013, The six signals WR, RD, and PSEN are operated by the 3-line-8-line decoder D37, the latch D36, and the logic gate circuit, and the operation result controls a chip select signal of the memory device, thereby selecting which memory device is to be read or written.

Furthermore, the model of the two-wire bus transceiver D34 is 533 a l 6, the model of the latches D35 and D36 is 1533R 33, the model of the 3-wire-8-wire decoder D37 is 533D 7, the resistances of the resistors R43, R45 and R46 are 1.2k Ω, the total resistance of the resistor row R44 is 5.1k Ω, the models of the and gates D39 and D44 are 533 l 13, the model of the not gate D40 is 1533 l2, the model of the not gate D41 is 533t 2, the model of the and gate D45 is 1533 l1, or the models of the gates D42, D43, D46 and D47 are 533 l 1.

Further, the expansion bus circuit comprises a latch D48, a latch D49, a latch D50, a latch D51, a latch D52, a latch D53 and a latch D54, which are sequentially connected to the bus, wherein the latch D48, the latch D49, the latch D50 and the latch D51 are used for data output, and the latch D52, the latch D53 and the latch D54 are used for data input.

Further, the single chip microcomputer and the clock circuit comprise a single chip microcomputer chip D, a capacitor C, a crystal oscillator G and a crystal oscillator G, wherein the first end of the capacitor C and the first end of the capacitor C are grounded, the second end of the capacitor C is connected with the BQ end of the single chip microcomputer chip D, the second end of the capacitor C is connected with the BQ end of the single chip microcomputer D, the two ends of the crystal oscillator G are respectively connected with the BQ end and the BQ end of the single chip microcomputer chip D, the first end of the capacitor C and the first end of the capacitor C are grounded, the second end of the capacitor C is connected with the XTAL end of the single chip microcomputer chip D, the two ends of the crystal oscillator G are respectively connected with the XTAL end and the XTAL end of the single chip D, the single chip microcomputer chip D is used as a backup of the single chip D, and, as a working reference clock of an internal circuit of the singlechip, the capacitors C35, C36, C37 and C38 are used as matching capacitors of the crystal oscillator and are used for starting oscillation of the crystal oscillator.

Further, the bus transceiver panel assembly includes six first optical coupling conversion circuits, six bus transceiver circuits and a passageway selection circuit, and every first optical coupling conversion circuit all connects a bus transceiver circuit, and six first optical coupling conversion circuits are used for converting 6 groups of on-off quantity signals of input into digital quantity signal through the opto-coupler, the passageway selection circuit is connected with six bus transceiver circuits respectively, and six bus transceiver circuits all are connected with the mainboard subassembly, the passageway selection circuit is used for gating any one of six bus transceiver circuits, makes a set of digital quantity signal output that corresponds to the mainboard subassembly.

Further, the first optical coupling conversion circuit comprises 8 identical first optical coupling conversion unit circuits, the first optical coupling conversion unit circuit comprises a voltage stabilizing diode V11, a resistor R47, a capacitor C40, an optical coupler B1, a resistor R48 and a resistor R49, the negative end of the voltage-stabilizing diode V11 is connected with a bus to access switching value signals, the positive end of the voltage-stabilizing diode V11 is connected with the first end of a resistor R47, the second end of the resistor R47 is respectively connected with the positive end of a capacitor C40 and a No. 4 pin of an optocoupler B1, the second end of the capacitor C40 and a No. 2 pin of the optocoupler B1 are grounded, the first end of the resistor R49 is connected with a power supply, the second end of the resistor R49 is connected with a No. 1 pin of the optocoupler B1, the first end of the resistor R48 is connected with a No. 3 pin of the optocoupler B1, a No. 5 pin of the optocoupler B1 and the second end of the resistor R48 are grounded, and the No. 1 pin of the optocoupler B1 is; when a 27V switching value signal is input into the circuit, the light emitting diode between the No. 4 pin and the No. 2 pin of the optical coupler B1 is switched on, the output end of the light emitting diode is switched on, the circuit outputs 0V, when the circuit has no switching value signal input, the light emitting diode at the input end of the optical coupler B1 is switched off, the output end of the optical coupler B1 is switched off, and the circuit output voltage is the power supply voltage.

The invention has the following effects:

the digital electronic control device of the gas turbine generator set realizes digital electronic automatic control, provides accurate and stable control, can monitor the running state of the gas turbine generator set in real time, improves the safety and reliability of the gas turbine generator set, and provides a solution for realizing multivariable, multitask and complex state control by acquiring signals such as a rotor rotating speed signal, an air inlet temperature signal, an exhaust temperature signal, an oil temperature signal, a switching value signal and the like of the gas turbine generator set to process and further outputting a control signal to control the working state of each accessory of the gas turbine generator set. And the program memory and the data memory circuit are arranged to store the main program and the temporarily loaded operation data when the single chip microcomputer operates, so that the data storage space is increased, a large amount of data collected in the operation process of the gas turbine generator set can be processed and stored in time, the bus transceiving and memory control circuit is used for receiving and sending the data of the single chip microcomputer and performing read-write control on the two program memories, and free and quick switching between the two program memories can be realized.

In addition to the objects, features and advantages described above, other objects, features and advantages of the present invention are also provided. The present invention will be described in further detail below with reference to the drawings.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this application, illustrate embodiments of the invention and, together with the description, serve to explain the invention and not to limit the invention. In the drawings:

fig. 1 is a schematic block diagram of a digital electronic control device of a gas turbine generator set according to a preferred embodiment of the present invention.

Fig. 2 is a schematic block diagram of the conversion board assembly of fig. 1.

Fig. 3 is a schematic circuit diagram of the current source circuit in fig. 2.

Fig. 4 is a schematic circuit diagram of a part of the analog processing circuit in fig. 2.

Fig. 5 is another circuit schematic diagram of the analog processing circuit in fig. 2.

Fig. 6 is a circuit structure diagram of the a/D conversion and control circuit in fig. 2.

Fig. 7 is a schematic circuit diagram of the rotational speed signal conditioning circuit in fig. 2.

Fig. 8 is a schematic circuit diagram of the D/a conversion and actuator control circuit in fig. 2.

Fig. 9 is a schematic block diagram of the motherboard assembly 12 in fig. 1.

Fig. 10 is a schematic circuit diagram of the single chip microcomputer and the clock circuit in fig. 9.

Fig. 11 is a circuit configuration diagram of the power-on reset and watchdog circuit of fig. 9.

Fig. 12 is a circuit configuration schematic diagram of the program memory and data memory circuits of fig. 9.

Fig. 13 is a schematic circuit diagram of a part of the bus transceiver and memory control circuit in fig. 9.

Fig. 14 is another circuit diagram of the bus transceiver and memory control circuit in fig. 9.

Fig. 15 is a schematic circuit configuration diagram of the expansion bus circuit in fig. 9.

Fig. 16 is a block diagram of the bus transceiver board assembly of fig. 1.

Fig. 17 is a schematic circuit configuration diagram of a first optical coupler conversion unit circuit included in the first optical coupler conversion circuit in fig. 16.

Fig. 18 is a circuit configuration diagram of the bus transceiver circuit in fig. 16.

Fig. 19 is a circuit configuration diagram of the channel selection circuit in fig. 16.

Fig. 20 is a block diagram of the output interface board assembly of fig. 1.

Fig. 21 is a circuit configuration diagram of the latch circuit in fig. 20.

Fig. 22 is a schematic circuit structure diagram of a second optical coupler conversion unit circuit included in the second optical coupler conversion circuit in fig. 20.

Description of the reference numerals

11. A conversion board assembly; 12. a motherboard assembly; 13. a bus transceiver board assembly; 14. an output interface board assembly; 15. a power board assembly; 16. a filter board assembly; 111. a power conversion circuit; 112. a current source circuit; 113. an analog quantity processing circuit; 114. an A/D conversion and control circuit; 115. a rotation speed signal conditioning circuit; 116. D/A conversion and actuating mechanism control circuit; 121. a singlechip and a clock circuit; 122. a power-on reset and watchdog circuit; 123. program memory and data memory circuitry; 124. a bus transceiver and memory control circuit; 125. an expansion bus circuit; 131. a first optocoupler conversion circuit; 132. a bus transceiver circuit; 133. a channel selection circuit; 141. a latch circuit; 142. and the second optical coupling conversion circuit.

Detailed Description

The embodiments of the invention will be described in detail below with reference to the accompanying drawings, but the invention can be embodied in many different forms, which are defined and covered by the following description.

As shown in fig. 1, a preferred embodiment of the present invention provides a digital electronic control device for a gas turbine generator set, which includes a conversion board assembly 11, a motherboard assembly 12, a bus transceiver board assembly 13, an output interface board assembly 14, a power board assembly 15, and a filter board assembly 16, where the conversion board assembly 11 is configured to collect and convert signals of an oil temperature sensor, an intake air temperature sensor, an exhaust air temperature thermocouple, and a rotation speed sensor, and then transmit the signals to the motherboard assembly 12 for processing, and is further configured to convert a digital quantity signal output by the motherboard assembly 12 into an analog quantity signal to control a current flowing through a fuel regulator, so as to control a rotation speed of the gas turbine generator set. The main board assembly 12 is configured to perform operation and processing on an input signal and output a corresponding control signal, the bus transceiver board assembly 13 is configured to convert six input switching value signals into digital quantity signals and transmit any one of the digital quantity signals to the main board assembly 12 for processing, the output interface board assembly 14 is configured to convert an 8-bit digital quantity signal output by the main board assembly 12 into a switching value signal for output, so as to control each accessory of the gas turbine generator set, for example, output a switching value signal to control a working state of each accessory, and output a state signal indication and a 5-bit SPI code to a display control combination to control a display content. The power panel assembly 15 is used for converting a power voltage provided by an external power supply into +5V, +25V, +15V and-15V for output so as to supply power to each assembly, and the filter panel assembly 16 is used for filtering the external power voltage.

The digital electronic control device of the gas turbine generator set can be understood to collect and process signals such as a rotor rotating speed signal, an air inlet temperature signal, an exhaust temperature signal, an oil temperature signal, a switching value signal and the like of the gas turbine generator set, further output a control signal to control the working state of each accessory of the gas turbine generator set, realize digital electronic automatic control, provide accurate and stable control, monitor the running state of the gas turbine generator set in real time, improve the safety and reliability of the gas turbine generator set, and provide a solution for realizing the control of multivariable, multitask and complex states.

It can be understood that the digital electronic control device adopts a frame stacking structure, the conversion board assembly 11, the main board assembly 12, the bus transceiver board assembly 13 and the output interface board assembly 14 are tightly installed in a peripheral frame through guide grooves, bolts and standard parts, namely, a plurality of guide grooves are arranged in the frame, then each board assembly is inserted into the guide grooves and then fixed through screws, pins and the like, the upper and lower positions among the board assemblies can be adjusted according to requirements, and the power board assembly 15 and the filter board assembly 16 are installed on the bottom surface of the peripheral frame.

As shown in fig. 2, the converter board assembly 11 specifically includes a power converter circuit 111, a current source circuit 112, an analog processing circuit 113, an a/D converter and control circuit 114, a speed signal conditioning circuit 115, and a D/a converter and actuator control circuit 116, the power converter circuit 111 is configured to convert the + 15V-15V voltage output by the power board assembly 15 into + 5V-5V voltage for use by other circuits of the converter board assembly 11, the current source circuit 112 is configured to supply power to the lubricant temperature sensor and the intake temperature sensor, the analog processing circuit 113 is configured to collect and filter and amplify voltage signals of the lubricant temperature sensor, the intake temperature sensor, and the exhaust temperature thermocouple for use by the subsequent a/D converter and control circuit 114, and the a/D converter and control circuit 114 is configured to convert the analog signal output by the analog processing circuit 113 into a 12-bit analog signal The rotation speed signal conditioning circuit 115 is used for acquiring a sinusoidal signal of the rotation speed sensor and converting the sinusoidal signal into a square wave signal so as to facilitate the counting of the subsequent singlechip circuit. The D/a conversion and actuator control circuit 116 is used to convert the digital signals output from the main board assembly 12 into analog signals for controlling the current flowing through the electro-hydraulic servo valve of the fuel regulator, thereby controlling the rotational speed of the gas turbine generator set. It is understood that the power conversion circuit 111 may be omitted and the electronic components of the conversion board assembly 11 obtain the operating voltage directly from the power board assembly 15.

Specifically, as shown in fig. 3, the current source circuit 112 includes a positive voltage regulator N1, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6, a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4, a potentiometer RP1, an operational amplifier N2, an 8-to-1 analog switch D1, and a fet V1, a first end of the resistor R1 is connected to the motherboard assembly 12, a second end of the resistor R1 is connected to the pin No. 1 of the positive voltage regulator N1, a first end of the resistor R2, and a first end of the capacitor C2, a power supply terminal of the positive voltage regulator N2 is connected to the power supply board assembly 15 for supplying +15V operating voltage, two ends of the capacitor C2 are connected to the pin No. 6 and pin No. 7 of the positive voltage regulator N2, a second end of the resistor R2 is connected to the first end of the potentiometer RP 72, and a second end of the potentiometer RP 72 (i.e., a sliding, A positive phase input end of an operational amplifier N2, a pin No. 3 of a field effect transistor V1 and a first end of a capacitor C4 are connected, a second end of the resistor R3 is respectively connected with a first end of a resistor R4 and an inverting input end of an operational amplifier N2, a second end of the capacitor C1 and a second end of the resistor R4 are both grounded, a first end of the capacitor C2 is grounded, a second end of the capacitor C2 is connected with a pin No. 4 of the operational amplifier N2, two ends of a capacitor C3 are respectively connected with a pin No. 1 and a pin No. 8 of the operational amplifier N2, an output end of an operational deflation amplifier N2 is connected with a pin No. 4 of the field effect transistor V1, a pin No. 1 of the field effect transistor V1 is suspended, a pin No. 2 of the field effect transistor V1 is respectively connected with a second end of the capacitor C4, a positive end of a diode V2 and an 8-selected-1 analog switch D1, and the 8-selected analog switch D1, The main board component 12 is connected, wherein, the oil temperature sensor is connected with No. 3 channel of the 1 st analog switch D1 of 8 selection, and the temperature sensor that admits air is connected with No. 5 channel of the 1 st analog switch D1 of 8 selection, diode V2, diode V3, diode V4 are in proper order with the syntropy to be established ties, and diode V4's negative pole end ground connection, the first end of resistance R5, the first end of resistance R6 all with the No. 8 channel connection of the 1 st analog switch D1 of 8 selection, the second end of resistance R5 and the second end of resistance R6 all ground connection. The model of the positive voltage regulator N1 is preferably AD584TH, the resistance of the resistor R1 is 2k Ω, the resistance of the resistor R2 is 1.09k Ω, the resistance of the resistor R3 is 9.09k Ω, the resistance of the resistor R4 is 14.3k Ω, the resistances of the resistor R5 and the resistor R6 are 202 Ω, the capacitance of the capacitor C1 is 0.4 μ F, the capacitance of the capacitor C2 is 68nF, the capacitances of the capacitor C3 and the capacitor C4 are 510pF, the capacitance of the capacitor C5 is 33pF, the total resistance of the potentiometer RP1 is 15 Ω, and the models of the diode V2, the diode V3 and the diode V4 are 1N 4148. The No. 1 pin of the positive voltage regulator N1 outputs +10V direct-current voltage, the voltage is divided by a resistor R3 and a resistor R4 and then serves as reference voltage of an operational amplifier N2, the operational amplifier N2 outputs negative voltage to control a field-effect tube V1 to be conducted, meanwhile, the +10V voltage generates current output through a resistor R2 and a potentiometer RP1, when a mainboard assembly 12 outputs a control signal to control a No. 3 channel in an 8-in-1 analog switch D1 to be closed, the field-effect tube V1 outputs current to supply power to a lubricating oil temperature sensor, and when a No. 5 channel in the 8-in-1 analog switch D1 is controlled to be closed, the field-effect tube V1 outputs current to supply power to an air inlet temperature sensor. Diode V2, diode V3 and diode V4 are used to limit the output voltage and avoid damaging the sensor, while potentiometer RP1 functions to regulate the amount of current supplied to the sensor.

It can be understood that the current source circuit 112 of the present embodiment outputs a +10V regulated voltage by the positive voltage regulator N1, the regulated voltage is divided by the resistors R3 and R4 and then used as a reference voltage of the operational amplifier N2, and a current output is generated by the resistors R2 and the potentiometer RP1, one positive voltage regulator N1 functions as both a reference voltage source and a current source, when the operational amplifier N2 outputs a negative voltage to control the conduction of the fet V1, the fet V1 outputs the current generated by the resistors R2 and the potentiometer RP1 to the oil temperature sensor or the intake air temperature sensor, the potentiometer RP1 can also be used to adjust the magnitude of the supply current, the output terminal voltage is limited by three diodes to protect the sensors, and the motherboard component 12 can also be used to select the power supply target, the circuit structure of the whole circuit is simple, the function integrated level is high to what adopt all is comparatively common electronic components on the market, and the circuit cost is low.

It is to be understood that, as shown in fig. 4 and fig. 5, the analog processing circuit 113 includes a resistor R7, a resistor R8, a resistor R9, a resistor R10, a resistor R11, a resistor R12, a resistor R13, a resistor R14, a resistor R15, a resistor R16, a resistor R17, a resistor R18, a resistor R19, a capacitor C6, a capacitor C7, a capacitor C8, a capacitor C9, a dual 8-way analog switch D2, an operational amplifier N3, an operational amplifier N4, a resistor R4, a capacitor C4, an operational amplifier N4, a resistor bank R4, a dual 8-way analog switch D4, a capacitor C4, a potentiometer RP4, an operational amplifier N4, a resistor R4, a first end of the operational amplifier N4, a first end of the resistor R3772, a positive electrode of the resistor R4, a positive electrode of the first end of the first resistor R4, a positive electrode of the first electrode, a first electrode of the first electrode, the first, the second end of the resistor R8 is connected with the double 8-way analog switch D2, the first end of the resistor R9 is connected with the positive terminal of the exhaust temperature thermocouple to acquire a voltage signal of the exhaust temperature thermocouple, the second end of the resistor R9 is connected with the first end of the resistor R10 and the positive terminal of the capacitor C6 respectively, the second end of the resistor R10 is connected with the first end of the resistor R11 and the positive terminal of the capacitor C92 respectively, the second end of the resistor R11 is connected with the double 8-way analog switch D2, the first end of the resistor R12, the first end of the resistor R13 and the first end of the resistor R6329 are connected with the power supply terminal of the sensor to acquire a power supply current of the sensor, the second end of the resistor R12 and the second end of the resistor R13 are both grounded, the second end of the resistor R14 is connected with the double 8-way analog switch D2, the first end of the resistor R15 is connected with the negative terminal of the exhaust temperature thermocouple to acquire a voltage signal, the second end of the resistor R5 is connected with the positive terminal of the positive terminal R, a second end of the resistor R16 is connected with a positive terminal of the capacitor C9 and a first end of the resistor R17 respectively, a second end of the resistor R17 is connected with the dual 8-way analog switch D2, a negative terminal of the capacitor C6 is connected with a negative terminal of the capacitor C7, a negative terminal of the capacitor C8 is connected with a negative terminal of the capacitor C9, an input terminal of the inverter D3 is connected with the motherboard assembly 12, an output terminal of the inverter D3 is connected with the dual 8-way analog switch D2, a first end of the resistor R18 is connected with a negative terminal of the intake air temperature sensor, a second end of the resistor R18 is connected with the dual 8-way analog switch D2, a first end of the resistor R19 is connected with a negative terminal of the lubricating oil temperature sensor, a second end of the resistor R19 is connected with the dual 8-way analog switch D2, the dual 8-way analog switch D2 is further connected with the motherboard assembly 12, one output terminal of the dual 8-way analog switch D2 is connected with an input terminal of the voltage follower N3, and a positive-, the other output end is connected with a positive input end of a voltage follower N4, an inverting input end of a voltage follower N4 is connected with the output end of the voltage follower N4, a first end of a resistor R20 is connected with an output end of the voltage follower N4, a second end of a resistor R20 is respectively connected with a first end of a resistor R22 and an inverting input end of an operational amplifier N5, a second end of a resistor R22 is connected with an output end of an operational amplifier N5, a first end of a resistor R21 is connected with an output end of the voltage follower N3, a second end of a resistor R21 is respectively connected with a first end of a resistor R23 and a positive input end of an operational amplifier N5, a second end of a resistor R23 is grounded, a first end of a capacitor C10 is grounded, a second end of a capacitor C10 is connected with a No. 4 pin of an operational amplifier N5, a first end of a capacitor C11 is connected with a No. 7 pin of an operational amplifier N5, a second end of a capacitor C11 is grounded, a, the double 8-way analog switch D2 is respectively connected with the resistor bank R24, the second end of the capacitor C12, the second end of the capacitor C13, the inverting input end of the operational amplifier N6, the output end of the operational amplifier N6 and the output end of the operational amplifier N7, the double 8-way analog switch D2 is further connected with the motherboard component 12, the corresponding channels are controlled to be closed according to the control signals output by the motherboard component 12, the first end of the capacitor C12 and the first end of the capacitor C13 are both grounded, the two ends of the capacitor C14 are respectively connected with the inverting input end and the output end of the operational amplifier N6, the two ends of the capacitor C15 are respectively connected with the inverting input end and the output end of the operational amplifier N7, the first end of the potentiometer RP2 is connected with the pin No. 1 of the operational amplifier N6, the second end of the potentiometer RP2 is connected with the pin No. 8 of the operational amplifier N6, the third end of the potentiometer RP2 is connected with the power board, the output terminal of the operational amplifier N6 is connected to the non-inverting input terminal of the operational amplifier N7, and the output terminal of the operational amplifier N6 is connected to the a/D conversion and control circuit 114. The resistance values of the resistor R7, the resistor R7 and the resistor R7 are 2k omega, the resistance values of the resistor R7, the resistor R7 and the resistor R7 are 3k omega, the resistance values of the resistor R7 and the resistor R7 are 102 omega, the resistance values of the resistor R7, the resistor R7 and the resistor R7 are 4.99k omega, the total resistance value of the potentiometer RP 7 is 15k omega, the model number of the resistor row R7 is 313HP 17, the capacitance values of the capacitor C7, the capacitor C7 and the capacitor C7 are 33 muF, the capacitance values of the capacitor C7, the capacitor C7 and the capacitor C7 are 68nF, the capacitance values of the capacitors C7 and the capacitance values of the analog switch 36591 of the double-way analog switch 7 and the analog switch 36591.

It can be understood that, in the analog processing circuit 113, the voltage signals of the oil temperature sensor, the intake temperature sensor, and the exhaust temperature thermocouple are directly collected and input to the double 8-way analog switch D2, and the sensor power supply current detection signal is converted into a voltage signal through the resistor R12 and the resistor R13 and input to the double 8-way analog switch D2, when the control signal output by the motherboard assembly 12 controls the corresponding channel in the double 8-way analog switch D2 to be closed, the voltage signal collected by the channel can be output to the positive phase input terminals of the voltage follower N3 and the voltage follower N4, and the voltage U output by the voltage follower N3 is output₀₁Voltage value of (d) is the same as that of its input terminal, voltage U output by voltage follower N4₀₂Is also the same as its input terminal. Voltage signal U output by voltage follower N3 and voltage follower N4₀₁And U₀₂Output U after differential amplification by an operational amplifier N5₀₃To the non-inverting input terminal of the operational amplifier N6, and since the resistances of the resistor R20, the resistor R21, the resistor R22 and the resistor R23 are equal, U is equal₀₃＝U₀₁-U₀₂. U output of operational amplifier N5₀₃Then input the voltage signal to the non-inverting input terminal of the operational amplifier N6 and the voltage signal output by the operational amplifier N6U₀₄Then, the signal is inputted to the non-inverting input terminal of the operational amplifier N7, and the motherboard component 12 outputs a control signal to control one of the channels of the dual 8-way analog switch D3 to be closed, so as to control the resistance value of the resistor introduced into the resistor bank R24, and further control the output voltage values of the operational amplifier N6 and the operational amplifier N7, i.e., control the amplification ratio of the analog processing circuit 113. For example, when the motherboard assembly 12 controls channel 1 of the dual 8-way analog switch D3 to be closed, the operational amplifiers N6 and N7 are both voltage followers, and the output voltage U of the operational amplifier N7₀₅＝U₀₄＝U₀₃(ii) a When the main board assembly 12 controls the channel 2 of the dual 8-way analog switch D3 to be closed, the output voltage of the operational amplifier N6 is:

actually measured U₀₄＝2U₀₃Thus, 2 π fc can be determined₃₈·R24 _5-241, and the operational amplifier N7 is still a voltage follower, the output voltage U of which₀₅＝U₀₄＝2U₀₃. When the motherboard assembly 12 controls the other channels of the dual 8-way analog switch D3 to be closed, the output voltages of the operational amplifiers N6 and N7 are:

wherein, X-X is the pin number at two ends of the corresponding resistor in the resistor bank R24.

It can be understood that in the analog processing circuit 113 of the present embodiment, R7, R8, R14, R18, and R19 are current limiting resistors, so that damage to subsequent circuits due to excessive input signal current can be avoided. Signals input by the exhaust temperature A8 and the exhaust temperature C8 are weak and are easily influenced by interference signals, and the R9, the R15, the R10, the R16, the R11, the R17, the C6, the C7, the C8 and the C9 form a common mode filter circuit for filtering interference in the exhaust temperature signals. D2 is an analog switch of 1 from 8, the master control board inputs control signals from A39, and controls the on and off of 8 channels in D2 after the control signals are inverted by an inverter D3. When the channel is conducted, the externally input lubricating oil temperature voltage, the externally input intake air temperature voltage and the externally input exhaust air temperature are output to the output end of the D2, and the operational amplifiers N3 and N4 are used as followers and used for buffering and isolation. In addition, the resistors R20, R21, R22, R23 and the operational amplifier N5 form a differential amplification circuit, and the differential amplification circuit has the functions of stabilizing a static working point, amplifying differential mode signals and suppressing common mode signals. D3 is an 8-from-1 analog switch, which is connected with the resistor bank R23, and the main control board inputs control signals from A40\ A41\ A42 to control the on and off of 8 channels in D3. When the channel is conducted, the operational amplifiers N6 and N7 are connected with the resistors in the R24, so that the amplification factor of the circuits of N6 and N7 is changed, the operational amplifiers N6 and N7 are used as negative feedback amplification circuits, and the RP2 is a zero-setting potentiometer and is used for adjusting the zero position of the N6.

As shown in fig. 6, the a/D conversion and control circuit 114 specifically includes a capacitor C16, a capacitor C17, a capacitor C18, a capacitor C19, a capacitor C20, a capacitor C21, a capacitor C22, a capacitor C23, a capacitor C24, a capacitor C25, a capacitor C26, a resistor R25, a resistor R26, a resistor R27, an inverter D4, a flip-flop D5, an inverter D6, a flip-flop D7, a 12-bit a/D converter D8, and a diode V5, wherein the 12-bit a/D converter D8 is respectively connected to the output terminal of the operational amplifier N7 and the motherboard 12 to receive the analog signal amplified by the analog processing circuit 113 and convert the analog signal into a digital signal, and output the digital signal to the motherboard 12 for processing, the first terminal of the capacitor C16 is grounded, the second terminal of the capacitor C16 is connected to the second terminal of the resistor R25, the second terminal of the resistor R25 is further connected to the power conversion circuit 111 for receiving the input voltage V +5, the first end of the resistor R25, the input end of the inverter D25 and the C25 end of the trigger D25 are all connected with the motherboard component 12, the output end of the inverter D25 is connected with the C25 end of the trigger D25, the Q25 end of the trigger D25 is respectively connected with the first end of the resistor R25, the second end of the resistor R25 and the cathode end of the diode V25, the first end of the resistor R25, the anode end of the diode V25 and the first end of the capacitor C25 are all connected with the R25 end of the trigger D25, the second end of the capacitor C25 is grounded, the second end of the resistor R25 is respectively connected with the first end of the capacitor C25 and the input end of the inverter D25, the second end of the capacitor C25 is grounded, the output end of the inverter D25 is connected with the C25 end of the trigger D25, the Q72 end and the Q25 end of the Q25 and the second end 25 of the capacitor A/D25 are connected with the bit A/D25, the first end of the capacitor D25, and the second end of the capacitor D25 are connected with the ground, the, The first end of the capacitor C21 and the first end of the capacitor C22 are both grounded, the second end of the capacitor C20 is connected to the first ends of the 12-bit a/D converter D8 and the capacitor C23, the second end of the capacitor C21, the second end of the capacitor C22 and the second end of the capacitor C23 are connected to the 12-bit a/D converter D8, the first end of the capacitor C24 and the first end of the capacitor C25 are both connected to the power conversion circuit 111, the second end of the capacitor C24 is connected to the 12-bit a/D converter D8, the second end of the capacitor C25 and the second end of the capacitor C26 are grounded, the first end of the capacitor C26 is connected to the power conversion circuit 111, and the RAD end of the 12-bit a/D converter D8 is also connected to the R1 and S2 ends of the flip-flop D7. The capacitance value of the capacitor C16 is 68nF, the capacitance value of the capacitor C17 is 1.2nF, the capacitance values of the capacitor C18 and the capacitor C19 are 47pF, the capacitance values of the capacitor C20, the capacitor C21, the capacitor C22, the capacitor C23, the capacitor C24, the capacitor C25 and the capacitor C26 are all 0.47 muF, the resistance value of the resistor R25 is 2k omega, the resistance values of the resistor R26 and the resistor R27 are 39k omega, the types of the inverters D4 and D6 are 564JIE5B, the type of the flip-flop D5 is 564TM2B, the type of the flip-flop D7 is 1533TM2, the type of the diode V5 is 1N4148, and the type of the 12-bit A/D converter D8 is 1108 IIB 2.

It is understood that pin 3 (i.e., the pin connected to the terminal Q2 of the flip-flop D7) of the 12-bit a/D converter D8 is a start signal, pin 4 (i.e., the pin connected to the terminal Q1 of the flip-flop D7) is a chip select signal, the low level is active, pin 18 (i.e., the RAD terminal) is a "ready" signal, pin 18 outputs the high level when pin 3 is the high level, pin 18 outputs the low level when pin 3 is the low level, and pin 32 (i.e., the pin connected to the output terminal of the operational amplifier N7) is an analog input terminal. When the power is turned on, the Q2 of the flip-flop D5 is at a low level, the Q1 of the flip-flop D7 is at a low level, the Q2 of the flip-flop D7 is at a high level, and the RAD of the 12-bit A/D converter D8 is at a high level. When the a30 signal sent by motherboard component 12 changes from low level to high level, the Q1 of flip-flop D7 outputs high level, the 12-bit a/D converter D8 is unselected and does not operate, and the Q2 of flip-flop D5 and the Q2 of flip-flop D7 remain unchanged. When the a30 signal sent by the motherboard assembly 12 changes from high level to low level, the Q1 terminal of the flip-flop D7 outputs low level, the Q2 terminal of the flip-flop D5 outputs high level, the high level charges the capacitor C17 through the resistor R26, the voltage at the R2 terminal of the flip-flop D5 gradually rises, when the voltage changes to high level, the Q2 terminal of the flip-flop D5 is reset to low level, the Q2 terminal of the flip-flop D5 actually outputs a positive pulse signal, and the pulse width is:

wherein, Vt is the high level voltage at the R2 terminal of the flip-flop D5, R is the resistance of the resistor R26, and C is the capacitance of the capacitor C17. Diode V5 is used for rapid discharge of capacitor C17. After a positive pulse signal output by a Q2 end of the flip-flop D5 passes through the inverter D6, a negative pulse signal is input by a C2 end of the flip-flop D7, the output of a Q2 end of the flip-flop D7 becomes low level, a RAD end of the 12-bit A/D converter D8 outputs low level, a Q1 end of the flip-flop D7 is reset to low level, a Q2 end of the flip-flop D7 is set to high level, and the RAD end of the 12-bit A/D converter D8 restores to high level, in the process, the analog quantity signal U₀₅Is converted into a digital quantity signal. It is understood that one of the functions of the a/D conversion and control circuit 114, inverters D4 and D6 of the present embodiment is to logically invert the input signal, and to shape the input signal into a standard voltage output. The flip-flops D5 and D7 function to process the input signal according to the triggering of the clock CLK signal, and have a function of latching the output. D8 is a 12-bit a/D converter that functions to convert an input analog quantity into a 12-bit digital quantity. R27 and C18 form a low-pass filter circuit, and a diode V5 is used for quickly discharging the capacitor.

As shown in fig. 7, the speed signal conditioning circuit 115 includes a resistor R28, a resistor R29, a resistor R30, a resistor R31, a capacitor C27, a zener diode V6, a diode V7, a diode V8, an operational amplifier N8, an inverter D9, and a flip-flop D10, a first end of the resistor R30 is connected to an external speed sensor to acquire a sinusoidal signal thereof, a second end of the resistor R28 is connected to a negative end of the zener diode V6, a first end of the capacitor C27, and an inverting input end of the operational amplifier N8, a positive end of the zener diode V6 and a second end of the capacitor C27 are grounded, a first end of the resistor R29 is floating, a second end of the resistor R29 is connected to a first end of the resistor R30 and a non-inverting input end of the operational amplifier N8, a second end of the resistor R30 is grounded, a positive end of the diode V7 is connected to a pin 8 of the operational amplifier N8, and a negative end of the diode V7 is connected to a voltage converting circuit 111 +5, the positive terminal of the diode V8 is grounded, the negative terminal of the diode V8 is connected to pin 8 of the operational amplifier N8, the first terminal of the resistor R31 is connected to the non-inverting input terminal of the operational amplifier N8, the second terminal of the resistor R31 is connected to the output terminal of the operational amplifier N8, the output terminal of the operational amplifier N8 is further connected to the input terminal of the inverter D9, the output terminal of the inverter D9 is connected to the C1 terminal of the flip-flop D10, the Q2 terminal of the flip-flop D10 is connected to the D1 terminal thereof, and the Q1 terminal of the flip-flop D10 is connected to the motherboard component 12. The resistance value of the resistor R28 is 2k omega, the resistance value of the resistor R29 is 150k omega, the resistance value of the resistor R30 is 0.1k omega, the resistance value of the resistor R31 is 24k omega, the model of the voltage stabilizing diode V6 is 2C212B, the capacitance value of the capacitor C27 is 1nF, the model of the inverter D9 is 564JIE5B, the model of the diodes V7 and V8 is 1N4148, and the model of the trigger D10 is 564TM 2B. It can be understood that the sinusoidal signal f inputted by the tachometer outputs a square wave having the same frequency as f through the operational amplifier N8, the square wave signal serves as a clock signal of the flip-flop D10 through the inverter D9, and the Q1 of the flip-flop D10 outputs a square wave signal having a frequency of 0.5f to the motherboard component 12. It can be understood that the speed signal conditioning circuit 115 of the present embodiment, the operational amplifier N86 is connected to form a comparator circuit, which is used to convert the input sinusoidal signal into a signal similar to a square wave, one of the functions of the inverter D9 is to logically invert the input signal, and shape the input signal into a standard voltage output, and the flip-flop D5 is used to convert the input signal into a square wave, and the control frequency is half of the input signal.

As shown in fig. 8, the D/a conversion and execution mechanism control circuit 116 specifically includes a potentiometer RP3, a potentiometer RP4, a potentiometer RP5, a capacitor C28, a capacitor C29, a capacitor C30, a capacitor C31, a resistor R31, a latch D31, a 12-bit D/a converter D31, an operational amplifier N31, a transistor V31, and a transistor V31, wherein first ends of the potentiometer RP 31 and the potentiometer RP 31 are all connected to the power board assembly 15, a first end of the potentiometer RP 31 is connected to a third end thereof, a second end of the potentiometer RP 31 and a second end of the potentiometer RP 31 are all connected to the D/a converter D31, an input end of the D31 is connected to the D/a converter D31, an output end of the motherboard 31 and the D31, a first terminal of a capacitor C28 is connected to the power conversion circuit 111, a second terminal of a capacitor C28 is grounded, a first terminal of a resistor R32 is grounded, a second terminal of a resistor R32 is connected to the 12-bit D/a converter D12, both terminals of a capacitor C29 are connected to the pin No. 3 and the pin No. 11 of the 12-bit D/a converter D12, respectively, an output terminal of the 12-bit D/a converter D12 is connected to an inverting input terminal of the operational amplifier N10, an output terminal of the operational amplifier N10 is connected to a non-inverting input terminal of the operational amplifier N11 and the pin No. 9 of the 12-bit D/a converter D12, respectively, a first terminal of a capacitor C31 and a non-inverting input terminal of the 12-bit D/a converter D12 are grounded, a second terminal of a capacitor C31 is connected to the pin No. 4 of the 12-bit D/a converter D12, a first terminal of a capacitor C30 is connected to the pin No. 7 of the 12-bit, two ends of a capacitor C32 are respectively connected with a pin No. 1 and a pin No. 8 of a 12-bit D/A converter D12, two ends of a capacitor C33 are respectively connected with a pin No. 1 and a pin No. 8 of an operational amplifier N11, a second end of a potentiometer RP5 is grounded, a first end of a potentiometer RP5 is respectively connected with a third end thereof and a first end of a resistor R34, a second end of a resistor R34 is respectively connected with a first end of a resistor R33 and an inverting input end of the operational amplifier N12, a second end of a resistor R33 and an output end of an operational amplifier N12 are respectively connected with the inverting input end of the operational amplifier N11, a resistor R35 is a sampling resistor, a first end of the resistor R35 is respectively connected with an electro-hydraulic servo valve and a positive phase input end of the operational amplifier N12, a second end of the resistor R35 is grounded, a first end of the capacitor C34 is grounded, a second end of the capacitor C84 is connected with a pin No. 8 of the operational amplifier N3742, and, The base electrode of the triode V10 is connected, the collector electrode of the triode V9 is connected with the power panel component 15, the collector electrode of the triode V10 is grounded, and the emitter electrode of the triode V9 and the emitter electrode of the triode V10 are both connected with the electro-hydraulic servo valve.

It is understood that the digital signal outputted from the motherboard component 12 is latched by the latch D11 and then outputted to the 12-bit D/a converter D12. The 12-bit D/a converter D12 only uses an 8-bit data port, converts a digital signal into a current signal, converts the current signal into a voltage through the operational amplifier N10, outputs the voltage to the actuator control circuit, and feeds back the voltage to the pin 9 of the 12-bit D/a converter D12 to adjust the output of the 12-bit D/a converter D12, and the potentiometer RP3 and the potentiometer RP4 are used to adjust the current output to the pin 4 and the pin 5 of the 12-bit D/a converter D12. The voltage output by the operational amplifier N11 adjusts the conduction degree of the transistor V9 and the transistor V10, thereby controlling the current input to the electrohydraulic servo valve, and the resistor R35 is a sampling resistor, which outputs the current voltage passing through the electrohydraulic servo valve to the operational amplifier N11 after being amplified in phase by the operational amplifier N12, and feeds back and adjusts the output voltage of the operational amplifier N11, wherein the output voltage of the operational amplifier N12 is:

U_R35＝IR₃₅

the total resistance values of the potentiometer RP3 and the potentiometer RP4 are 150 Ω, the total resistance value of the potentiometer RP5 is 22 Ω, the capacitance values of the capacitor C28, the capacitor C30, the capacitor C31, the capacitor C32 and the capacitor C34 are 68pF, the capacitance value of the capacitor C29 is 0.1nF, the capacitance value of the capacitor C33 is 0.51nF, the resistance value of the resistor R32 is 2k Ω, the resistance value of the resistor R33 is 14.3k Ω, the resistance value of the resistor R34 is 105 Ω, the resistance value of the resistor R35 is 1.14 Ω, the model of the latch D11 is 1533HP33, the model of the 12-bit D/a converter D12 is 1108 pi 1 ah, the models of the operational amplifiers N10 and N11 are 153 alder 6, the model of the operational amplifier N573 5 is 17A, and the model of the triode V9 and the model of the 58v 24 is the boot 830. It can be understood that in the D/a conversion and execution mechanism control circuit 116 of the embodiment, the latch D11 is used to latch the digital quantity signal inputted from the main control board at the output terminal, the D12 is a 12-bit D/a converter, which forms a D/a conversion circuit with the operational amplifier N10 to convert the digital quantity into a corresponding analog quantity, the operational amplifier N11 is used as a comparator to compare the feedback signal of the electrohydraulic servo valve with the analog quantity of the D/a conversion circuit, and the comparison result is used to drive the two triodes V9, V10, V9 and V10 which are large-current triodes for driving the voltage servo valve to operate. The operational amplifier N12 is used as a negative feedback amplifying circuit to amplify the feedback signal inputted from the electro-hydraulic servo valve, RP3 and RP4 adjust the reference current inputted to D12, and RP5 adjusts the amplification factor of the operational amplifier N12.

As shown in fig. 9, the motherboard assembly 12 specifically includes a single chip microcomputer and clock circuit 121, a power-on reset and watchdog circuit 122, a program memory and data memory circuit 123, a bus transceiver and memory control circuit 124, and an expansion bus circuit 125, where the power-on reset and watchdog circuit 122 and the bus transceiver and memory control circuit 124 are all connected to the single chip microcomputer and the clock circuit 121, and the bus transceiver and memory control circuit 124 is further connected to the expansion bus circuit 125, the program memory and data memory circuit 123, respectively. The power-on reset and watchdog circuit 122 is used to monitor the operation status of the single chip microcomputer, and once the single chip microcomputer has an error in operation, the single chip microcomputer is reset. The program memory and data memory circuit 123 is used for storing a main program and temporarily loaded operation data when the single chip microcomputer operates. The bus transceiver and memory control circuit 124 is used for receiving and transmitting data of the single chip microcomputer and performing read-write control on the two program memories. The expansion bus circuit 125 is used for data exchange between the motherboard assembly 12 and the outside.

As shown in fig. 10, the one-chip microcomputer and clock circuit 121 includes a one-chip microcomputer chip D13, a one-chip microcomputer chip D14, a capacitor C35, a capacitor C36, a crystal oscillator G36, and a crystal oscillator G36, wherein a first end of the capacitor C36 and a first end of the capacitor C36 are both grounded, a second end of the capacitor C36 is connected to the BQ 36 of the one-chip microcomputer chip D36, a second end of the capacitor C36 is connected to the BQ 36 of the one-chip microcomputer D36, two ends of the crystal oscillator G36 are respectively connected to the BQ 36 and the BQ 36 of the one-chip microcomputer chip D36, the first end of the capacitor C36 and the first end of the capacitor C36 are both grounded, the second end of the capacitor C36 is connected to the XTAL 36 of the one-chip microcomputer chip D36, and the XTAL 36 of the crystal oscillator G36 are respectively connected to the XTAL 36 and the XTAL 36 of the one-chip D36. The singlechip chip D13 is a Russian singlechip and is of the type of NE1830 BE 31, the singlechip chip D14 is an 8-bit MCS-51 kernel series and is of the type of 80C31, and the capacitance values of the capacitor C35, the capacitor C36, the capacitor C37 and the capacitor C38 are 30 pF. The two single-chip microcomputers have independent 12MHz frequency clock circuits, share a bus, a program memory and a data memory, and have simpler circuit structures. It can be understood that in the single chip microcomputer and the clock circuit 121 of the embodiment, D14 is a 51-series single chip microcomputer, D14 is a backup of D13, the main frequency of the crystal oscillators G1 and G2 is 12MHz, and is used as a working reference clock of an internal circuit of the single chip microcomputer, and C35, C36, C37, and C38 are used as matching capacitors of the crystal oscillator and are used for starting oscillation of the crystal oscillator.

As shown in fig. 11, the power-on reset and watchdog circuit 122 includes a capacitor C39, a resistor R36, a resistor R37, a resistor R38, a resistor R39, a resistor R40, a resistor R41, a resistor R42, an inverter D15, an inverter D16, an inverter D17, an or gate D18, a flip-flop D19, a flip-flop D20, a nand gate D21, a nand gate D22, an inverter D23, an inverter D24, an inverter D25, an inverter D26, an or gate D27, a counter D28, a counter D29, and a counter D30, wherein a positive terminal of the capacitor C39 is connected to the power board assembly 15, a negative terminal of the capacitor C39 is connected to a first terminal of the resistor R36, an input terminal of the inverter D15, a set terminal of the flip-flop D15, a second terminal of the resistor R15 is grounded, an output terminal of the inverter D15 is connected to an input terminal of the inverter D15, an output terminal of the inverter D15, a reset terminal of the flip-flop P360, and the reset terminal of the single chip microcomputer P360, the output end of the inverter D17 is connected to the set end of the flip-flop D19 and the other input end of the or gate D18, the output end of the or gate D18 is connected to the second end of the resistor R37, the R end of the counter D28, the R end of the counter D29 and the R end of the counter D30, the reset end of the flip-flop D20 is connected to the Q end of the counter D29, the E end of the counter D29 is connected to the Q end of the counter D28, the E end of the counter D30 is connected to the Q end of the counter D29, the inverting output end of the flip-flop D20 is connected to the input end of the nand gate D21 and the input end of the nand gate D829, the other input end of the counter D30 is connected to the Q end of the counter D30, the output end of the nand gate D21 is connected to the other input end of the nand gate D22, the output end of the nand gate D22 is connected to the reset signal input end of the nand gate D38, the first end of the single chip microcomputer, The input end of an inverter D26 is connected, the first end of a resistor R39 is connected with the power board assembly 15, the second end of a resistor R39 is connected with the output end of a NAND gate D22, the first end of a resistor R40 is connected with the power board assembly 15, the second end of a resistor R40 is connected with the input end of an inverter D23 and the output end of an inverter D25 respectively, the output end of an inverter D23 is connected with the first end of a resistor R41, the second end of the resistor R41 is connected with the input end of an inverter D24 and the first end of a capacitor C40 respectively, the output end of an inverter D24 is connected with the first end of a resistor R42, the second end of a resistor R42 is connected with the second end of a capacitor C40 and the input end of an inverter D25 respectively, the output end of an inverter D25 and the output end of an inverter D26 are connected with the two input ends of an OR gate D27 respectively, or the. It can be understood that when power is on, a pulse generated at the resistor R36 is a high level pulse of about 38.5ms, the inverter D16 outputs a high level, the or gate D18 outputs a high level, and the counters D28, D29, and D30 are all reset (i.e., all output terminals output a low level); the trigger D20 is set, the inverted output end of the trigger D20 outputs low level, the NAND gate D22 outputs high level to the reset signal input end of the single chip microcomputer, and the single chip microcomputer resets. And when the power-on is finished and the reset pulse is small, the inverter D23, the resistor R41, the inverter D24, the capacitor C40, the resistor R42 and the inverter D25 form a ring oscillator with RC delay, and the theoretical calculation frequency is 50 KHz. The clock signal generated by the ring oscillator is input to the clock input terminal of the counter D28, and a watchdog timer with the period of 41ms is formed by the counter D28, the counter D29 and the counter D30. The P1.0 port of the singlechip is used for outputting a dog feeding instruction (low-level pulse), and the low-level pulse realizes zero clearing of the timer through an inverter D17 and an OR gate D18. The capacitance value of the capacitor C39 is 6.8 muF, the resistance value of the resistor R36 is 8.2k omega, the resistance values of the resistors R37, R38, R39 and R40 are 1.2k omega, the resistance values of the resistors R41 and R42 are 620 omega, the models of the inverters D15, D16, D17 and D26 are 564 n-l 2B, the models of the inverters D23, D24 and D25 are 1533 n-l 2, the models of the gates D18 and D27 are 1533 n-l 2, the models of the flip-flops D19 and D20 are 564TM2B, the models of the NAND gates D21 and D22 are 533 n-l 13, and the models of the counters D28, D29 and D30 are 564V 10.

As shown in fig. 12, the program memory and data memory circuit 123 includes a program memory D31, a program memory D32, and a data memory D33, the program memories D31 and D32 are OTPROMs of 8K × 8, the model is 556PT161, the two program memories D31 and D32 share an address bus and a data bus, but have independent chip select control lines, the chip select signal is active low, the data memory D33 is a RAM with a capacity of 2K × 8, the model is 537py9, the address line is 11 bits, and the address line has a chip select, an output enable, and a read/write control signal line.

As shown in fig. 13 and 14, the bus transceiver and memory control circuit 124 includes a two-wire bus transceiver D34, a latch D35, a latch D36, A3-wire to 8-wire decoder D37, a resistor R43, a resistor bank R44, an and gate D39, a not gate D40, a not gate D41, an or gate D42, an or gate D43, an and gate D44, an and gate D45, an or gate D45, a resistor R45, the two-wire bus transceiver D45 is respectively connected with a single chip microcomputer and the latch D45, the latch D45 is connected with the single chip microcomputer, the 8-bit address bus a 45-a 45 is output from the single chip microcomputer to the two-way bus transceiver D45, and is output from the two-way bus transceiver D45 to the latch D45 and is latched at the output end of the latch D45, the 5-bit address bus a 45-a 45 is output from the single chip microcomputer to the latch D45 and latches the address value of the 13-bit memory output of the, the data from the memory is output D0-D7 to the B port of the two-wire bus transceiver D34, then to the A port of the two-wire bus transceiver D34, and finally to the single chip. An input end of the 3-line-8-line decoder D37 is connected to the single chip, an output end of the 3-line-8-line decoder D37 is connected to an input end of an or gate D46, an input end of an or gate D42, an input end of a not gate D41, an input end of an or gate D43, and an input end of an or gate D47, respectively, a first end of a resistor in the resistor bank R44 is connected to the power board assembly 15, a second end of the resistor bank R44 is connected to a Y0 end, a Y1 end, and a Y2 end of the 3-line-8-line decoder D37, a first end of the resistor R43 is connected to the power board assembly 15, a second end of the resistor R43 is connected to a G1 end of the 3-line-8-line decoder D37 and an LE end of the latch D36, a Q36 end of the latch D36 is connected to an input end of the and gate D36, a Q36 end of the latch D36 is connected to another input end of the and another input end of the gate D36 or, the output end of the and gate D39 is connected with the input end of the and gate D44, the output end of the not gate D40 is connected with the other input end of the and gate D44, the output end of the not gate D41 is connected with the input end of the and gate D45, the output end of the or gate D42 or the output end of the or gate D43 is floating, the first end of the resistor R45 and the first end of the resistor R46 are both connected with the power board assembly 15 to be connected with the +5V power voltage, the second end of the resistor R11 is respectively connected with the output end of the and gate D39 and the other input end of the and gate D45, the second end of the resistor R46 is connected with the output end of the nand gate D40, the output end of the and gate D44 is connected with the program memory D31, the output end of the and gate D45 is connected with the program memory D32, the output end of. The six signals of the address buses a013-a015, WR, RD, and PSEN are operated by the 3-line-8-line decoder D37, the latch D36, and the logic gate circuit, and the operation result controls the chip select signal of the memory, so that which memory is to be read or written is selected, and the read or write of the memory is controlled based on the logic gate circuit, and the circuit configuration is very simple.

It can be understood that in the bus transceiving and memory control circuit 124 of this embodiment, D37 is a 3-8 decoder, the input address signals a013-a015 control its output Y0-Y7, only one output port is an active signal at any time, D36 is a latch, which is used to latch the input WR, RD, PSEN at its output port to form S-WR, S-RD, S-PSEN signals, D39, D40, D41, D42, D43, D44, D45, D46, D47 to form a logic operation circuit, which operates the output signals of D37 and D36, and the operation result controls the chip select signal of the memory for selecting which memory to read or write.

It is understood that the model 533 of the two-wire bus transceiver D34 is 533/l 6, the model of the latches D35 and D36 is 1533/R33, the model of the 3-wire-8-wire decoder D37 is 533/l 7, the resistances of the resistors R43, R45 and R46 are 1.2k Ω, the total resistance of the resistor row R44 is 5.1k Ω, the models of the and gates D39 and D44 are 533/l 13, the model of the not gate D40 is 1533/l 2, the model of the not gate D41 is 533/l 2, the model of the and gate D45 is 1533/l 1, or the models of the gates D42, D43, D46 and D47 are 533/l 1.

As shown in fig. 15, the expansion bus circuit 125 specifically includes a latch D48, a latch D49, a latch D50, a latch D51, a latch D52, a latch D53, and a latch D54, which are sequentially connected to the bus, wherein the latch D48, the latch D49, the latch D50, and the latch D51 are used for data output, and the latch D52, the latch D53, and the latch D54 are used for data input.

As shown in fig. 16, the bus transceiver board assembly 13 includes six first optical coupler conversion circuits 131, six bus transceiver circuits 132, and a channel selection circuit 133, each first optical coupler conversion circuit 131 is connected to one bus transceiver circuit 132, the six first optical coupler conversion circuits 131 are configured to optically couple 6 sets of input switching value signals (8 signals in each set) into digital value signals, the channel selection circuit 133 is connected to the six bus transceiver circuits 132, the six bus transceiver circuits 132 are connected to the motherboard assembly 12, and the channel selection circuit 133 is configured to gate any one of the six bus transceiver circuits 132, so that a corresponding set of digital value signals is output to the motherboard assembly 12. The first optical coupler conversion circuit 131 includes 8 identical first optical coupler conversion unit circuits, as shown in fig. 17, the first optical coupler conversion unit circuit includes a zener diode V11, a resistor R47, a capacitor C40, an optical coupler B1, a resistor R48, and a resistor R49, the negative end of the voltage-stabilizing diode V11 is connected with a bus to access a switching value signal, the positive end of the voltage-stabilizing diode V11 is connected with the first end of a resistor R47, the second end of the resistor R47 is connected with the positive end of a capacitor C40 and the No. 4 pin of an optocoupler B1 respectively, the second end of the capacitor C40 and the No. 2 pin of the optocoupler B1 are all grounded, the first end of the resistor R49 is connected with a power supply, the second end of the resistor R49 is connected with the No. 1 pin of the optocoupler B1, the first end of the resistor R48 is connected with the No. 3 pin of the optocoupler B1, the No. 5 pin of the optocoupler B1 and the second end of the resistor R48 are grounded, and the No. 1 pin of the optocoupler B1. The first optical coupling conversion unit circuit has two functions, namely converting input switching value into digital value so as to facilitate the use of subsequent circuits, and isolating input to avoid external interference signal input. When a 27V switching value signal is input into the circuit, the light emitting diode between the No. 4 pin and the No. 2 pin of the optocoupler B1 is conducted, the output ends (namely the No. 1 pin and the No. 5 pin) are conducted, and the circuit outputs 0V; when the circuit has no switching value signal input, the light emitting diode at the input end of the optocoupler B1 is cut off, the output end of the optocoupler B1 is cut off, and the circuit output voltage is VCC. And, the breakdown voltage of zener diode V11 is 12V, and only when input voltage is greater than 12V, this zener diode V11 is punctured, and opto-coupler B1 can switch on, has avoided the interference of external signal to cause opto-coupler B1 misconnection. The model of the voltage stabilizing diode V11 is BZX85/C12, the resistance value of the resistor R47 is 1.5k omega, the resistance value of the resistor R48 is 100k omega, the resistance value of the resistor R49 is 6.2k omega, the model of the optocoupler B1 is 3OT126A, and the capacitance value of the capacitor C40 is 47 muF.

As shown in fig. 18, the bus transceiver circuit 132 includes a resistor R50 and a bus transceiver D55, a first end of the resistor R50 is connected to a power supply, a second end of the resistor R50 is connected to

pins

2, 3, 15, and 26 of the bus transceiver D55, an output end of the bus transceiver D55 is connected to the motherboard component 12, and the digital quantity digital value bus transceiver D55 has pins 16 to 13 on the left side thereof converted by an optical coupler B1, and when a pin 1 of the bus transceiver D55 is active, the bus transceiver D55 operates to output the digital quantity signal to pins 13 to 6 on the right side thereof. The outputs of the six bus transceivers D55 are shorted, and at most one bus is active at any time under the control of pin No. 1 chip select signal (CS, active low).

As shown in fig. 19, the channel selection circuit 133 includes a resistor R51 and a 3-line-8-line decoder D56, a first end of the resistor R51 is connected to the power supply, a second end of the resistor R51 is connected to pin 6 of the 3-line-8-line decoder D56, pin 1, pin 2, and pin 3 of the input end of the 3-line-8-line decoder D56 are all connected to the motherboard 12, pin 10 to pin 15 of the output end of the 3-line-8-line decoder D56 are respectively connected to pin 1 of the six bus transceivers D55, the motherboard 12 sends out a control signal, only one output end pin of the 3-line-8-line decoder D56 is at a low level at any time, and the circuit where the bus transceiver D55 corresponding to the threshold is located is gated, so as to output digital data to the motherboard 12.

As shown in fig. 20, the output interface board assembly 14 specifically includes four latch circuits 141 and four second optical coupling conversion circuits 142, an input end of each latch circuit 141 is connected to the motherboard assembly 12, an output end of each latch circuit 141 is connected to the second optical coupling conversion circuit 142, each latch circuit 141 is correspondingly connected to one second optical coupling conversion circuit 142, each latch circuit 141 is configured to latch a digital quantity signal output by the motherboard assembly 12 at an output end thereof, and keep the digital quantity signal unchanged until a next set of digital quantity arrives, and each second optical coupling conversion circuit 142 is configured to convert the input digital quantity signal into a switching quantity signal, isolate input and output, avoid interference, and then transmit the switching quantity signal to each accessory of the gas turbine generator set.

Specifically, as shown in fig. 21, the latch circuit 141 includes a resistor R52, a resistor R53, a capacitor C41, and a latch D57, a first end of the resistor R53 is connected to the power board assembly 15, a second end of the resistor R53 is connected to an OE end of the latch D57, an OE end of the latch D57 is further connected to the motherboard assembly 12, a first end of the resistor R52 is connected to the motherboard assembly 12, a second end of the resistor R52 is connected to a first end of the capacitor C41 and an LE end of the latch D57, a second end of the capacitor C41 is grounded, pins No. 2 to No. 9 at an input end of the latch D57 are connected to the motherboard assembly 12 to access an 8-bit digital quantity signal, and pins No. 12 to No. 19 at an output end of the latch D57 are connected to the second optical coupler conversion circuit. The type of the latch D57 is 1533P 33, the motherboard component 12 inputs 8-bit digital quantity signals to the pins 2-9 of the latch D57 input end, when the control signals OE, LE input by the motherboard component 12 are both valid, the latch D57 works to latch the signals to the output end. The input ends of the four latch circuits 141 are in short circuit, the No. 1 pin OE enabling end is in short circuit, and only one latch circuit 141 is in a working state at most at any time under the control of the No. 11 pin LED end signal. The resistance values of the resistor R52 and the resistor R53 are 1k omega, and the capacitance value of the capacitor C41 is 510 pF. The resistance value of the resistor R54 is 300 omega, the model of the optocoupler B2 is 3OT123A, the resistance value of the resistor R55 is 3k omega, the resistance value of the resistor R56 is 100k omega, the resistance value of the resistor R57 is 1.2k omega, the resistance value of the resistor R58 is 560 omega, the capacitance value of the capacitor C42 is 22nF, the model of the triode V12 is 2T 830R, the model of the triode V13 is 2T208M, and the model of the diode V14 is 2 II 120A 1. The resistor R52 and the capacitor C51 form a low-pass filter circuit.

The second optical coupler conversion circuit 142 includes 8 identical second optical coupler conversion unit circuits, as shown in fig. 22, each second optical coupler conversion unit circuit includes a resistor R54, a resistor R55, a resistor R56, a resistor R57, a resistor R58, an optical coupler B2, a capacitor C42, a transistor V12, a transistor V13, and a diode V14, a first end of the resistor R54 is connected to a power supply, a second end of the resistor R54 is connected to a pin No. 4 of the optical coupler B2, a pin No. 2 of the optical coupler B2 is connected to the motherboard assembly 12, a pin No. 1 of the optical coupler B2 is connected to a first end of the resistor R55, a pin No. 5 of the optical coupler B2 is grounded, a pin No. 3 of the optical coupler B2 is connected to a first end of the resistor R56, a second end of the resistor R56 is grounded, a first end of the resistor R57 is connected to a power supply to a voltage +27V, a first end of the capacitor C42 is connected to the power supply, a second end of the resistor R57 and a second end of the resistor R, the second end of the resistor R55 is also connected with the base of the triode V13, the first end of the resistor R58 is connected with a power supply to be connected with +27V voltage, the second end of the resistor R58 is connected with the emitter of the triode V13, the emitter of the triode V12 is connected with the power supply to be connected with +27V voltage, the base of the triode V12 is connected with the emitter of the triode V13, the collector of the triode V12 and the collector of the triode V13 are both connected with the positive end of the diode V14, and the negative end of the diode V14 is connected with accessories of the gas turbine generator set. When 0V is input into the pin No. 2 of the optocoupler B2, a light emitting diode between the pin No. 4 and the pin No. 2 of the optocoupler B2 is conducted, the pin No. 1 and the pin No. 5 of the output end are conducted, the base voltage of the triode V13 is divided by the resistor R55 and the resistor R57, so that Vb is smaller than Ve, the triode V13 is conducted, the triode V12 is conducted, and the +27V voltage is output through the emitter-collector of the triode V12 and the diode V14; when 5V is input into the pin No. 2 of the optocoupler B2, the light emitting diode at the input end of the optocoupler B2 is cut off, the output end of the optocoupler is cut off, the transistor V13 is Vb ═ Ve ≈ 27V, the transistor V13 is cut off, the transistor V12 is cut off, and the output end of the circuit is in a suspension state.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A digital electronic control device of a gas turbine generator set is characterized in that,

the fuel regulator comprises a conversion board assembly (11), a mainboard assembly (12), a bus transceiver board assembly (13), an output interface board assembly (14) and a power board assembly (15), wherein the conversion board assembly (11) is used for collecting signals of a lubricating oil temperature sensor, an air inlet temperature sensor, an exhaust temperature thermocouple and a rotating speed sensor, converting the signals and then transmitting the signals to the mainboard assembly (12) for processing, and is also used for converting digital quantity signals output by the mainboard assembly (12) into analog quantity signals to control the current flowing through the fuel regulator, the mainboard assembly (12) is used for operating and processing input signals and outputting corresponding control signals, the bus transceiver board assembly (13) is used for converting six groups of switching quantity signals input from the outside into digital quantity signals and then transmitting one group of the digital quantity signals to the mainboard assembly (12) for processing, the output interface board assembly (14) is used for converting the 8-bit digital quantity signal output by the main board assembly (12) into a switching quantity signal to be output so as to control each accessory of the gas turbine generator set, and the power board assembly (15) is used for converting an external power supply voltage into a working voltage required by each assembly;

the main board assembly (12) comprises a single chip microcomputer and clock circuit (121), a power-on reset and watchdog circuit (122), a program memory and data memory circuit (123), a bus transceiving and memory control circuit (124) and an expansion bus circuit (125), wherein the power-on reset and watchdog circuit (122) and the bus transceiving and memory control circuit (124) are respectively connected with the single chip microcomputer and the clock circuit (121), the bus transceiving and memory control circuit (124) is also respectively connected with the expansion bus circuit (125), the program memory and data memory circuit (123), the power-on reset and watchdog circuit (122) is used for monitoring the operation condition of the single chip microcomputer, the single chip microcomputer is reset once the operation of the single chip microcomputer is wrong, and the program memory and data memory circuit (123) is used for storing a main program and temporarily loaded operation data during the operation of the single chip microcomputer, the bus transceiving and memory control circuit (124) is used for receiving and sending data of the single chip microcomputer and performing read-write control on the two program memories, and the expansion bus circuit (125) is used for exchanging data between the main board assembly (12) and the outside.

2. The digital electronic control device of a gas turbine generator set of claim 1,

the power-on reset and watchdog circuit (122) comprises a capacitor C, a resistor R, a inverter D, a phase inverter D, an OR gate D, a trigger D, a NAND gate D, a phase inverter D, a OR gate D, a counter D and a counter D, wherein the positive terminal of the capacitor C is connected with a power panel assembly (15), the negative terminal of the capacitor C is respectively connected with the first terminal of the resistor R, the input terminal of the phase inverter D and the setting terminal of the trigger D, the second terminal of the resistor R is grounded, the output terminal of the phase inverter D is connected with the input terminal of the phase inverter D, the output terminal of the phase inverter D is respectively connected with the input terminal of the OR gate D and the reset terminal of the trigger D, the, the output end of the inverter D17 is connected with the set end of a flip-flop D19 and the other input end of an OR gate D18, the output end of the OR gate D18 is connected with the second end of a resistor R37, the R end of a counter D28, the R end of a counter D29 and the R end of a counter D30, the reset end of the flip-flop D20 is connected with the Q end of a counter D29, the E end of a counter D29 is connected with the Q end of a counter D28, the E end of a counter D30 is connected with the Q end of a counter D29, the inverting output end of the flip-flop D20 is connected with the input end of a NAND gate D21 and the input end of a NAND gate D829, the other input end of a counter D30 is connected with the Q end of the counter D30, the output end of the NAND gate D21 is connected with the other input end of a NAND gate D22, the output end of a NAND gate D22 is connected with the reset signal input end of a resistor R38, the first end of a single chip microcomputer power supply, The input end of an inverter D26 is connected, the first end of a resistor R39 is connected with a power board assembly (15), the second end of a resistor R39 is connected with the output end of a NAND gate D22, the first end of a resistor R40 is connected with the power board assembly (15), the second end of a resistor R40 is respectively connected with the input end of the inverter D23 and the output end of an inverter D25, the output end of an inverter D23 is connected with the first end of a resistor R41, the second end of the resistor R41 is respectively connected with the input end of an inverter D24 and the first end of a capacitor C40, the output end of an inverter D24 is connected with the first end of a resistor R42, the second end of a resistor R42 is respectively connected with the second end of a capacitor C40 and the input end of an inverter D25, the output end of an inverter D25 and the output end of an inverter D26 are respectively connected with the two input ends of an OR gate D27, or the; when the power is on, a high-level pulse is generated on the resistor R36, the inverter D16 outputs a high level, the OR gate D18 outputs a high level, the counters D28, D29 and D30 are all reset, the flip-flop D20 is set, the inverted output end of the flip-flop D20 outputs a low level, the NAND gate D22 outputs a high level to the reset signal input end of the single chip microcomputer, the single chip microcomputer is reset, when the power is on and the reset pulse is reduced, the inverter D23, the resistor R41, the inverter D24, the capacitor C40, the resistor R42 and the inverter D25 form a ring oscillator with RC delay, a clock signal generated by the ring oscillator is input to the clock input end of the counter D28, the watchdog is formed by the counter D28, the counter D29 and the counter D30, a P1.0 port of the watchdog is used for outputting a feeding instruction, and the low-level pulse realizes zero clearing of the timer through the inverter D17 and the counter D18.

3. The digital electronic control device of a gas turbine generator set of claim 2,

the capacitance value of the capacitor C39 is 6.8 muF, the resistance value of the resistor R36 is 8.2k omega, the resistance values of the resistors R37, R38, R39 and R40 are 1.2k omega, the resistance values of the resistors R41 and R42 are 620 omega, the models of the inverters D15, D16, D17 and D26 are 564 n-l 2B, the models of the inverters D23, D24 and D25 are 1533 n-l 2, the models of the gates D18 and D27 are 1533 n-l 2, the models of the flip-flops D19 and D20 are 564TM2B, the models of the NAND gates D21 and D22 are 533 n-l 13, and the models of the counters D28, D29 and D30 are 564V 10.

4. The digital electronic control device of a gas turbine generator set of claim 2,

the program memory and data memory circuit (123) comprises a program memory D31, a program memory D32 and a data memory D33, wherein the program memories D31 and D32 are OTPROMs of 8K 8, the two program memories D31 and D32 share an address bus and a data bus, but have independent chip selection control lines, chip selection signals are effective in low level, the data memory D33 is a RAM with the capacity of 2K 8, address lines are 11 bits, and the chip selection control lines, output enabling lines and read-write control signal lines are provided.

5. The digital electronic control device of a gas turbine generator set of claim 4,

the bus transceiving and memory control circuit (124) comprises a two-wire bus transceiver D34, a latch D35, a latch D36, A3-wire-8-wire decoder D37, a resistor R37, a resistor bank R37, an AND gate D37, a NOT gate D37, an OR gate D37, an AND gate D37, a resistor R37 and a resistor R37, wherein the two-wire bus transceiver D37 is respectively connected with a single chip microcomputer and the latch D37, the latch D37 is connected with the single chip microcomputer, 8-bit address bus A37-A37 is output from the single chip microcomputer to the two-way bus transceiver D37, then the two-way bus D37 is output to the latch D37 and is latched at the output end of the latch D37, a 5-bit address bus A37-37A 37 is output to the latch D37, the address output end of the 13-bit bus for controlling the data output of the memory D37, the two-wire bus transceiver D37 is first output port of the two-wire bus transceiver 37, then the signal is sent to an A port of a dual-wire bus transceiver D34 and finally sent to a single chip microcomputer, an input end of a 3-wire-8-wire decoder D37 is connected with the single chip microcomputer, an output end of the 3-wire-8-wire decoder D37 is respectively connected with an input end of an OR gate D46, an input end of an OR gate D42, an input end of an NOT gate D41, an input end of an OR gate D43 and an input end of an OR gate D47, a first end of a resistor in a resistor bank R44 is connected with a power supply board assembly (15), a second end of the resistor R43 is respectively connected with a Y0 end, a Y1 end and a Y2 end of a 3-wire-8-wire decoder D37, a first end of a resistor R43 is connected with the power supply board assembly (15), a second end of the resistor R43 is respectively connected with a G1 end of the 3-wire-8-wire decoder D37 and an LE end of a latch D9, a Q5 end of a latch D39, a Q6 end of a latch D36, the Q7 of the latch D36 is connected to the other input of the or gate D42 and the other input of the or gate D46, the output of the and gate D39 is connected to the input of the and gate D44, the output of the not gate D40 is connected to the other input of the and gate D44, the output of the not gate D41 is connected to the input of the and gate D45, the output of the or gate D42 and the output of the or gate D43 are floating, the first end of the resistor R45 and the first end of the resistor R46 are connected to the power supply board assembly (15) for receiving the +5V supply voltage, the second end of the resistor R11 is connected to the output of the and gate D39 and the other input of the and gate D45, the second end of the resistor R46 is connected to the output of the nand gate D40, the output of the and gate D44 is connected to the program memory D31, the output of the and gate D45 is connected to the output of the program memory D45, the address D45 a-015, and the data bus a-013 a-bus, The six signals WR, RD, and PSEN are operated by the 3-line-8-line decoder D37, the latch D36, and the logic gate circuit, and the operation result controls a chip select signal of the memory device, thereby selecting which memory device is to be read or written.

6. The digital electronic control device of a gas turbine generator set of claim 5,

the model of the dual-wire bus transceiver D34 is 533A L6, the model of the latch D35, D36 is 1533K 33, the model of the 3-wire-8-wire decoder D37 is 533D 7, the resistances of the resistors R43, R45, R46 are 1.2K Ω, the total resistance of the resistor row R44 is 5.1K Ω, the models of the AND gates D39, D44 are 533L 13, the model of the NOT gate D40 is 1533L 2, the model of the NOT gate D41 is 533L 2, the model of the AND gate D45 is 1533L 1, or the models of the gates D42, D43, D46, D47 are 533L 1.

7. The digital electronic control device of a gas turbine generator set of claim 2,

the expansion bus circuit (125) comprises a latch D48, a latch D49, a latch D50, a latch D51, a latch D52, a latch D53 and a latch D54 which are sequentially connected to the bus, wherein the latch D48, the latch D49, the latch D50 and the latch D51 are used for data output, and the latch D52, the latch D53 and the latch D54 are used for data input.

8. The digital electronic control device of a gas turbine generator set of claim 2,

the single-chip microcomputer and the clock circuit (121) comprise a single-chip microcomputer chip D, a capacitor C, a crystal oscillator G and a crystal oscillator G, wherein the first end of the capacitor C and the first end of the capacitor C are grounded, the second end of the capacitor C is connected with the BQ end of the single-chip microcomputer chip D, the second end of the capacitor C is connected with the BQ end of the single-chip microcomputer D, the two ends of the crystal oscillator G are respectively connected with the BQ end and the BQ end of the single-chip microcomputer chip D, the first end of the capacitor C and the first end of the capacitor C are grounded, the second end of the capacitor C is connected with the XTAL end of the single-chip microcomputer chip D, the two ends of the crystal oscillator G are respectively connected with the XTAL end and the XTAL end of the single-chip D, the single-chip microcomputer chip D is, as a working reference clock of an internal circuit of the singlechip, the capacitors C35, C36, C37 and C38 are used as matching capacitors of the crystal oscillator and are used for starting oscillation of the crystal oscillator.

9. The digital electronic control device of a gas turbine generator set according to any one of claims 1 to 8,

the bus transceiver panel assembly (13) comprises six first optical coupling conversion circuits (131), six bus transceiver circuits (132) and a channel selection circuit (133), wherein each first optical coupling conversion circuit (131) is connected with one bus transceiver circuit (132), the six first optical coupling conversion circuits (131) are used for converting 6 groups of input switching value signals into digital value signals through optical coupling, the channel selection circuit (133) is respectively connected with the six bus transceiver circuits (132), the six bus transceiver circuits (132) are connected with the mainboard assembly (12), and the channel selection circuit (133) is used for gating any one of the six bus transceiver circuits (132) to enable a corresponding group of digital value signals to be output to the mainboard assembly (12).

10. The digital electronic control device of a gas turbine generator set of claim 9,

the first optical coupling conversion circuit (131) comprises 8 identical first optical coupling conversion unit circuits, the first optical coupling conversion unit circuit comprises a voltage stabilizing diode V11, a resistor R47, a capacitor C40, an optical coupler B1, a resistor R48 and a resistor R49, the negative end of the voltage-stabilizing diode V11 is connected with a bus to access switching value signals, the positive end of the voltage-stabilizing diode V11 is connected with the first end of a resistor R47, the second end of the resistor R47 is respectively connected with the positive end of a capacitor C40 and a No. 4 pin of an optocoupler B1, the second end of the capacitor C40 and a No. 2 pin of the optocoupler B1 are grounded, the first end of the resistor R49 is connected with a power supply, the second end of the resistor R49 is connected with a No. 1 pin of the optocoupler B1, the first end of the resistor R48 is connected with a No. 3 pin of the optocoupler B1, a No. 5 pin of the optocoupler B1 and the second end of the resistor R48 are grounded, and a No. 1 pin of the optocoupler B1 is also connected with; when a 27V switching value signal is input into the circuit, the light emitting diode between the No. 4 pin and the No. 2 pin of the optical coupler B1 is switched on, the output end of the light emitting diode is switched on, the circuit outputs 0V, when the circuit has no switching value signal input, the light emitting diode at the input end of the optical coupler B1 is switched off, the output end of the optical coupler B1 is switched off, and the circuit output voltage is the power supply voltage.