CN101853051A - Man-machine interaction unit device - Google Patents
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Abstract
The invention discloses a man-machine interaction unit device, which comprises a central processing unit, a central processing unit minimum system module, a storage module, a display module and an MVB bus interface circuit, wherein the central processing unit minimum system module comprises a power module, a clock module, a reset module and a JTAG/COP interface circuit; the central processing unit is connected with the storage module and the central processing unit minimum system module; the central processing unit expands the MVB bus interface circuit through an external bus and communicates with a vehicle central control unit through an MVB bus; the display module comprises a graphics display controller; and the central processing unit is connected with a display through the graphics display controller, and is an industrial processor of Freescale Company. Through the device, CPU power consumption and system heating are effectively reduced, the stability of the man-machine interaction unit device is improved, the CPU computing power is greatly improved, and the product life cycle is prolonged.
Description
Technical field
The present invention relates to a kind of man-machine interaction unit display device, especially relate to a kind of man-machine interaction unit display apparatus that is applied to rail vehicles digitizing and graphical display process, this invention also can be used for similar field man-machine interaction unit electric equipment products.
Background technology
At present, along with the development of railway locomotive equipment, man-machine interaction unit device is shown by initial charactron, has developed into the stage of extensive employing LCD liquid crystal screen display.Liquid crystal screen display possesses abundanter information, provides the good man-machine interaction interface with figure, curve in conjunction with the mode of literal, is popular in users.LCD screen shows that replacing charactron shows, has become inevitable.
The existing liquid crystal screen display circuit design of using has 2 kinds of technical schemes to realize usually:
First kind of scheme:
Based on the core processing module of X86 series CPU technology, this processing module is a general CPU card providing of third party producer normally, except the CPU minimum system, also comprises serial ports, parallel port, LCD display interface and Standard bus interface.Current the most frequently used be that the CPU card adopts PC104 bus and interface board to interconnect, interface board is responsible for correspondence with foreign country and environmental data collecting, by PC104 bus and CPU card swap data, the CPU card is responsible for the processing of data and the demonstration of figure.
The CPU of X86 series has for many years application in the liquid crystal screen display kind, has facility and powerful technical support, the very convenient integrated exploitation of carrying out system, but the power consumption considerable influence stability of system.In application process for many years, this CPU card is the highest device of failure rate in the display always.The stack access node structure of PC104 module is unfavorable for the heat radiation of CPU, influences the ability of continuous working under the condition of high temperature, causes the generation of a lot of soft faults, brings extremely bad influence for the stability of whole system.
Second kind of scheme:
Based on the core processing module of ARM9 series CPU technology, this processing module can be designed to independent CPU card, also can make a whole plate with interface board, realizes the demonstration of collection, processing and the figure of data.
The application of ARM9 series CPU, it is big to have solved X86 series CPU power consumption, and the problem that thermal value is high has improved the stability of system greatly.But ARM9 series CPU does not possess the floating-point operation ability usually, is restricted in the application of high-end system.Simultaneously, because the ARM technology is to use at commercial field the earliest, the update of product is very fast, can't guarantee long life cycle in commercial Application.
Summary of the invention
The invention provides a kind of man-machine interaction unit device, this invention can overcome the technical matters that CPU arithmetic capability deficiency, system performance instability or product life cycle that prior art exists can't guarantee well, and the man-machine interaction unit device that a kind of arithmetic capability is powerful, system stability is high, the product life cycle is long is provided.
The invention provides a kind of embodiment of man-machine interaction unit device, a kind of man-machine interaction unit device, comprise central processing unit, the central processing unit minimum systematic module, memory module, display module, the MVB bus interface circuit, the central processing unit minimum systematic module comprises power module, clock module, reseting module and JTAG/COP interface circuit, central processing unit and memory module, the central processing unit minimum systematic module links to each other, central processing unit is by external bus expansion MVB bus interface circuit, communicate by MVB bus and vehicle central control module, display module comprises graphic display control, central processing unit links to each other with display by graphic display control, and described central processing unit adopts the technical grade processor of Freescale company.
As the further embodiment of the present invention, described graphic display control further directly is connected with the pci bus interface of central processing unit by the PCI multiplex bus, and graphic display control is by extending out the video memory of high speed SDRAM as graphic display control.
As the further embodiment of the present invention, described display module further comprises the LVDS interface circuit, and described graphic display control links to each other with LVDS interface liquid crystal display by the LVDS interface circuit.
As the further embodiment of the present invention, described man-machine interaction unit device further comprises FPGA module and encryption chip, encryption chip and FPGA module constitute encrypting module, the FPGA module links to each other with central processing unit, the FPGA module links to each other with a data lines of unibus encryption chip by an I/O interface, man-machine interaction unit device works on power, central processing unit sends the forcible authentication signal to the FPGA module, FPGA module controls encryption chip carries out computations, reading encrypted result of calculation, with the cryptographic calculation results contrast of FPGA module self, whether decision disposes FPGA modular design data, thus the operation of application program in the control central processing unit.
As the further embodiment of the present invention, further by FPGA module and keyboard circuit, the Flash storer links to each other with watchdog circuit described central processing unit.
As the further embodiment of the present invention, the further 32 bit processor MPC5200B that adopt based on the e300 kernel of described Freescale company's technical grade processor, described kernel is the superscale framework, high primary frequency low-power consumption kernel.
As the further embodiment of the present invention, described central processing unit links to each other with digital temperature sensor, real-time clock and audio decoding circuit by the I2C bus interface.
As the further embodiment of the present invention, described central processing unit links to each other with IC-card with touch-screen by the spi bus interface.
As the further embodiment of the present invention, as data-carrier store, and to select dominant frequency for use be that two 64M byte DDR SDRAM of 133MHz are as internal memory to the Nor Flash that described central processing unit extends out the 32M byte as the Nor Flash of program storage and 32M byte.
As the further embodiment of the present invention, described reseting module further comprises watchdog circuit, central processing unit links to each other with the FPGA module, the FPGA module links to each other with the input end of watchdog circuit, central processing unit is exported feeding-dog signal by the FPGA module to watchdog circuit, and watchdog circuit resets for central processing unit provides.
By using the described man-machine interaction unit device of embodiment of the present invention, reduced the heating of power consumption and the system of CPU effectively, make the system stability of man-machine interaction unit device improve, the arithmetic capability of CPU significantly improves simultaneously, and the life cycle of product also increases to some extent.
Description of drawings
In order to be illustrated more clearly in the embodiment of the invention or technical scheme of the prior art, to do to introduce simply to the accompanying drawing of required use in embodiment or the description of the Prior Art below, apparently, accompanying drawing in describing below only is some embodiments of the present invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is the systematic functional structrue block diagram 1 of the man-machine interactive unit equipment of the present invention;
Fig. 2 is the systematic functional structrue block diagram 2 of the man-machine interactive unit equipment of the present invention;
Fig. 3 is CPU and the peripheral circuit data and the address wire interface block diagram of the man-machine interactive unit equipment of the present invention;
Fig. 4 is the CPU initial configuration circuit block diagram of the man-machine interactive unit equipment of the present invention;
Fig. 5 is the FLASH memory circuitry block diagram of the man-machine interactive unit equipment of the present invention;
Fig. 6 is the DDR SDRAM circuit block diagram of the man-machine interactive unit equipment of the present invention;
Fig. 7 is the Peripheral Interface block diagram of the MPC5200B of the man-machine interactive unit equipment of the present invention;
Fig. 8 is the jtag interface circuit block diagram of the man-machine interactive unit equipment of the present invention;
Fig. 9 is the cpu clock circuit diagram of the man-machine interactive unit equipment of the present invention;
Figure 10 is the reset circuit schematic diagram of the man-machine interactive unit equipment of the present invention;
Figure 11 is the reset timing figure of the man-machine interactive unit equipment of the present invention;
Figure 12 is the 5V-3.3V circuit structure block diagram of the man-machine interactive unit equipment of the present invention;
Figure 13 is the 3.3V-2.5V circuit structure block diagram of the man-machine interactive unit equipment of the present invention;
Figure 14 is the 3.3V-1.5V circuit structure block diagram of the man-machine interactive unit equipment of the present invention;
Figure 15 is the MPC5200B electrifying timing sequence figure of the man-machine interactive unit equipment of the present invention;
Figure 16 is the graphics controller circuit structured flowchart of the man-machine interactive unit equipment of the present invention;
Figure 17 is the SDRAM video memory circuit structure block diagram of the man-machine interactive unit equipment of the present invention;
Figure 18 is the LVDS driving circuit structure block diagram of the man-machine interactive unit equipment of the present invention;
Figure 19 is the encrypted circuit structured flowchart of the man-machine interactive unit equipment of the present invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the invention, the technical scheme in the embodiment of the invention is clearly and completely described, obviously, described embodiment only is a part of embodiment of the present invention, rather than whole embodiment.Based on the embodiment among the present invention, those of ordinary skills are not making the every other embodiment that is obtained under the creative work prerequisite, and the subordinate is in the scope of protection of the invention.
Embodiment as a kind of man-machine interaction unit device of the present invention, as depicted in figs. 1 and 2 be that a kind of typical case of the present invention on field of track traffic rolling stock man-machine interaction unit device uses, the systematic functional structrue block diagram of Fig. 1 has been described the schematic block circuit diagram of mainboard
Man-machine interaction unit device comprises central processing unit, the central processing unit minimum systematic module, memory module, display module, the MVB bus interface circuit, the central processing unit minimum systematic module comprises power module, clock module, reseting module and JTAG/COP interface circuit, central processing unit and memory module, the central processing unit minimum systematic module links to each other, central processing unit is by external bus expansion MVB bus interface circuit, communicate by MVB bus and vehicle central control module, display module comprises graphic display control, central processing unit links to each other with display by graphic display control, and central processing unit adopts the technical grade processor of Freescale company.
Wherein: mainboard is that core makes up the processor minimum system with the MPC5200B central processing unit (CPU) of Freescale company.
Memory module comprises: the Nor Flash that extends out the 32M byte as the Nor Flash of program storage and 32M byte as data-carrier store; Selecting dominant frequency for use is that two 64M byte DDR SDRAM of 133MHz are as internal memory;
Utilize the I2C interface of CPU to extend out a digital temperature sensor and real-time clock;
Utilize the built-in CAN bus controller of CPU to realize two-way CAN bus;
Utilize the I2S bus of CPU to realize audio frequency Codec decoding function;
Utilize the SPI interface of CPU to realize touch-screen and IC-card function;
By outside LocalPlusBus bus expansion MVB bus interface circuit, can communicate by MVB bus and vehicle central control module;
Extend out a slice FPGA, carry out system logic management and keyboard scan, luminance brightness collection, realize Nand Flash controller and 1wire encryption chip interface function simultaneously;
Ethernet mac controller (ethernet controller) is provided, and the physical chip by MII interface expansion Ethernet provides standard 10/100Mbps self-adaptation Ethernet interface;
Utilize the USB interface of CPU, realize the USB2.0 message transmission rate of (12Mbps) at full speed, be used for the dump of data file;
Designed the RS232 interface circuit,, simply, reliably finished the download of this mainboard program by RS232 serial ports and these two kinds of interface modes of Ethernet;
1 road RS485 and 1 road RS422 communication interface are provided, are used for and the communicating by letter of expansion equipment.
CPU minimum system circuit module is the indispensable minimum circuit system that processor can work together, and has comprised power module, clock module, reseting module, JTAG/COP interface circuit.
Fig. 3 is the block diagram of the data and address bus of MPC5200B and peripheral circuit, and the data of MPC5200B and address wire adopt multiplexer mode, confirm by the electrification reset configuration pin.Wherein multiplexing address signal adopts special-purpose latch 74LVC574 to carry out address latch under the triggering of ale signal.Bus is Flash storer, MVB expansion, FPGA data and the address wire of connected system respectively, and pci bus connects LCD Control.In the time circulation in office, bus can only be shared for parts.MPC5200B and being connected of DDR SDRAM storer are that the DDR SDRAM bus (13 bit address buses, 32 bit data bus) by the MPC5200B special use realizes.
Fig. 4 is the schematic block circuit diagram of CPU initial configuration.Because this product uses on bigger locomotive of vibration or motor train unit, stop to use the cross-over connection cover, in assembling, can select the 0 Europe resistance of control corresponding line by welding is connected to high level or low level, thereby realize the initial configuration that powers on CPU.
Fig. 5 is the schematic block circuit diagram of Flash storer on the mainboard, always has 4 identical Flash, the program storage of 2 construction systems, 2 composition data storeies.Adopt 16 bit data patterns by BYTE pin level is set for high the selection, the CPU local data bus is operated in 32 bit patterns, therefore forms one 32 bit data bus pattern by 2 Flash.The CE signal of program storage selects CS0 to link to each other with the sheet of MPC5200B, is used for the system file storage; The CE signal of data-carrier store links to each other with the CS1 of MPC5200B, as data storage.The WP signal is a write protect signal, forbids in the process of system reset Flash being carried out write operation.
MPC5200B has a special SDRAM/DDR control interface, and in order to control SDRAM or DDR-SDRAM device, the monolithic DDR-SDRAM capacity of support can reach 256M (can support two).
The DDR-SDRAM of this mainboard has selected 2 DDR-SDRAM chips for use, its framework is 4 (banks) * 8M * 16 (64M bytes), and every bank row address number is 13, and the column address number is 10, the DDR-SDRAM of this mainboard is the space of 128MB altogether, can satisfy the service requirement of embedded OS.
The memory block theory diagram of two DDR-SDRAM compositions as shown in Figure 6.
Fig. 7 is the Peripheral Interface block diagram of MPC5200B, from as can be seen last, MPC5200B carries one road Ethernet controller, one road USB controller, six road PSC (serialization controller able to programme, the user can be configured to different patterns as required, as various modes such as URAT, SPI, AC97, Codec, IrDA), two-way I2C controller, one road TIMER controller.
The JTAG/COP interface circuit as shown in Figure 8, the JTAG/COP interface support program of MPC5200B is downloaded, single-step instruction is carried out, the setting and the functions such as observation, observation internal register state of program breakpoint, Fig. 8 is the JTAG/COP interface circuit block diagram of MPC5200B, the JTAG_TRST# pin of MPC5200B among the figure has been connected in PORRESET# (MPC5200B electrification reset) by a switching diode (being equivalent to the function with door here), like this, mainboard is when carrying out reset operation, and jtag register also can carry out reset operation.
MPC5200B needs to be used for producing required clock with 2 crystal oscillators.One is slow clock crystal oscillator, fixed-frequency is 32.768KHz, operation when usually only being used for supporting chip and powering on, then will switch to another frequency is the 33MHz crystal oscillator, master clock frequency is provided, the normal procedure that is used for operation processor, Fig. 9 are the circuit block diagrams that two crystal oscillators of clock are provided for MPC5200B.After the master clock frequency of 33M enters CPU, APLL by system carries out frequency multiplication, by but the multiple of control corresponding word selective system APLL frequency multiplication is set, handle at the process frequency division then and offer Peripheral Interface, wherein the clock behind one road frequency division provides clock through the APLL of kernel for kernel work.
Resetting of this mainboard mainly is resetting of MPC5200B, FLASH storer, ethernet physical layer chip (ethernet controller) and MVB bus interface circuit, and the mode that resets has that electrification reset, power monitoring reset, watchdog reset.
Figure 10 is the reseting module circuit block diagram of mainboard, adopts the watchdog circuit chip to constitute reset circuit, can monitor the power supply of 1.5V and 3.3V simultaneously, and possesses the operation of house dog supervision master routine.
When powering on, watchdog chip power vd D (3.3V) is when being higher than 1.1V, output low level RESET signal, the crucial power supply (3.3V and 1.5V) that this moment, chip began system monitors, as long as these two are monitored power supply and are lower than and monitor that (Vit of 3.3V is 2.93V to threshold value Vit herein, 1.5V Vit be 1.4V), RESET can keep output low level always, when being elevated to Vit greater than correspondence Deng the input of 3.3V and 1.5V, RESET still will keep the low level of 100ms to guarantee just to become high level after there are enough reset times in system again.After finishing if power on, be lower than corresponding Vit in case the input of 3.3V or 1.5V occurs, RESET saltus step immediately becomes low level.
The reset signal RESET of watchdog chip output directly connects with PORRESET#.And PORRESET# is the electrification reset of MPC5200B, also be the reset signal of whole mainboard, the reset signal of other device (FLASH storer, ethernet physical layer chip (ethernet controller) and FPGA (being used for resetting to the MVB Bus Interface Chip)) on it and the mainboard all is directly to be connected in series.So,, just can realize the reset function of these devices as long as watchdog chip is exported reset signal.
WDOG is the input of watchdog chip, it is directly linked to each other with the I/O of FPGA, then can realize resetting of mainboard: when system powers on by these two signals of WDOG, RESET and FPGA internal logic, then normally feed dog to WDI by FPGA, after starting fully Deng CPU, again the control of " house dog " is transferred to CPU.
The reseting module principle as shown in figure 10, MPC5200B has three pins and resets relevantly, is respectively PORRESET, HRESET and SRESET, in this mainboard, the various reset operations of MPC5200B is all undertaken by PORRESET#.Figure 11 is the reset timing figure of MPC5200B, when when PORRESET# is low level, also continuing 100us at least, CPU enters reset mode, the CPU internal logic makes HRESET and SRESET also become low level, enter latch mode and system clock and activate etc. the APLL of system, and PORRESET# becomes high level, CPU just finishes to reset, PORRESET becomes high level after 4096 clock period, and HRESET and SRESET also become high level by low level.
In addition, the PORRESET# of MPC5200B, HRESET# and SRESET# all can not realize the resetting of JTAG logic resetted to JTAG if desired, need to give the JTAG_TRST pin of MPC5200B put low level.Because FREESCALE do not recommend JTAG_TRST directly to link to each other with PORRESET#, so in this mainboard, JTAG_TRST connects together by a switching diode and PORRESET#, this switching diode in fact be equivalent to one with function.Like this, carry out that electrification reset, power monitoring reset, three kinds of watchdog resets all can be to the JTAG logic reset when resetting.
Feed circuit such as Figure 12 are to shown in Figure 14, mainboard uses the 5V power supply of man-machine interaction unit internal electric source module output as the input power supply, elder generation was through pi type filter after the 5V power supply advanced plate, reducing noise and interference, and then obtain the required supply voltage of each components and parts on the mainboard by LDO and DC/DC device.Required supply voltage has 3.3V, 1.5V, 2.5V.
3.3V voltage:
3.3V by converting by DC/DC through filtered 5V power supply.The load current of this DC/DC is 6A, and input voltage is 3.0-6V, and output voltage is 3.3V, and precision is ± 3%, and efficient can reach (variation with load current changes) more than 90%.As shown in figure 12.
2.5V voltage:
2.5V power supply is to be converted by LDO by the 3.3V power supply.The load current of this LDO is 0-3A, and input voltage is 2.5-7.0V, fixedly 2.5V DC output, and precision is ± 1.5% (under the room temperature).As shown in figure 13.
1.5V voltage:
1.5 power supply is converted through LDO by 3.3V.This LDO load current range is 0-1.5A, and to have only the pressure drop of 110mV, precision under the load current of 1.5A be ± 1.5% (under the room temperature), as shown in figure 14.
The power supply sequential:
The electrifying timing sequence of motherboard power supply mainly requires to design according to the electrifying timing sequence of MPC5200B chip, and the desired electrifying timing sequence of MPC5200B is seen shown in Figure 15.
Electrifying timing sequence to several voltages when MPC5200B powers on does not have specific (special) requirements, and more topmost requirement is to power supply for it, and the supply voltage of chip core e300 at any time all can not be than I/O Buffer and the high 0.4V of DDR Buffer; In addition, for avoiding opening the ESD protecting clamper resistance of chip internal, the rise time of MPC5200B power supply should be greater than 1 microsecond.
In the display module design,, extended out the LCD graphic display control IC of a automotive grade for this this plate because MPC5200 does not have lcd controller.This product is applicable to that the advanced person's navigation in the automobile application shows with video.32 graphics controller, floating-point operation can realize the exact figure graphics processing function, this device comprises one 32,33MHz pci interface, and 70MBps is provided message transmission rate.This controller is integrated external memory interface, but off-line connects the SDRAM storer.This controller has the Video Capture function, can store the digital of digital video data in DVD and other graphic memory.This controller provides the support of 6 levels, the video input function of a simultaneously integrated multiple geometry engines and enhancing.This device is supported traditional functions such as XGA (1,024 * 768 pixel), 4 stacked adding (overlay), a left side/right picture demonstration, peripheral rolling, double buffer and transparent demonstration.6 layers show 4 different color palettes of support, and each palette provides 256 looks.All layers all provide the indirect color of direct colour of 24 or 16 bit resolutions or 8 bit resolutions.The power supply ratings of this controller is 1.8V, 500mA and 3.3V, 100mA.This graphics controller adopts 0.18 μ m technology manufacturing, and 256 pin BGA are provided encapsulation.
The graphics controller circuit principle: this controller adopts the PCI multiplex bus directly to be connected with the pci bus interface of CPU, and 32 bit data bus are wide, and communication speed is 33M.Video is output as the digital rgb pattern, and according to the interface requirement of connecing liquid crystal display, the digital rgb output mode adopts RGB 6:6:6 signal combination pattern.This sheet has been expanded 32M high speed SDRAM outward simultaneously, reaches as high as the access speed of 10ns.As shown in figure 16.
On SDRAM video memory circuit design, graphics controller has a special SDRAM control interface, in order to control SDRAM and FDRAM (Fast Page Mode DRAM, quick page or leaf switch mode dynamic RAM, the DRAM of improvement version) device, the monolithic sdram size of support can reach 256M (can support two).The SDRAM full name is a synchronous DRAM.SDRAM locks together with RAM CPU by an identical clock, make RAM and CPU can share a clock period, with identical speed synchronization work, can improve 50% with EDO internal memory (output of Extended Data Out growth data, the SIMM memory bar of P486 computer 72 lines) phase specific rate.
This mainboard has been selected 2 SDRAM chip for use, and its framework is 4 (banks) * 2M * 16 (16M bytes), and every bank row address number is 12, and the column address number is 9, is total to the 32MB storage space, can satisfy the service requirement of embedded OS.
The SDRAM chip is divided into 4 bank, and the address location of 2M is arranged in each bank, and each address location contains 16 storage unit, and the capacity of chip piece is 128M bit.In order to make full use of the width of graphics controller 32 position datawires, this mainboard is formed the data bus of 32 bit wides with two SDRAM, makes the data that each read-write cycle can 4 bytes of access.Compare with the Flash storer, the control signal of SDRAM is more, and its connecting circuit is relative complex also.The memory block of two SDRAM compositions and the catenation principle block diagram of processor are as shown in figure 17.
On the LVDS interface circuit design, the graphics controller that this plate uses is supported the TFT display mode, and the signal of controller output has RGB digital signal, pixel clock (PCLK), (HSYNC) (VSYNC) under this display mode.This product adopts 10.4 cun LVDS (Low Voltage Differential Signaling, low-voltage differential signal) interface screen, to improve the quality that shows output signal.Because graphics controller can not directly be connected with LVDS interface liquid crystal display, must add driving circuit by between, the output parallel signal of graphics controller is converted to the LVDS signal and offers liquid crystal display.
This plate is selected automotive grade LVDS chip for driving for use, and temperature can be worked in 125 ℃ at-40 ℃.Can support display resolutions such as VGA, SVGA, XGA, input clock is 20～65MHz, and data bandwidth can reach 170Mbps, and power supply is single 3.3V power supply.The theory diagram of LVDS chip for driving as shown in figure 18.
Owing to be easy to capture FPGA configuration bit stream, and duplicate, therefore, the FPGA design is difficult to take precautions against design and steals.(IP) compares with lift intellectual property, may extract IP hardly from bit stream, but but can clone whole design from FPGA.In order to protect configuration bit stream, the FPGA that has can encrypt bit stream now.Yet, come need increase step in process of production the key among the FPGA is programmed for the FPGA of encryption configuration bit stream for not possessing embedded bit stream cryptographic means, therefore improved cost.For high volume applications, the cost performance of companion chip safe in utilization can be higher.Adopt the safe companion chip of safe storage (encryption chip) as FPGA, before Hash calculation result's coupling in FPGA and safe storage, the design among this scheme forbidding FPGA, therefore, even captured the configuration data bit stream, design also is safe.Adopt the DS28E011 line interface chip of MAXIM company, therefore, this solution only needs a FPGA I/O pin.Safe storage need adopt pull-up resistor and 1 line I/O pin, and the connecting circuit principle as shown in figure 19.
The Freescale company technical grade 32 bit processor MPC5200B that select for use in a kind of preferred implementation of the present invention are as the core of this hardware system, and all other hardware circuit is all around it and work.MPC5200B is integrated high performance kernel e300 based on MPC603e series, this kernel adopts the superscale framework, high primary frequency can reach 400MHz (environment temperature is-40 ℃ to 85 ℃), processing power with 760MIPS, during full speed running, the power consumption of kernel only is 1W, and the power of X86 series CPU module is usually more than 5W, and the power consumption of the III CPU module of running quickly of same processing power surpasses 12W especially.Simultaneously, MPC5200B is a universal cpu that aims at the commercial Application design, and life cycle can guarantee that more than 20 years contrast ARM9 series CPU is the life cycle in 5 years nearly, has remarkable advantages.
The concrete model that chip that embodiment of the present invention can adopt and components and parts model include, but are not limited in the above-mentioned preferred implementation record and select for use can realize that other company of identical or identity function or other model chip and components and parts are replaced and also should belong to protection scope of the present invention.The above only is a preferred implementation of the present invention; should be pointed out that for those skilled in the art, under the prerequisite that does not break away from the principle of the invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (10)
1. man-machine interaction unit device, it is characterized in that: comprise central processing unit, the central processing unit minimum systematic module, memory module, display module, the MVB bus interface circuit, the central processing unit minimum systematic module comprises power module, clock module, reseting module and JTAG/COP interface circuit, central processing unit and memory module, the central processing unit minimum systematic module links to each other, central processing unit is by external bus expansion MVB bus interface circuit, communicate by MVB bus and vehicle central control module, display module comprises graphic display control, central processing unit links to each other with display by graphic display control, and described central processing unit adopts the technical grade processor of Freescale company.
2. a kind of man-machine interaction unit device according to claim 1, it is characterized in that: described graphic display control directly is connected with the pci bus interface of central processing unit by the PCI multiplex bus, and graphic display control is by extending out the video memory of high speed SDRAM as graphic display control.
3. a kind of man-machine interaction unit device according to claim 2 is characterized in that: described display module comprises the LVDS interface circuit, and described graphic display control links to each other with LVDS interface liquid crystal display by the LVDS interface circuit.
4. according to claim 1,2, the described a kind of man-machine interaction unit device of arbitrary claim in 3, it is characterized in that: described man-machine interaction unit device comprises FPGA module and encryption chip, encryption chip and FPGA module constitute encrypting module, the FPGA module links to each other with central processing unit, the FPGA module links to each other with a data lines of unibus encryption chip by an I/O interface, man-machine interaction unit device works on power, central processing unit sends the forcible authentication signal to the FPGA module, FPGA module controls encryption chip carries out computations, reading encrypted result of calculation, cryptographic calculation results contrast with FPGA module self, whether decision disposes FPGA modular design data, thus the operation of application program in the control central processing unit.
5. a kind of man-machine interaction unit device according to claim 4 is characterized in that: described central processing unit is by FPGA module and keyboard circuit, and the Flash storer links to each other with watchdog circuit.
6. according to the described a kind of man-machine interaction unit device of arbitrary claim in the claim 1,2,3,5, it is characterized in that: described Freescale company technical grade processor is 32 bit processor MPC5200B based on the e300 kernel, described kernel is the superscale framework, high primary frequency low-power consumption kernel.
7. a kind of man-machine interaction unit device according to claim 6 is characterized in that: described central processing unit links to each other with digital temperature sensor, real-time clock and audio decoding circuit by the I2C bus interface.
8. a kind of man-machine interaction unit device according to claim 7 is characterized in that: described central processing unit links to each other with IC-card with touch-screen by the spi bus interface.
9. a kind of man-machine interaction unit device according to claim 8, it is characterized in that: as data-carrier store, and to select dominant frequency for use be that two 64M byte DDR SDRAM of 133MHz are as internal memory to the Nor Flash that described central processing unit extends out the 32M byte as the Nor Flash of program storage and 32M byte.
10. a kind of man-machine interaction unit device according to claim 9, it is characterized in that: described reseting module comprises watchdog circuit, central processing unit links to each other with the FPGA module, the FPGA module links to each other with the input end of watchdog circuit, central processing unit is exported feeding-dog signal by the FPGA module to watchdog circuit, and watchdog circuit resets for central processing unit provides.
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| CN 201010160166 CN101853051A (en) | 2010-04-30 | 2010-04-30 | Man-machine interaction unit device |
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| CN102231058A (en) * | 2011-04-19 | 2011-11-02 | 铁道部运输局 | Man-machine interface board for rail transit vehicle brake electrical system |
| CN103389438A (en) * | 2013-07-30 | 2013-11-13 | 天津七一二通信广播有限公司 | Welding detection system and welding detection method for circuit board with CPU |
| CN103795275A (en) * | 2012-11-01 | 2014-05-14 | 南车青岛四方机车车辆股份有限公司 | Apparatus for providing high-quality power supply for track traffic man-machine interaction system |
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| CN107767488A (en) * | 2017-09-13 | 2018-03-06 | 陕西千山航空电子有限责任公司 | A kind of data storage cell and storage method based on LVDS buses |
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Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101165674A (en) * | 2006-10-16 | 2008-04-23 | 深圳市亿科科技发展有限公司 | Palm computer for automobile failure diagnosis |
-
2010
- 2010-04-30 CN CN 201010160166 patent/CN101853051A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101165674A (en) * | 2006-10-16 | 2008-04-23 | 深圳市亿科科技发展有限公司 | Palm computer for automobile failure diagnosis |
Non-Patent Citations (1)
| Title |
|---|
| 《电子产品世界》 20050531 飞思卡尔半导体技术园地 采用MPC5200 实现高速视频探测的车内应用 正文部分第1页第1-2段 1-10 , 第9期 2 * |
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| CN102231058A (en) * | 2011-04-19 | 2011-11-02 | 铁道部运输局 | Man-machine interface board for rail transit vehicle brake electrical system |
| CN103795275A (en) * | 2012-11-01 | 2014-05-14 | 南车青岛四方机车车辆股份有限公司 | Apparatus for providing high-quality power supply for track traffic man-machine interaction system |
| CN103795275B (en) * | 2012-11-01 | 2016-05-25 | 中车青岛四方机车车辆股份有限公司 | A kind ofly provide the device of high quality power supply for track traffic man-machine interactive system |
| CN103389438A (en) * | 2013-07-30 | 2013-11-13 | 天津七一二通信广播有限公司 | Welding detection system and welding detection method for circuit board with CPU |
| CN103389438B (en) * | 2013-07-30 | 2015-11-25 | 天津七一二通信广播有限公司 | A kind of for the welding detection system with cpu pcb and method |
| CN104539345A (en) * | 2014-12-26 | 2015-04-22 | 深圳航天东方红海特卫星有限公司 | Microsatellite multifunctional data testing system |
| CN107409046A (en) * | 2015-04-14 | 2017-11-28 | 西门子公司 | Apparatus and method for generating key in programmable hardware module |
| CN105652742A (en) * | 2015-12-29 | 2016-06-08 | 哈尔滨恒誉名翔科技有限公司 | Man-machine interaction device |
| CN107767488A (en) * | 2017-09-13 | 2018-03-06 | 陕西千山航空电子有限责任公司 | A kind of data storage cell and storage method based on LVDS buses |
| CN108268002A (en) * | 2017-12-14 | 2018-07-10 | 深圳市显控科技股份有限公司 | A kind of combination HMI and the all-in-one machine and communication means of PLC functions |
| CN108162981A (en) * | 2017-12-29 | 2018-06-15 | 山东渔翁信息技术股份有限公司 | A kind of unmanned apparatus control method, apparatus and system |
| CN110196625A (en) * | 2018-02-27 | 2019-09-03 | 维谛技术有限公司 | A kind of USB reset circuit |
| CN110196625B (en) * | 2018-02-27 | 2024-04-05 | 维谛技术有限公司 | USB reset circuit |
| CN111555949A (en) * | 2019-10-30 | 2020-08-18 | 江苏云涌电子科技股份有限公司 | VPN application development platform and monitoring method thereof |
| CN112286099A (en) * | 2020-10-29 | 2021-01-29 | 中国航发南方工业有限公司 | Digital electronic control device of gas turbine generator set |
| CN112305966A (en) * | 2020-10-29 | 2021-02-02 | 中国航发南方工业有限公司 | Digital electronic control device of gas turbine generator set |
| CN113190494A (en) * | 2020-12-25 | 2021-07-30 | 成都卓源网络科技有限公司 | Circuit structure of key distribution system |
| CN115102620A (en) * | 2022-07-11 | 2022-09-23 | 天津市英贝特航天科技有限公司 | Optical fiber 1553B bus communication device |
| CN115102620B (en) * | 2022-07-11 | 2024-05-28 | 天津市英贝特航天科技有限公司 | Optical fiber 1553B bus communication device |
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