CN112289881B - GaInP/GaAs/Ge/Si four-junction solar cell and preparation method thereof - Google Patents

GaInP/GaAs/Ge/Si four-junction solar cell and preparation method thereof Download PDF

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CN112289881B
CN112289881B CN202011164078.9A CN202011164078A CN112289881B CN 112289881 B CN112289881 B CN 112289881B CN 202011164078 A CN202011164078 A CN 202011164078A CN 112289881 B CN112289881 B CN 112289881B
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gaas
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CN112289881A (en
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王智勇
黄瑞
兰天
代京京
李颖
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Beijing University of Technology
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Abstract

The invention discloses a GaInP/GaAs/Ge/Si four-junction solar cell and a preparation method thereof, wherein the solar cell sequentially comprises the following components: the solar cell comprises a Si substrate, a Si sub-cell, a Ge film, a Ge sub-cell, a GaAs sub-cell and a GaInP sub-cell; a GaAs or InGaAs contact layer and an upper electrode are arranged on the partial upper surface of the top AlInP or GaInP third window layer of the GaInP sub-battery, and a lower electrode is arranged at the bottom of the Ge film; the preparation method comprises the steps of preparation of a Si substrate and epitaxial growth of a Si sub-battery, bonding and film stripping of a Ge film, preparation of the Ge sub-battery, preparation of a GaAs sub-battery, preparation of a GaInP sub-battery, preparation of a contact layer, debonding, and etching SiO2And photoetching to prepare upper and lower electrodes. The invention mainly utilizes the wafer bonding and ion implantation modes to reduce the preparation cost of the device and improve the photoelectric conversion efficiency of the solar chip.

Description

GaInP/GaAs/Ge/Si four-junction solar cell and preparation method thereof
Technical Field
The invention relates to the technical field of compound semiconductor solar cells, in particular to a GaInP/GaAs/Ge/Si four-junction solar cell and a preparation method thereof.
Background
In the 21 st century, the unprecedented speed of human civilization is advancing; in the process of the continuous development of economic society, people also bear the pressure of the shortage of fossil fuels. In order to solve the dilemma, an inexhaustible green energy source needs to be found, and solar energy can meet the needs of people. The solar power generation can realize large-scale application in the long term, and can solve the application in some special fields in the short term; it is reported that photovoltaic power generation will account for 5-20% of the total world power generation by 2030. Solar power generation has many advantages, such as safe and reliable, noiseless, pollution-free, need not to consume fuel, need not mechanical rotating parts, fault rate is low etc.. With the advantages, solar power generation technology is researched by countries around the world.
The development of solar technologies such as crystalline silicon solar cells, amorphous silicon thin-film solar cells, III-V group compound semiconductor solar cells, and the like is becoming mature. Among them, the development of GaAs-based III-V compound semiconductor multijunction solar cell technology is particularly spotlighted. Currently, the highest conversion efficiency of III-V compound semiconductor multijunction solar cells has exceeded 30%; the operating efficiency of the multi-junction solar cell is over 40% under the condition of high-power light-gathering module light gathering. Therefore, the III-V group compound semiconductor multi-junction solar cell has wide development and application prospects by virtue of technical breakthrough in the photovoltaic field.
In order to obtain as high a photoelectric conversion efficiency as possible. The cascade battery can meet the basic requirements of material lattice matching, reasonable forbidden band width combination, top and bottom sub-battery current matching and the like. The ternary alloy GaInP is an ideal top battery material matched with GaAs lattice, the forbidden band width Eg is between 1.85eV and 1.9eV, and the theoretical conversion efficiency of the GaInP/GaAs cascade battery formed by the ternary alloy GaInP and GaAs is 34% at most. The three-junction GaInP/GaAs/Ge cascade battery is mainly characterized in that a pn junction in the same direction as two junctions of GaInP/GaAs is formed on a Ge substrate through processes such as ion injection and the like, and then a GaAs and GaInP battery is grown by using an MOCVD technology, so that a structure with three sub-batteries connected in series is formed. The spectrum coverage of the Ge substrate layer is wide, and the maximum short-circuit current can reach more than 2 times of the highest conversion efficiency.
Because of the restriction of the series connection of the three-junction batteries, the absorption efficiency of the traditional three-junction GaInP/GaAs/Ge cascade battery is not high; in addition, the Ge substrate is expensive and the overall cost is high, which are not favorable for the wide-range application of the solar cell.
Disclosure of Invention
Aiming at the problems in the prior art, the invention provides a GaInP/GaAs/Ge/Si four-junction solar cell and a preparation method thereof.
The invention discloses a GaInP/GaAs/Ge/Si four-junction solar cell, which sequentially comprises the following components: the solar cell comprises a Si substrate, a Si sub-cell, a Ge film, a Ge sub-cell, a GaAs sub-cell and a GaInP sub-cell;
the Si sub-battery is formed by epitaxially growing an N-type Si film on a P-type Si substrate, and a layer of SiO is deposited on the N-type Si film2Laminated on SiO2Bonding the Ge film on the layer;
a GaAs or InGaAs contact layer is arranged on the partial upper surface of the third AlInP or GaInP window layer on the top of the GaInP sub-cell, and an upper electrode is arranged on the GaAs or InGaAs contact layer;
and photoetching part of the lower surface of the Si substrate to the position of the Ge film, and arranging a lower electrode at the bottom of the Ge film.
As a further improvement of the invention, the Ge sub-battery sequentially comprises a Ge buffer layer, a Ge first back field layer, a Ge first base region, a Ge first emitter region, an AlGaAs first window layer, a barrier layer of AlGaAs or Al (Ga) InP, a doping layer of InGaAs (P) and a barrier layer of AlGaAs or Al (Ga) InP from bottom to top.
As a further improvement of the invention, Al (Ga) InP represents AlxGa1-xInP, wherein x is more than or equal to 0 and less than or equal to 1; AlGaAs represents AlxGa1-xAs, wherein x is in the range of 0-1.
As a further improvement of the invention, the GaAs sub-battery sequentially comprises a GaAs second back field layer, a GaAs second base region, a GaAs emitter region, an AlInP or GaInP second window layer and a GaAs second tunneling layer from bottom to top.
As a further improvement of the invention, the GaInP sub-cell sequentially comprises a third back field layer of GaInP, a third base region of GaInP, a third emitter region of GaInP, and a third window layer of AlInP or GaInP from bottom to top.
The invention also discloses a preparation method of the GaInP/GaAs/Ge/Si four-junction solar cell, which comprises the following steps:
step 1, preparation of a Si substrate and epitaxial growth of a Si sub-battery;
step 2, bonding of the Ge film and film stripping;
step 3, preparing the Ge sub-battery;
step 4, preparing a GaAs sub-battery;
step 5, preparing a GaInP sub-battery;
step 6, preparing a contact layer;
step 7, bonding is released;
step 8, etching SiO2A layer;
step 9, photoetching;
and step 10, preparing upper and lower electrodes.
As a further improvement of the invention, the method specifically comprises the following steps:
step 1, preparation of a Si substrate and epitaxial growth of a Si sub-battery:
taking two Si pieces, carrying out thermal oxidation on the surfaces of the two Si pieces, and oxidizing a layer of SiO with the thickness of about 300nm2A layer; then, ion implantation is carried out on one of the oxidized Si wafers, the implantation depth is about 1-3 μm, and the implantation dosage is at least 5 x 1016/cm2(ii) a Bonding the oxidation surfaces of the two Si sheets, keeping the applied bonding force at 100-500 kg for at least 30min, then placing the bonded Si sheets in an annealing furnace for annealing, introducing nitrogen in the annealing process, wherein the annealing temperature is 500-900 ℃, and the annealing time is at least 30 min; after the annealing is finished, naturally cooling the temperature in the cavity to room temperature, and taking out the Si sheet pair; stripping the Si wafer subjected to ion implantation, and polishing the top Si surface after the stripping is finished; after polishing, epitaxially growing a layer of Si film, namely a Si sub-battery, by adopting a metal organic chemical vapor deposition method or a molecular beam epitaxy method;
step 2, bonding of the Ge film and film peeling:
depositing a layer of SiO on the Si epitaxial layer prepared in step 12Layer of SiO2The layer thickness is about 50-500 nm, and then the chemical mechanical polishing process is adopted to deposit SiO2Polishing the layer to reduce the surface roughness to below 0.5 nm; taking a Ge sheet, and carrying out ion implantation on the Ge sheet, wherein the implantation depth is 1-3 mum, the dose of implantation is at least 4 x 1016/cm2(ii) a Then compounding the Ge sheet and the SiO on the Si composite wafer2Bonding the surfaces, wherein the applied bonding force is 100 kg-500 kg, and keeping for at least 30 min; after bonding, placing the wafer in an annealing furnace, and continuously introducing nitrogen in the annealing process, wherein the annealing temperature is 400-500 ℃ and the annealing time is 1 h; at the same time, the Ge wafer will lift off at the implant depth, thereby forming SiO2A layer of Ge film is reserved on the surface of the substrate, and the residual Ge sheet can be recycled;
step 3, preparing the Ge sub-battery:
epitaxially growing a Ge buffer layer on the Ge film, and growing a first Ge back field layer, a first Ge base region, a first Ge emitter region, an AlGaAs first window layer and a first tunneling layer on the surface of the Ge buffer layer, wherein the first tunneling layer sequentially comprises a barrier layer of AlGaAs or Al (Ga) InP, a doping layer of InGaAs (P) and a barrier layer of AlGaAs or Al (Ga) InP from bottom to top;
step 4, preparing the GaAs sub-battery:
sequentially growing a GaAs second back field layer, a GaAs second base region, a GaAs emitter region and AlInP on the first tunneling layer2Or GaInP2A second window layer and a GaAs second tunneling layer;
step 5, preparing a GaInP sub-battery:
a third back field layer of GaInP, a third base region of GaInP, a third emitter region of GaInP and AlInP are sequentially grown on the second tunneling layer of GaAs2Or GaInP2A third window layer;
step 6, preparing a contact layer:
in the AlInP2Or GaInP2Preparing a GaAs or InGaAs contact layer on the third window;
and 7, bonding resolution:
using wafer bonding equipment to remove SiO in step 12The bonding layer is subjected to bonding release; the Si sheet obtained by bonding can be recycled;
step 8, etching SiO2Layer (b):
a very thin SiO layer remains on the bottom Si surface2Layer of SiO etched by HF acid2A layer, the bottom Si layer remaining;
step 9, photoetching:
spin-coating a layer of photoresist on the Si wafer at the bottom of the epitaxial wafer, and photoetching the position which is not coated with the photoresist until the photoetching depth reaches the position of the Ge layer at the bottom; after photoetching, removing redundant photoresist on the bottom Si wafer;
step 10, preparing an upper electrode and a lower electrode:
cleaning the upper surface and the lower surface of the epitaxial wafer to remove pollutants on the upper surface and the lower surface; after cleaning, placing the epitaxial wafer in a drying oven to dry water vapor on the surface of the epitaxial wafer; and preparing electrodes on the upper surface and the lower surface after drying.
As a further improvement of the invention, in the step 1, the substrate Si is P type, the epitaxial layer Si is N type, the epitaxial thickness is 200-500 nm, and the doping concentration is 2 multiplied by 1017cm-3～2×1018cm-3。
As a further improvement of the invention, when ion implantation is carried out on the Si wafer, the implanted ions are implanted in a manner of implanting only hydrogen ions or co-implanting hydrogen ions and helium ions, and the total dose of implanted ions is at least 5 x 1016/cm2。
As a further improvement of the invention, when ion implantation is carried out on the Ge wafer, the implanted ions are hydrogen ions, and the dose of the implanted ions is at least 5 multiplied by 1016/cm2。
Compared with the prior art, the invention has the beneficial effects that:
1. the invention adopts the modes of ion implantation and wafer bonding to form the SiO2A layer of Ge film is bonded on the layer, so that the utilization rate of Ge can be improved, and the cost of the solar cell chip is reduced;
2. in the structure of the invention, the absorption wavelength of Si is 400-1100 nm, and SiO is2The layer has high light transmittance, so that the Si sub-battery can improve the absorption capacity of the chip and increase the photoelectric conversion efficiency of the chip.
Drawings
Fig. 1 to 10 are structural diagrams corresponding to the preparation process of a GaInP/GaAs/Ge/Si four-junction solar cell in embodiment 1 of the present invention;
fig. 11 is a schematic structural view of a solar cell chip in embodiment 2 of the present invention;
FIG. 12 is a diagram illustrating the chip structure in step 7 according to embodiment 3 of the present invention;
FIG. 13 is a flow chart of a method of fabricating a GaInP/GaAs/Ge/Si four-junction solar cell of the present invention.
In the figure:
10. a Si substrate layer; 101. a bottom Si sheet; 102. an intermediate SiO2 layer; 103. a top Si wafer; 104. a Si sub-cell;
201. a bonded Ge film;
30. a Ge sub-battery; 301. a Ge buffer layer; 302. a Ge first back field layer; 303. a Ge first base region; 304. a Ge first emission region; 305. an AlGaAs first window layer; 306. a barrier layer of AlGaAs or Al (Ga) InP; 307. a doped layer of InGaAs (P); 308. a barrier layer of AlGaAs or Al (Ga) InP;
40. a GaAs sub-cell; 401. a GaAs second back field layer; 402. a GaAs second base region; 403. a GaAs emission region; 404. an AlInP or GaInP second window layer; 405. a GaAs second tunneling layer;
50. a GaInP sub-cell; 501. a third back field layer of GaInP; 502. a GaInP third base region; 503. a GaInP third emission region; 504. a third window layer of AlInP or GaInP;
601. a GaAs or InGaAs contact layer; 602. an upper electrode; 603. and a lower electrode.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention.
The invention is described in further detail below with reference to the attached drawing figures:
as shown in fig. 1 to 10, the invention provides a GaInP/GaAs/Ge/Si four-junction solar cell, which sequentially comprises: a Si substrate 10, a Si sub-cell 104, a Ge film 201, a Ge sub-cell 30, a GaAs sub-cell 40, and a GaInP sub-cell 50; wherein the content of the first and second substances,
the Si substrate 10 of the invention is a P-type Si substrate, the Si sub-battery 104 is an N-type Si film epitaxially grown on the P-type Si substrate, and a layer of SiO is deposited on the N-type Si film2Laminated on SiO2Bonding a Ge film 201 on the layer;
the Ge sub-battery 30 of the invention comprises a Ge buffer layer 301, a Ge first back-field layer 302, a Ge first base region 303, a Ge first emitting region 304, an AlGaAs first window layer 305, a barrier layer 306 of AlGaAs or al (ga) InP, a doping layer 307 of ingaas (p) and a barrier layer 308 of AlGaAs or al (ga) InP in sequence from bottom to top; wherein Al (Ga) InP represents AlxGa1- xInP, wherein x is more than or equal to 0 and less than or equal to 1; AlGaAs represents AlxGa1-xAs, where x is In the range 0. ltoreq. x.ltoreq.1, and (In) GaAs denotes InxGa1-xAs, wherein x is in the range of 0-1.
The GaAs sub-cell 40 sequentially comprises a GaAs second back field layer 401, a GaAs second base region 402, a GaAs emitter region 403, an AlInP or GaInP second window layer 404 and a GaAs second tunneling layer 405 from bottom to top;
the GaInP sub-cell 50 of the invention comprises a third back field layer 501 of GaInP, a third base region 502 of GaInP, a third emitting region 503 of GaInP, and a third window layer 504 of AlInP or GaInP in sequence from bottom to top;
the invention is provided with a GaAs or InGaAs contact layer 601 on the partial upper surface of the third AlInP or GaInP window layer 504 on the top of the GaInP sub-cell, and an upper electrode 602 is arranged on the GaAs or InGaAs contact layer 601; and photoetching part of the lower surface of the Si substrate to the position of the Ge film, and arranging a lower electrode 603 at the bottom of the Ge film.
As shown in fig. 13, the present invention provides a method for manufacturing a GaInP/GaAs/Ge/Si four-junction solar cell, including:
step 1, preparation of a Si substrate and epitaxial growth of a Si sub-battery;
step 2, bonding of the Ge film and film stripping;
step 3, preparing the Ge sub-battery;
step 4, preparing a GaAs sub-battery;
step 5, preparing a GaInP sub-battery;
step 6, preparing a contact layer;
step 7, bonding is released;
step 8, etching SiO2A layer;
step 9, photoetching;
and step 10, preparing upper and lower electrodes.
The invention provides a preparation method of a GaInP/GaAs/Ge/Si four-junction solar cell, which specifically comprises the following steps:
step 1, preparation of a Si substrate and epitaxial growth of a Si sub-battery:
taking two Si pieces, carrying out thermal oxidation on the surfaces of the two Si pieces, and oxidizing a layer of SiO with the thickness of about 300nm2A layer; then, ion implantation is carried out on one of the oxidized Si wafers, the implantation depth is about 1-3 μm, and the implantation dosage is at least 5 x 1016/cm2(ii) a Bonding the oxidation surfaces of the two Si sheets, keeping the applied bonding force at 100-500 kg for at least 30min, then placing the bonded Si sheets in an annealing furnace for annealing, introducing nitrogen in the annealing process, wherein the annealing temperature is 500-900 ℃, and the annealing time is at least 30 min; after the annealing is finished, naturally cooling the temperature in the cavity to room temperature, and taking out the Si sheet pair; stripping the Si wafer subjected to ion implantation, and polishing the top Si surface after the stripping is finished; after polishing, epitaxially growing a layer of Si film, namely a Si sub-battery, by adopting a metal organic chemical vapor deposition method or a molecular beam epitaxy method to form a structure shown in figure 1;
step 2, bonding of the Ge film and film peeling:
depositing a layer of SiO on the Si epitaxial layer prepared in step 12Layer of SiO2The layer thickness is about 50-500 nm, and then the chemical mechanical polishing process is adopted to deposit SiO2Polishing the layer to reduce the surface roughness to below 0.5 nm; taking a Ge sheet, and carrying out ion implantation on the Ge sheet to the implantation depth1-3 μm, and the implantation dose is at least 4 × 1016/cm2(ii) a Then compounding the Ge sheet and the SiO on the Si composite wafer2Bonding the surfaces, wherein the applied bonding force is 100 kg-500 kg, and keeping for at least 30 min; after bonding, placing the wafer in an annealing furnace, and continuously introducing nitrogen in the annealing process, wherein the annealing temperature is 400-500 ℃ and the annealing time is 1 h; at the same time, the Ge wafer will lift off at the implant depth, thereby forming SiO2A layer of Ge film is reserved on the surface of the substrate, and the residual Ge sheet can be recycled to finally form the structure shown in figure 2;
step 3, preparing the Ge sub-battery:
epitaxially growing a Ge buffer layer on the Ge film, growing a Ge first back field layer, a Ge first base region, a Ge first emitter region, an AlGaAs first window layer and a first tunneling layer on the surface of the Ge buffer layer, wherein the first tunneling layer sequentially comprises a barrier layer of AlGaAs or al (ga) InP, a doping layer of ingaas (p) and a barrier layer of AlGaAs or al (ga) InP from bottom to top, and the formed structure is as shown in fig. 3;
step 4, preparing the GaAs sub-battery:
sequentially growing a GaAs second back field layer, a GaAs second base region, a GaAs emitter region and AlInP on the first tunneling layer2Or GaInP2The second window layer and the GaAs second tunneling layer form a structure as shown in FIG. 4;
step 5, preparing a GaInP sub-battery:
sequentially growing a third back field layer of GaInP, a third base region of GaInP, a third emitter region of GaInP and AlInP on the second tunneling layer of GaAs2Or GaInP2A third window layer, the structure of which is shown in fig. 5;
step 6, preparing a contact layer:
in AlInP2Or GaInP2Preparing a GaAs or InGaAs contact layer on the third window, wherein the formed structure is shown in FIG. 6;
and 7, bonding resolution:
using wafer bonding equipment to remove SiO in step 12The bonding layer is subjected to bonding release; the Si wafer obtained by the de-bonding can be recycled, and the formed structure is shown in figure 7Shown in the specification;
step 8, etching SiO2Layer (b):
a very thin SiO layer remains on the bottom Si surface2Layer of SiO etched by HF acid2Layer, leaving the bottom Si layer, resulting in the structure shown in fig. 8;
step 9, photoetching:
spin-coating a layer of photoresist on the Si wafer at the bottom of the epitaxial wafer, and photoetching the position which is not coated with the photoresist until the photoetching depth reaches the position of the Ge layer at the bottom; after the photoetching is finished, removing the redundant photoresist on the bottom Si wafer, and forming a structure as shown in FIG. 9;
step 10, preparing an upper electrode and a lower electrode:
cleaning the upper surface and the lower surface of the epitaxial wafer to remove pollutants on the upper surface and the lower surface; after cleaning, placing the epitaxial wafer in a drying oven to dry water vapor on the surface of the epitaxial wafer; after the drying is completed, electrodes are prepared on the upper and lower surfaces, and the formed structure is shown in fig. 10.
Preferably, in the step 1, the substrate Si is P type, the epitaxial layer Si is N type, the epitaxial thickness is 200-500 nm, and the doping concentration is 2 x 1017cm-3～2×1018cm-3；
Preferably, when ion implantation is performed into the Si wafer in step 1, the implanted ions may be hydrogen ions alone or hydrogen ions and helium ions are co-implanted, and the total dose of the implanted ions is at least 5 × 1016/cm2；
Preferably, when ion implantation is performed on the Ge wafer in step 2, the implanted ions are hydrogen ions, and the dose of the implanted ions is at least 5 × 1016/cm2；
Preferably, the Ge buffer layer (301) epitaxially grown in the step 3 has a thickness of 50-400 nm and a doping concentration of at least 2 × 1018cm-3(ii) a The Ge first back field layer (302) has a thickness of 500-1000 nm and a doping concentration of at least 5 × 1017cm-3The doping type is P type; the thickness of the Ge first base region (303) ranges from 4 mu m to 15 mu m, and the doping concentration is at least 1 multiplied by 1017cm-3The doping type is P type; the thickness range of the Ge first emitting region (304) is 100 to300nm, doping concentration of 7 × 1017cm-3～3×1018cm-3The doping type is N type; the thickness of the AlGaAs first window layer (305) is 20-200 nm, and the doping concentration is at least 6 x 1018cm-3The doping type is N type; the thickness of the barrier layer (306) of AlGaAs or Al (Ga) InP in the first tunneling layer is 20-100 nm, and the doping concentration is at least 2 x 1018cm-3The doping type is N type; the thickness of the doped layer (307) of InGaAs (P) is 10-40 nm, and the doping concentration is at least 1 × 1019cm-3The doping type is P type; the AlGaAs or Al (Ga) InP barrier layer (308) has a thickness of 20-100 nm and a doping concentration of at least 2 x 1019cm-3The doping type is P type;
preferably, the thickness of the GaAs second back field layer in the step 4 is 500-1000 nm, and the doping concentration is 1 × 1018cm-3～3×1018cm-3The doping type is P type; the thickness range of the GaAs second base region is 2-10 mu m, and the doping concentration is 1 multiplied by 1017cm-3～6×1017cm-3The doping type is P type; the thickness range of the GaAs emission region is 400-1000 nm, and the doping concentration is 1 multiplied by 1018cm-3～5×1018cm-3The doping type is N type; AlInP2Or GaInP2The second window layer has a thickness of 150-800 nm and a doping concentration of 1 × 1018cm-3～5×1018cm-3The doping type is N type; the thickness range of the GaAs second tunneling layer is 10-100 nm, and the doping concentration is 2 multiplied by 1019cm-3～1×1020cm-3The doping type is P type;
preferably, the thickness of the third back field layer of GaInP in step 5 is 20-100 nm, and the doping concentration is 1 × 1018cm-3～5×1018cm-3The doping type is P type; the thickness range of the GaInP third base region is 500-1000 nm, and the doping concentration is 1 multiplied by 1017cm-3～1×1018cm-3The doping type is P type; the thickness range of the GaInP third emitting region is 200-300 nm, and the doping concentration is 1 multiplied by 1018cm-3～5×1018cm-3The doping type is N type; the thickness range of the third window of the AlInP or GaInP is 20-100 nm, and the doping concentration is 1 multiplied by 1017cm-3～1×1018cm-3And the doping type is N type.
Example 1:
the structure of the solar cell chip prepared in example 1 is shown in fig. 10, and the specific preparation process flow is as follows:
step 1: taking two Si pieces, carrying out thermal oxidation on the surfaces of the two Si pieces, and oxidizing a layer of SiO with the thickness of about 300nm2And (3) a layer. Then, ion implantation is carried out on one of the oxidized Si wafers, the implantation surface is an oxidation layer, the implanted ions are hydrogen ions, the implantation depth is about 3 mu m, and the implantation dosage is 6 multiplied by 1016/cm2. And then bonding the oxidation surfaces of the two Si pieces, keeping the applied bonding force at 200kg for 1 hour, putting the bonded Si pieces in an annealing furnace for annealing, introducing nitrogen in the annealing process, wherein the annealing temperature is 600 ℃, and the annealing time is 30 min. And after the annealing is finished, naturally cooling the temperature in the chamber to room temperature, and taking out the Si sheet pair. The ion-implanted Si wafer is stripped, and after the stripping is completed, the top Si surface is polished. After polishing, a Si film is epitaxially grown by Metal Organic Chemical Vapor Deposition (MOCVD) or Molecular Beam Epitaxy (MBE), wherein the thickness of the Epitaxy is 200nm, and the N-type doping concentration is 5 × 1017cm-3；
Step 2: depositing a layer of SiO on the surface of the Si epitaxial layer2Layer of SiO2The layer thickness is approximately 100nm, and the deposited SiO is then polished by a Chemical Mechanical Polishing process (CMP)2The layer is polished to reduce its surface roughness to below 0.5 nm. Taking a Ge sheet, and carrying out ion implantation on the Ge sheet, wherein the implanted ions are hydrogen ions, the implantation depth is 2 mu m, and the implantation dosage is 4 multiplied by 1016/cm2. Then compounding the Ge sheet and the SiO on the Si composite wafer2The faces were bonded with a bonding force of 200kg applied for 1 hour. After bonding, the wafer is processedPlacing the mixture in an annealing furnace, and continuously introducing nitrogen gas in the annealing process, wherein the annealing temperature is 450 ℃ and the annealing time is 1 h. At the same time, the Ge wafer will lift off at the implant depth, thereby forming SiO2A layer of Ge film is reserved on the surface of the substrate, and the residual Ge sheet can be recycled;
and step 3: a Ge buffer layer is epitaxially grown on a Ge film by adopting a Metal Organic Chemical Vapor Deposition (MOCVD) method or a Molecular Beam Epitaxy (MBE) method, a first Ge back field layer, a first Ge base region, a first Ge emitting region, a first AlGaAs window layer and a first tunneling junction are grown on the surface of the Ge buffer layer, and the first tunneling junction sequentially comprises a barrier layer of AlGaAs, a doping layer of InGaAs and a barrier layer of AlGaAs from bottom to top. Wherein the Ge buffer layer (301) has a thickness of 50nm and a P-type doping concentration of 2 × 1018cm-3(ii) a The Ge first back field layer (302) has a thickness of 500nm and a P-type doping concentration of 5 × 1017cm-3(ii) a The thickness of the Ge first base region (303) is 4 μm, and the N-type doping concentration is 1 × 1017cm-3(ii) a The Ge first emission region (304) has a thickness in the range of 100nm and an N-type doping concentration of 7 × 1017cm-3(ii) a The AlGaAs first window layer (305) has a thickness in the range of 20nm and an N-type doping concentration of 6 x 1018cm-3(ii) a The barrier layer (306) of AlGaAs in the first tunneling layer has a thickness of 20nm and a P-type doping concentration of 2 × 1018cm-3The thickness of the doped layer (307) of InGaAs (P) is 10nm, and the doping concentration is 1 × 1019cm-3The AlGaAs barrier layer (308) has a thickness in the range of 20nm and a P-type doping concentration of 2 x 1019cm-3；
And 4, step 4: sequentially growing a GaAs second back field layer, a GaAs second base region, a GaAs emitter region and GaInP on the first tunneling layer2A second window layer and a GaAs second tunneling layer. Wherein the thickness of the GaAs second back field layer is 500nm, and the P-type doping concentration is 1 × 1018cm-3(ii) a The thickness of the GaAs second base region is 5 μm, and the P-type doping concentration is 2 × 1017cm-3(ii) a The thickness of the GaAs emission region is 400nm, and the N-type doping concentration is 1 × 1018cm-3(ii) a The thickness of the GaInP second window layer is 150nm, and the N typeThe doping concentration is 1 x 1018cm-3(ii) a The thickness of the GaAs second tunneling layer is 50nm, and the P-type doping concentration is 2 multiplied by 1019cm-3；
And 5: and growing a third back field layer of GaInP, a third base region of GaInP, a third emitter region of GaInP and a third window of GaInP on the second tunneling layer of GaAs in sequence. Wherein the thickness of the third back field layer of GaInP is 20nm, and the P-type doping concentration is 1 × 1018cm-3(ii) a The thickness of the GaInP third base region is 500nm, and the P-type doping concentration is 1 multiplied by 1017cm-3(ii) a The thickness of the GaInP third emitting region is 200nm, and the N-type doping concentration is 1 × 1018cm-3(ii) a The thickness of the GaInP third window is 20nm, and the N-type doping concentration is 1 × 1017cm-3；
Step 6: preparing a GaAs contact layer on the GaInP third window, wherein the thickness of the contact layer is 50nm, and the N-type doping concentration is 1 multiplied by 1018cm-3；
And 7: using wafer debonding equipment to remove SiO in the bottom substrate2And the bonding layer is subjected to debonding.
And 8: a very thin SiO layer remains on the bottom Si surface2Layer of SiO etched by HF acid2Layer, the bottom Si layer remains.
And step 9: and spin-coating a layer of photoresist on the Si wafer at the bottom of the epitaxial wafer, and photoetching the position which is not coated with the photoresist until the photoetching depth reaches the position of the Ge layer at the bottom. And after photoetching is finished, removing the redundant photoresist on the bottom Si wafer.
Step 10: and cleaning the upper surface and the lower surface of the epitaxial wafer to remove pollutants on the upper surface and the lower surface. And after cleaning, placing the epitaxial wafer in an oven to dry the water vapor on the surface of the epitaxial wafer. And preparing electrodes on the upper surface and the lower surface after drying. And finally obtaining the silicon-based GaInP/GaAs/Ge/Si four-junction solar cell.
Example 2:
the structure of the solar cell chip prepared in example 2 is shown in fig. 11, and the specific preparation process flow is as follows:
step 1: taking two Si pieces, carrying out thermal oxidation on the surfaces of the two Si pieces, and oxidizing a layer of SiO with the thickness of about 300nm2And (3) a layer. Then, ion implantation is carried out on one of the oxidized Si wafers, the implantation surface is an oxidation layer, the implanted ions are hydrogen ions, the implantation depth is about 3 mu m, and the implantation dosage is 6 multiplied by 1016/cm2. And then bonding the oxidation surfaces of the two Si pieces, keeping the applied bonding force for 1 hour at 300kg, and then placing the bonded Si pieces in an annealing furnace for annealing, wherein nitrogen is introduced during the annealing process, the annealing temperature is 600 ℃, and the annealing time is 30 min. And after the annealing is finished, naturally cooling the temperature in the chamber to room temperature, and taking out the Si sheet pair. The ion-implanted Si wafer is stripped, and after the stripping is completed, the top Si surface is polished. After polishing, a Si film is epitaxially grown by Metal Organic Chemical Vapor Deposition (MOCVD) or Molecular Beam Epitaxy (MBE), wherein the thickness of the Epitaxy is 200nm, and the N-type doping concentration is 5 × 1017cm-3；
Step 2: taking a Ge sheet, and carrying out ion implantation on the Ge sheet, wherein the implanted ions are hydrogen ions, the implantation depth is 2 mu m, and the implantation dosage is 4 multiplied by 1016/cm2. And then bonding the Ge sheet and the epitaxial Si film, wherein the applied bonding force is 200kg, and the bonding time is kept for 1 hour. And after bonding, placing the wafer in an annealing furnace, and continuously introducing nitrogen in the annealing process, wherein the annealing temperature is 450 ℃ and the annealing time is 1 h. At the same time, the Ge wafer will lift off at the implant depth, thereby forming SiO2A layer of Ge film is reserved on the surface of the substrate, and the residual Ge sheet can be recycled;
and step 3: a Ge buffer layer is epitaxially grown on a Ge film by adopting a Metal Organic Chemical Vapor Deposition (MOCVD) method or a Molecular Beam Epitaxy (MBE) method, a first Ge back field layer, a first Ge base region, a first Ge emitting region, a first AlGaAs window layer and a first tunneling junction are grown on the surface of the Ge buffer layer, and the first tunneling junction sequentially comprises a barrier layer of AlGaAs, a doping layer of InGaAs and a barrier layer of AlGaAs from bottom to top. Wherein the Ge buffer layer (301) has a thickness of 80nm and a P-type doping concentration of 2 × 1018cm-3(ii) a Ge first back field layer (302)) Has a thickness of 500nm and a P-type doping concentration of 6 × 1017cm-3(ii) a The thickness of the Ge first base region (303) is 4 μm, and the N-type doping concentration is 1 × 1017cm-3(ii) a The Ge first emission region (304) has a thickness in the range of 100nm and an N-type doping concentration of 7 × 1017cm-3(ii) a The AlGaAs first window layer (305) has a thickness in the range of 20nm and an N-type doping concentration of 6 x 1018cm-3(ii) a The barrier layer (306) of AlGaAs in the first tunneling layer has a thickness of 20nm and a P-type doping concentration of 2 × 1018cm-3The thickness of the doped layer (307) of InGaAs (P) is 10nm, and the doping concentration is 1 × 1019cm-3The AlGaAs barrier layer (308) has a thickness in the range of 20nm and a P-type doping concentration of 2 x 1019cm-3；
And 4, step 4: and growing a GaAs second back field layer, a GaAs second base region, a GaAs emitter region, a GaInP second window layer and a GaAs second tunneling layer on the first tunneling layer in sequence. Wherein the thickness of the GaAs second back field layer is 500nm, and the P-type doping concentration is 1 × 1018cm-3(ii) a The thickness of the GaAs second base region is 5 μm, and the P-type doping concentration is 2 × 1017cm-3(ii) a The thickness of the GaAs emission region is 400nm, and the N-type doping concentration is 1 × 1018cm-3(ii) a The thickness of the GaInP second window layer is 150nm, and the N-type doping concentration is 1 × 1018cm-3(ii) a The thickness of the GaAs second tunneling layer is 50nm, and the P-type doping concentration is 2 multiplied by 1019cm-3；
And 5: and growing a third back field layer of GaInP, a third base region of GaInP, a third emitter region of GaInP and a third window of GaInP on the second tunneling layer of GaAs in sequence. Wherein the thickness of the third back field layer of GaInP is 20nm, and the P-type doping concentration is 1 × 1018cm-3(ii) a The thickness of the GaInP third base region is 500nm, and the P-type doping concentration is 1 multiplied by 1017cm-3(ii) a The thickness of the GaInP third emitting region is 200nm, and the N-type doping concentration is 1 × 1018cm-3；GaInP2The thickness of the third window is 20nm, and the N-type doping concentration is 1 multiplied by 1017cm-3；
Step 6: preparing a GaAs contact layer on the GaInP third window, wherein the thickness of the contact layer is 50nm, and the N type doping concentration isDegree of 1X 1018cm-3；
And 7: using wafer debonding equipment to remove SiO in the bottom substrate2And the bonding layer is subjected to debonding.
And 8: a very thin SiO layer remains on the bottom Si surface2Layer of SiO etched by HF acid2Layer, the bottom Si layer remains.
And step 9: and cleaning the upper surface and the lower surface of the epitaxial wafer to remove pollutants on the upper surface and the lower surface. And after cleaning, placing the epitaxial wafer in an oven to dry the water vapor on the surface of the epitaxial wafer. And preparing electrodes on the upper surface and the lower surface after drying. And finally obtaining the silicon-based GaInP/GaAs/Ge/Si four-junction solar cell.
Example 3
The specific preparation process flow of the solar cell chip prepared in example 3 is as follows:
step 1: taking two Si pieces, carrying out thermal oxidation on the surfaces of the two Si pieces, and oxidizing a layer of SiO with the thickness of about 300nm2And (3) a layer. Then, ion implantation is carried out on one of the oxidized Si wafers, the implantation surface is an oxidation layer, the implanted ions are hydrogen ions and helium ions, the implantation depth is about 2 mu m, and the total implantation dosage is 7 multiplied by 1016/cm2. And then bonding the oxidation surfaces of the two Si pieces, keeping the applied bonding force at 200kg for 1 hour, putting the bonded Si pieces in an annealing furnace for annealing, introducing nitrogen in the annealing process, wherein the annealing temperature is 600 ℃, and the annealing time is 30 min. And after the annealing is finished, naturally cooling the temperature in the chamber to room temperature, and taking out the Si sheet pair. The ion-implanted Si wafer is stripped, and after the stripping is completed, the top Si surface is polished. After polishing, a Si film is epitaxially grown by Metal Organic Chemical Vapor Deposition (MOCVD) or Molecular Beam Epitaxy (MBE), wherein the thickness of the Epitaxy is 200nm, and the N-type doping concentration is 5 × 1017cm-3；
Step 2: depositing a layer of SiO on the surface of Si epitaxy2Layer of SiO2Layer thickness of about 100nm, followed by Chemical mechanical polishing (CMP: Chemical Me)Mechanical polising) on deposited SiO2The layer is polished to reduce its surface roughness to below 0.5 nm. Taking a Ge sheet, and carrying out ion implantation on the Ge sheet, wherein the implanted ions are hydrogen ions, the implantation depth is 2 mu m, and the implantation dosage is 6 multiplied by 1016/cm2. Then compounding the Ge sheet and the SiO on the Si composite wafer2The faces were bonded with a bonding force of 300kg applied for 1 hour. And after bonding, placing the wafer in an annealing furnace, and continuously introducing nitrogen in the annealing process, wherein the annealing temperature is 450 ℃ and the annealing time is 1 h. At the same time, the Ge wafer will lift off at the implant depth, thereby forming SiO2A layer of Ge film is reserved on the surface of the substrate, and the residual Ge sheet can be recycled;
and step 3: a Ge buffer layer is epitaxially grown on a Ge film by adopting a Metal Organic Chemical Vapor Deposition (MOCVD) method or a Molecular Beam Epitaxy (MBE) method, a first Ge back field layer, a first Ge base region, a first Ge emitting region, a first AlGaAs window layer and a first tunneling junction are grown on the surface of the Ge buffer layer, and the first tunneling junction sequentially comprises a barrier layer of AlGaAs, a doping layer of InGaAs and a barrier layer of AlGaAs from bottom to top. Wherein the Ge buffer layer (301) has a thickness of 50nm and a P-type doping concentration of 2 × 1018cm-3(ii) a The Ge first back field layer (302) has a thickness of 500nm and a P-type doping concentration of 5 × 1017cm-3(ii) a The thickness of the Ge first base region (303) is 4 μm, and the N-type doping concentration is 1 × 1017cm-3(ii) a The Ge first emission region (304) has a thickness in the range of 100nm and an N-type doping concentration of 7 × 1017cm-3(ii) a The AlGaAs first window layer (305) has a thickness in the range of 20nm and an N-type doping concentration of 6 x 1018cm-3(ii) a The barrier layer (306) of AlGaAs in the first tunneling layer has a thickness of 20nm and a P-type doping concentration of 2 × 1018cm-3The thickness of the doped layer (307) of InGaAs (P) is 10nm, and the doping concentration is 1 × 1019cm-3The AlGaAs barrier layer (308) has a thickness in the range of 20nm and a P-type doping concentration of 2 x 1019cm-3；
And 4, step 4: sequentially growing a GaAs second back field layer and a GaAs second base region on the first tunneling layerThe GaAs emitting region, the GaInP second window layer and the GaAs second tunneling layer. Wherein the thickness of the GaAs second back field layer is 500nm, and the P-type doping concentration is 1 × 1018cm-3(ii) a The thickness of the GaAs second base region is 5 μm, and the P-type doping concentration is 2 × 1017cm-3(ii) a The thickness of the GaAs emission region is 400nm, and the N-type doping concentration is 1 × 1018cm-3(ii) a The thickness of the GaInP second window layer is 150nm, and the N-type doping concentration is 1 × 1018cm-3(ii) a The thickness of the GaAs second tunneling layer is 50nm, and the P-type doping concentration is 2 multiplied by 1019cm-3；
And 5: and growing a third back field layer of GaInP, a third base region of GaInP, a third emitter region of GaInP and a third window of GaInP on the second tunneling layer of GaAs in sequence. Wherein the thickness of the third back field layer of GaInP is 20nm, and the P-type doping concentration is 1 × 1018cm-3(ii) a The thickness of the GaInP third base region is 500nm, and the P-type doping concentration is 1 multiplied by 1017cm-3(ii) a The thickness of the GaInP third emitting region is 200nm, and the N-type doping concentration is 1 × 1018cm-3(ii) a The thickness of the GaInP third window is 20nm, and the N-type doping concentration is 1 × 1017cm-3；
Step 6: preparing a GaAs contact layer on the GaInP third window, wherein the thickness of the contact layer is 50nm, and the N-type doping concentration is 1 multiplied by 1018cm-3；
And 7: and after the epitaxy is finished, spin-coating a layer of photoresist on the surface and the side surface of the epitaxial wafer. The structure is shown in FIG. 12, and then the middle SiO of the bottom Si composite wafer is etched by HF acid2And (3) a layer. After the etching is finished, removing the photoresist covering the epitaxial wafer;
and 8: and spin-coating a layer of photoresist on the Si wafer at the bottom of the epitaxial wafer, and photoetching the position which is not coated with the photoresist until the photoetching depth reaches the position of the Ge layer at the bottom. And after photoetching is finished, removing the redundant photoresist on the bottom Si wafer.
And step 9: and cleaning the upper surface and the lower surface of the epitaxial wafer to remove pollutants on the upper surface and the lower surface. And after cleaning, placing the epitaxial wafer in an oven to dry the water vapor on the surface of the epitaxial wafer. And preparing electrodes on the upper surface and the lower surface after drying. And finally obtaining the silicon-based GaInP/GaAs/Ge/Si four-junction solar cell.
The above is only a preferred embodiment of the present invention, and is not intended to limit the present invention, and various modifications and changes will occur to those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (8)

1. A GaInP/GaAs/Ge/Si four-junction solar cell is characterized by sequentially comprising from bottom to top: the solar cell comprises a Si substrate, a Si sub-cell, a Ge film, a Ge sub-cell, a GaAs sub-cell and a GaInP sub-cell;
the Si sub-battery is formed by epitaxially growing an N-type Si film on a P-type Si substrate, and a layer of SiO is deposited on the N-type Si film2Laminated on SiO2Bonding the Ge film on the layer;
the GaInP sub-battery sequentially comprises a third back field layer of GaInP, a third base region of GaInP, a third emitter region of GaInP and a third window layer of AlInP or GaInP from bottom to top, wherein a GaAs or InGaAs contact layer is arranged on the upper surface of part of the third window layer of AlInP or GaInP, and an upper electrode is arranged on the GaAs or InGaAs contact layer;
and photoetching part of the lower surface of the Si substrate to the position of the Ge film, and arranging a lower electrode at the bottom of the Ge film.
2. The GaInP/GaAs/Ge/Si quadruple junction solar cell of claim 1, wherein the Ge subcell comprises, in order from bottom to top, a Ge buffer layer, a Ge first back-field layer, a Ge first base region, a Ge first emitter region, an AlGaAs first window layer, a barrier layer of AlGaAs or al (ga) InP, a doped layer of ingaas (p), and a barrier layer of AlGaAs or al (ga) InP; wherein Al (Ga) InP represents AlxGa1-xInP, wherein x is more than or equal to 0 and less than or equal to 1; AlGaAs represents AlxGa1-xAs, wherein x is in the range of 0-1; InGaAs (P) represents a doped layer of InGaAs with a P-type doping.
3. The GaInP/GaAs/Ge/Si four-junction solar cell of claim 1, wherein the GaAs sub-cell includes, in order from bottom to top, a GaAs second back-field layer, a GaAs second base region, a GaAs emitter region, an AlInP or GaInP second window layer, and a GaAs second tunneling layer.
4. The method for manufacturing a GaInP/GaAs/Ge/Si four-junction solar cell according to any one of claims 1 to 3, comprising:
step 1, preparation of a Si substrate and epitaxial growth of a Si sub-battery;
step 2, bonding of the Ge film and film stripping;
step 3, preparing the Ge sub-battery;
step 4, preparing a GaAs sub-battery;
step 5, preparing a GaInP sub-battery;
step 6, preparing a contact layer;
step 7, bonding is released;
step 8, etching SiO2A layer;
step 9, photoetching;
and step 10, preparing upper and lower electrodes.
5. The method of claim 4, wherein the method specifically comprises:
step 1, preparation of a Si substrate and epitaxial growth of a Si sub-battery:
taking two Si pieces, carrying out thermal oxidation on the surfaces of the two Si pieces, and oxidizing a layer of SiO with the thickness of 300nm2A layer; then, ion implantation is carried out on one of the oxidized Si wafers, the implantation depth is 1-3 mu m, and the implantation dosage is at least 5 multiplied by 1016/cm2(ii) a Bonding the oxidation surfaces of the two Si sheets, keeping the applied bonding force at 100-500 kg for at least 30min, then placing the bonded Si sheets in an annealing furnace for annealing, introducing nitrogen in the annealing process, wherein the annealing temperature is 500-900 ℃, and the annealing time is at least 30 min; after the annealing is finished, naturally cooling the temperature in the cavity to room temperature, and taking out the Si sheet pair; the ion-implanted Si wafer is strippedAfter stripping, polishing the top Si surface; after polishing, epitaxially growing a layer of Si film, namely a Si sub-battery, by adopting a metal organic chemical vapor deposition method or a molecular beam epitaxy method;
step 2, bonding of the Ge film and film peeling:
depositing a layer of SiO on the Si epitaxial layer prepared in step 12Layer of SiO2The layer thickness is 50-500 nm, and then the chemical mechanical polishing process is adopted to deposit SiO2Polishing the layer to reduce the surface roughness to below 0.5 nm; taking a Ge sheet, and carrying out ion implantation on the Ge sheet, wherein the implantation depth is 1-3 mu m, and the implantation dosage is at least 4 multiplied by 1016/cm2(ii) a Then compounding the Ge sheet and the SiO on the Si composite wafer2Bonding the surfaces, wherein the applied bonding force is 100 kg-500 kg, and keeping for at least 30 min; after bonding, placing the wafer in an annealing furnace, and continuously introducing nitrogen in the annealing process, wherein the annealing temperature is 400-500 ℃ and the annealing time is 1 h; at the same time, the Ge wafer will lift off at the implant depth, thereby forming SiO2A layer of Ge film is reserved on the surface of the substrate, and the residual Ge sheet can be recycled;
step 3, preparing the Ge sub-battery:
epitaxially growing a Ge buffer layer on the Ge film, and growing a first Ge back field layer, a first Ge base region, a first Ge emitter region, an AlGaAs first window layer and a first tunneling layer on the surface of the Ge buffer layer, wherein the first tunneling layer sequentially comprises a barrier layer of AlGaAs or Al (Ga) InP, a doping layer of InGaAs (P) and a barrier layer of AlGaAs or Al (Ga) InP from bottom to top;
step 4, preparing the GaAs sub-battery:
growing a second GaAs back field layer, a second GaAs base region, a GaAs emitter region, an AlInP or GaInP second window layer and a second GaAs tunneling layer on the first tunneling layer in sequence;
step 5, preparing a GaInP sub-battery:
growing a third back field layer of GaInP, a third base region of GaInP, a third emitter region of GaInP and a third window layer of AlInP or GaInP on the second GaAs tunneling layer in sequence;
step 6, preparing a contact layer:
preparing a GaAs or InGaAs contact layer on the third AlInP or GaInP window;
and 7, bonding resolution:
using wafer bonding equipment to remove SiO in step 12The bonding layer is subjected to bonding release; the Si sheet obtained by bonding can be recycled;
step 8, etching SiO2Layer (b):
a very thin SiO layer remains on the bottom Si surface2Layer of SiO etched by HF acid2A layer, the bottom Si layer remaining;
step 9, photoetching:
spin-coating a layer of photoresist on the Si wafer at the bottom of the epitaxial wafer, and photoetching the position which is not coated with the photoresist until the photoetching depth reaches the position of the Ge layer at the bottom; after photoetching, removing redundant photoresist on the bottom Si wafer;
step 10, preparing an upper electrode and a lower electrode:
cleaning the upper surface and the lower surface of the epitaxial wafer to remove pollutants on the upper surface and the lower surface; after cleaning, placing the epitaxial wafer in a drying oven to dry water vapor on the surface of the epitaxial wafer; and preparing electrodes on the upper surface and the lower surface after drying.
6. The method of claim 5, wherein in step 1, the substrate Si is P-type, the epitaxial layer Si is N-type, the epitaxial thickness is 200-500 nm, and the doping concentration is 2 x 1017cm-3～2×1018 cm-3。
7. The method of claim 5, wherein the Si wafer is implanted with ions by implanting only hydrogen ions or co-implanting hydrogen ions and helium ions, and the total dose of implanted ions is at least 5 x 1016/cm2。
8. The method of claim 5, wherein the method comprises fabricating a GaInP/GaAs/Ge/Si four-junction solar cellWhen ion implantation is carried out in the Ge wafer, the implanted ions are hydrogen ions, and the dose of the implanted ions is at least 5 x 1016/cm2。
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