CN112271209B - Semiconductor device manufacturing method and semiconductor device - Google Patents

Semiconductor device manufacturing method and semiconductor device Download PDF

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CN112271209B
CN112271209B CN202011461968.6A CN202011461968A CN112271209B CN 112271209 B CN112271209 B CN 112271209B CN 202011461968 A CN202011461968 A CN 202011461968A CN 112271209 B CN112271209 B CN 112271209B
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confinement heterojunction
confinement
heterojunction
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CN112271209A (en
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李马惠
师宇晨
张海超
穆瑶
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Shaanxi Yuanjie Semiconductor Technology Co ltd
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Shaanxi Yuanjie Semiconductor Technology Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions

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Abstract

The application relates to a semiconductor device and a preparation method thereof. The preparation method of the semiconductor device comprises the following steps: providing a substrate, and growing a first coating layer on the surface of the substrate; growing a first confinement heterojunction layer on the surface of the first cladding layer away from the substrate; growing an active layer on a surface of the first confinement heterojunction layer away from the first cladding layer; growing a second confinement heterojunction layer on the surface of the active layer away from the first confinement heterojunction layer; the first confinement heterojunction layer has a gradually decreasing forbidden bandwidth and the second confinement heterojunction layer has a gradually increasing forbidden bandwidth along the direction from the first cladding layer to the second confinement heterojunction layer. A difference of forbidden band width gradient is formed between the first limiting heterojunction layer and the second limiting heterojunction layer, and movement of a current carrier in the heterojunction can be accelerated, so that the transit time of the current carrier in the heterojunction is reduced, and the injection efficiency of the current carrier is improved.

Description

Semiconductor device manufacturing method and semiconductor device
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to a method for manufacturing a semiconductor device and a semiconductor device.
Background
In the current information era, emerging technical fields such as cloud computing, artificial intelligence, internet of things and the like show explosive growth and are considered as a technical revolution of human beings again in history. The development of these fields depends on the support of a new generation of high-speed communication network, i.e. a 5G network. The 5G infrastructure market worldwide will be rapidly growing in the year from 2020 to 2024, as shown by the relevant agency data, during which it is expected that it will grow at a composite annual growth rate of 106.4%, and the overall market size will reach $ 2000 billion by 2024.
The 5G service scene puts forward a series of technical requirements of high reliability, large capacity, low time delay and the like for a 5G network, wherein a semiconductor device is a key component of the 5G network. Semiconductor devices may be used to generate, control, receive, convert, amplify signals, perform energy conversions, and the like. However, the semiconductor device prepared by the traditional semiconductor device preparation method has low carrier injection efficiency and cannot meet the market demand.
Disclosure of Invention
In view of the above, it is necessary to provide a method for manufacturing a semiconductor device and a semiconductor device.
In one embodiment, the present application provides a method of manufacturing a semiconductor device, comprising the steps of:
providing a substrate, and growing a first coating layer on the surface of the substrate;
growing a first confinement heterojunction layer on the surface of the first cladding layer away from the substrate;
growing an active layer on a surface of the first confinement heterojunction layer away from the first cladding layer;
growing a second confinement heterojunction layer on the surface of the active layer away from the first confinement heterojunction layer;
the first confinement heterojunction layer has a gradually decreasing forbidden bandwidth and the second confinement heterojunction layer has a gradually increasing forbidden bandwidth along the direction from the first cladding layer to the second confinement heterojunction layer.
In one embodiment, the step of growing a first confinement heterojunction layer on a surface of the first cladding layer remote from the substrate comprises:
sequentially growing a plurality of first sub-confinement heterojunction layers with the band gap gradually reduced on the surface of the first cladding layer far away from the substrate;
wherein a difference in a gradient of forbidden band widths of adjacent first sub-confinement heterojunction layers is 20 to 100 meV.
In one embodiment, the step of growing a second confinement heterojunction layer on a surface of the active layer remote from the first confinement heterojunction layer comprises:
sequentially growing a plurality of second sub-confinement heterojunction layers with gradually-increased forbidden band widths on the surface of the active layer far away from the first confinement heterojunction layer;
wherein a difference in a gradient of forbidden band widths of adjacent second sub-confinement heterojunction layers is 20meV to 100 meV.
In one embodiment, the semiconductor device manufacturing method further includes:
and forming a second cladding layer on the surface of the second confinement heterojunction layer far away from the active layer.
In one embodiment, the semiconductor device manufacturing method further includes:
forming an ohmic contact layer on the surface of the second cladding layer away from the second confinement heterojunction layer;
forming a first metal electrode layer on the surface of the ohmic contact layer far away from the second cladding layer;
and forming a second metal electrode layer on the surface of the substrate far away from the first coating layer.
The present application provides a semiconductor device. The semiconductor device includes a substrate, a first cladding layer, a first confinement heterojunction layer, an active layer, and a second confinement heterojunction layer. The surface of the substrate is provided with the first cladding layer. The first confinement heterojunction layer is disposed on a surface of the first cladding layer away from the substrate. The active layer is arranged on the surface of the first confinement heterojunction layer far away from the first cladding layer. The second confinement heterojunction layer is disposed on a surface of the active layer away from the first confinement heterojunction layer. The first confinement heterojunction layer has a gradually decreasing forbidden bandwidth and the second confinement heterojunction layer has a gradually increasing forbidden bandwidth along the direction from the first cladding layer to the second confinement heterojunction layer.
In one embodiment, the first confinement heterojunction layer includes a plurality of first sub-confinement heterojunction layers. The plurality of first sub-confinement heterojunction layers are sequentially arranged on the surface, far away from the substrate, of the first cladding layer. The difference of the forbidden band widths of the adjacent first sub-confinement heterojunction layers is 20-100 meV. And the forbidden bandwidth of the plurality of first sub-confinement heterojunction layers gradually becomes smaller along the direction from the first cladding layer to the active layer.
In one embodiment, the difference in the gradient of the forbidden band widths of the adjacent first sub-confinement heterojunction layers is 50 meV.
In one embodiment, the number of the first sub-confinement heterojunction layers is [ (E)gc1-Egb）/△Eg1]Get the whole downwards. Wherein E isgc1Is the forbidden band width of the first cladding layer, EgbIs the forbidden band width, Delta E, of the barrier material in the active layerg1The difference of the forbidden band widths of the adjacent first sub-confinement heterojunction layers is determined.
In one embodiment, the semiconductor structure further comprises a second cladding layer. The second cladding layer is arranged on the surface of the second confinement heterojunction layer far away from the active layer. The second confinement heterojunction layer includes a plurality of second sub-confinement heterojunction layers. The second sub-confinement heterojunction layers are sequentially arranged on the surface, far away from the first confinement heterojunction layer, of the active layer. The difference of the forbidden band widths of the adjacent second sub-confinement heterojunction layers is 20-100 meV. And the forbidden bandwidth of the second sub-confinement heterojunction layers is gradually increased along the direction from the active layer to the second cladding layer.
In one embodiment, the difference in the gradient of the forbidden band widths of the adjacent second sub-confinement heterojunction layers is 50 meV.
In one embodiment, the number of the second sub-confinement heterojunction layers is [ (E)gc2-Egb）/△Eg2]Get the whole downwards. Wherein E isgc2Is the forbidden band width of the second cladding layer, EgbIs the forbidden band width, Delta E, of the barrier material in the active layerg2And the difference of the forbidden band widths of the adjacent second sub-confinement heterojunction layers is shown.
In one embodiment, the first confinement heterojunction layer comprises InGaAlAs doped N-type with a doping concentration in the range of 5 × 1017cm-3To 20X 1017cm-3。
In one embodiment, the second confinement heterojunction layer comprises P-type doped InGaAlAs with a doping concentration in the range of 5 × 1017cm-3To 20X 1017cm-3。
In one embodiment, the first confinement heterojunction layer has a thickness in a range of 10nm to 200 nm. The second confinement heterojunction layer has a thickness in a range of 10nm to 200 nm.
In one embodiment, the present application provides a semiconductor device comprising a substrate, a first cladding layer, a first confinement heterojunction layer, an active layer, and a second confinement heterojunction layer. The surface of the substrate is provided with the first cladding layer. The first confinement heterojunction layer is disposed on a surface of the first cladding layer away from the substrate. The active layer is arranged on the surface of the first confinement heterojunction layer far away from the first cladding layer. The second confinement heterojunction layer is disposed on a surface of the active layer away from the first confinement heterojunction layer. The first confinement heterojunction layer has a gradually decreasing forbidden bandwidth and the second confinement heterojunction layer has a gradually increasing forbidden bandwidth along the direction from the first cladding layer to the second confinement heterojunction layer. The thickness of the first confinement heterojunction layer is 100nm, and the doping concentration of the first confinement heterojunction layer is 1.5 × 1018cm-3. The second confinement heterojunction layer has a thickness of 200nm and a doping concentration of 1 × 1018cm-3. The forbidden bandwidth of the first confinement heterojunction layer is gradually reduced by a gradient difference of 100meV, and the forbidden bandwidth of the second confinement heterojunction layer is gradually increased by a gradient difference of 100 meV.
In one embodiment, the present application provides a semiconductor device comprising a substrate, a first cladding layer, a first confinement heterojunction layer, an active layer, and a second confinement heterojunction layer. The surface of the substrate is provided with the first cladding layer. The first confinement heterojunction layer is disposed on a surface of the first cladding layer away from the substrate. The active layer is arranged on the surface of the first confinement heterojunction layer far away from the first cladding layer. The second confinement heterojunction layer is disposed on a surface of the active layer away from the first confinement heterojunction layer. The first confinement heterojunction layer has a gradually decreasing forbidden bandwidth and the second confinement heterojunction layer has a gradually increasing forbidden bandwidth along the direction from the first cladding layer to the second confinement heterojunction layer. The thickness of the first confinement heterojunction layer is 100nm, and the doping concentration of the first confinement heterojunction layer is1.5×1018cm-3. The second confinement heterojunction layer has a thickness of 50nm and a doping concentration of 1 × 1018cm-3. The forbidden bandwidth of the first confinement heterojunction layer is gradually reduced by a gradient difference of 100meV, and the forbidden bandwidth of the second confinement heterojunction layer is gradually increased by a gradient difference of 100 meV.
In one embodiment, the present application provides a semiconductor device comprising a substrate, a first cladding layer, a first confinement heterojunction layer, an active layer, and a second confinement heterojunction layer. The surface of the substrate is provided with the first cladding layer. The first confinement heterojunction layer is disposed on a surface of the first cladding layer away from the substrate. The active layer is arranged on the surface of the first confinement heterojunction layer far away from the first cladding layer. The second confinement heterojunction layer is disposed on a surface of the active layer away from the first confinement heterojunction layer. The first confinement heterojunction layer has a gradually decreasing forbidden bandwidth and the second confinement heterojunction layer has a gradually increasing forbidden bandwidth along the direction from the first cladding layer to the second confinement heterojunction layer. The thickness of the first confinement heterojunction layer is 100nm, and the doping concentration of the first confinement heterojunction layer is 1.5 × 1018cm-3. The second confinement heterojunction layer has a thickness of 50nm and a doping concentration of 1 × 1018cm-3. The forbidden bandwidth of the first confinement heterojunction layer is gradually reduced by a gradient difference of 50meV, and the forbidden bandwidth of the second confinement heterojunction layer is gradually increased by a gradient difference of 50 meV.
In the semiconductor device manufacturing method and the semiconductor device, the first coating layer is arranged on the surface of the substrate and covers the substrate, so that a buffer effect is achieved. The first confinement heterojunction layer and the second confinement heterojunction layer are respectively arranged on two sides of the active layer, namely the active layer is arranged between the first confinement heterojunction layer and the second confinement heterojunction layer. Meanwhile, the forbidden bandwidth of the first confinement heterojunction layer gradually becomes smaller and the forbidden bandwidth of the second confinement heterojunction layer gradually becomes larger along the direction from the first cladding layer to the second confinement heterojunction layer. In this case, a plurality of graded layers having different band gaps are formed by the first confinement heterojunction layer and the second confinement heterojunction layer. Furthermore, a difference in forbidden bandwidth gradient is formed between the first confinement heterojunction layer and the second confinement heterojunction layer, and the movement of carriers in the heterojunction can be accelerated, so that the transit time of the carriers in the heterojunction is reduced, the carrier injection efficiency is improved, and the requirement of high-speed modulation rate of more than 25GHz can be met.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments or the conventional technologies of the present application, the drawings used in the descriptions of the embodiments or the conventional technologies will be briefly introduced below, it is obvious that the drawings in the following descriptions are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a semiconductor device provided in the present application.
Fig. 2 is a schematic structural diagram of a first confinement heterojunction layer provided in the present application.
Fig. 3 is a schematic structural diagram of a second confinement heterojunction layer provided in the present application.
Fig. 4 is a schematic illustration of the thickness of the first cladding layer, the thickness of the first confinement heterojunction layer, and the thickness of the second confinement heterojunction layer provided herein.
Fig. 5 is a schematic diagram of the relationship between different doping and bandwidth of the first cladding layer provided in the present application.
Fig. 6 is a schematic diagram of different thicknesses of the first cladding layer in relation to the bandwidth provided in the present application.
Fig. 7 is a schematic diagram of the relationship between the different thicknesses and the bandwidths of the first confinement heterojunction layer provided in the present application.
Fig. 8 is a schematic diagram of the relationship between the different thicknesses and the bandwidths of the second confinement heterojunction layer provided in the present application.
Fig. 9 is a schematic diagram of the relationship between the different doping concentrations and the bandwidths of the second confinement heterojunction layer provided in the present application.
Fig. 10 is a schematic diagram of a relationship between a gradient of a band gap of a stack of the first confinement heterojunction layer and the second confinement heterojunction layer and a bandwidth provided in the present application.
Description of reference numerals:
the semiconductor device 100, the substrate 10, the first cladding layer 20, the first confinement heterojunction layer 30, the first sub-confinement heterojunction layer 310, the active layer 40, the second confinement heterojunction layer 50, the second sub-confinement heterojunction layer 510, the second cladding layer 60, the ohmic contact layer 70, the first metal electrode layer 810, the second metal electrode layer 820, the high reflection coating layer 910 and the anti-reflection coating layer 920.
Detailed Description
To facilitate an understanding of the present application, the present application will now be described more fully with reference to the accompanying drawings. Embodiments of the present application are set forth in the accompanying drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and/or sections, these elements, components, regions, layers, doping types and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or section from another element, component, region, layer, doping type or section. Thus, a first element, component, region, layer, doping type or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application; for example, the first doping type may be made the second doping type, and similarly, the second doping type may be made the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.
Spatial relational terms, such as "under," "below," "under," "over," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations) and the spatial descriptors used herein interpreted accordingly.
As used herein, the singular forms "a", "an" and "the" may include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises/comprising," "includes" or "including," etc., specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. Also, in this specification, the term "and/or" includes any and all combinations of the associated listed items.
Referring to fig. 1, the present application provides a semiconductor device 100. The semiconductor device 100 includes a substrate 10, a first cladding layer 20, a first confinement heterojunction layer 30, an active layer 40, and a second confinement heterojunction layer 50. The surface of the substrate 10 is provided with the first clad layer 20. The first confinement heterojunction layer 30 is disposed on the surface of the first cladding layer 20 away from the substrate 10. The active layer 40 is disposed on a surface of the first confinement heterojunction layer 30 away from the first cladding layer 20. The second confinement heterojunction layer 50 is disposed on a surface of the active layer 40 away from the first confinement heterojunction layer 30. In a direction from the first cladding layer 20 to the second confinement heterojunction layer 30, the first confinement heterojunction layer 30 has a gradually decreasing forbidden bandwidth, and the second confinement heterojunction layer 50 has a gradually increasing forbidden bandwidth.
In this embodiment, the first cladding layer 20 is disposed on the surface of the substrate 10, and covers the substrate 10 to play a role in buffering. The first confinement heterojunction layer 30 and the second confinement heterojunction layer 50 are respectively disposed on both sides of the active layer 40, i.e., the active layer 40 is disposed between the first confinement heterojunction layer 30 and the second confinement heterojunction layer 50. At this time, a plurality of graded layers having different forbidden band widths are formed by the first confinement heterojunction layer 30 and the second confinement heterojunction layer 50. Furthermore, a difference in forbidden bandwidth gradient is formed between the first confinement heterojunction layer 30 and the second confinement heterojunction layer 50, and the movement of carriers in the heterojunction can be accelerated, so that the transit time of carriers in the heterojunction is reduced, the carrier injection efficiency is improved, and the requirement of a high-speed modulation rate of 25GHZ or more can be met.
Referring to fig. 2, in one embodiment, the first confinement heterojunction layer 30 includes a plurality of first sub-confinement heterojunction layers 310. The first sub-confinement heterojunction layers 310 are sequentially disposed on the surface of the first cladding layer 20 away from the substrate 10. The difference of the forbidden band widths of the adjacent first sub-confinement heterojunction layers 310 is 20 to 100 meV. And the band gap widths of the plurality of first sub-confinement heterojunction layers 310 become gradually smaller in the direction from the first cladding layer 20 to the active layer 40.
In this embodiment, the plurality of first sub-confinement heterojunction layers 310 are sequentially disposed on the surface of the first cladding layer 20 away from the substrate 10, which is understood to mean that the plurality of first sub-confinement heterojunction layers 310 are stacked one by one on the surface of the first cladding layer 20 (the structure shown in fig. 2). And, a difference Δ E between the gaps between the materials of the two adjacent first sub-confinement heterojunction layers 310g1Is 20 to 100 meV. At this time, the plurality of first sub-confinement heterojunction layers 310 are different in band gap width. The first confinement heterojunction layer 30 includes n layers of the first sub-confinement heterojunction layer 310 different in material composition disposed in this order from bottom to top.
Meanwhile, the plurality of first sub-confinement heterojunction layers 310 gradually decrease in energy gap along the direction from the first cladding layer 20 to the active layer 40 (from bottom to top), thereby forming a plurality of graded layers having different energy gaps. At this time, the first confinement heterojunction layer 30 forms a plurality of graded layers with gradually decreasing forbidden band widths, which can accelerate the movement of carriers in the heterojunction, thereby reducing the transit time of the carriers in the heterojunction and improving the carrier injection efficiency.
In one embodiment, the difference in the gradient of the forbidden band widths of the adjacent first sub-confinement heterojunction layers 310 is 50 meV.
In this embodiment, the difference Δ E between the adjacent two first sub-confinement heterojunction layers 310 in the gradient of the forbidden band width between the materialsg1Is 50 meV. At this time, the band gap of the first one of the first sub-confinement heterojunction layers 310 in the first confinement heterojunction layer 30 is 50meV larger than the band gap of the second one of the first sub-confinement heterojunction layers 310 in the direction from the first cladding layer 20 to the active layer 40 (from bottom to top). The second one of the first sub-confinement heterojunction layers 310 has a band-gap width 50meV larger than that of the third one of the first sub-confinement heterojunction layers 310. The third sub-confinement heterojunction layer 310 has a wider forbidden band than the fourth sub-confinement heterojunction layerThe first sub-confinement heterojunction layer 310 has a band gap 50meV greater. In this way, a plurality of graded layers in which the forbidden band width is gradually reduced are formed in the first confinement heterojunction layer 30.
By making the difference Δ E between the forbidden band widths between the materials of two adjacent first sub-confinement heterojunction layers 310g1The first sub confinement heterojunction layers 310 are set to be 50meV, and gradually changing gradient layers with 50meV as intervals are formed among the first sub confinement heterojunction layers 310, so that the movement of carriers in the heterojunction can be accelerated better, the transit time of the carriers in the heterojunction is further reduced, and the carrier injection efficiency is improved.
In one embodiment, the number of the first sub-confinement heterojunction layers 310 is [ (E)gc1-Egb）/△Eg1]Get the whole downwards. Wherein E isgc1Is the forbidden band width, E, of the first cladding layer 20gbThe forbidden band width, Delta E, of the barrier material in the active layer 40g1The difference in the forbidden band widths of the adjacent first sub-confinement heterojunction layers 310 is a gradient.
In this embodiment, the number of the first sub-confinement heterojunction layers 310 in the first confinement heterojunction layer 30 can be selected according to a difference between a forbidden bandwidth of the first cladding layer 20 and a forbidden bandwidth of the barrier material in the active layer 40. At this time, according to [ (E)gc1-Egb）/△Eg1]Get the whole downwardsThe number of the first sub-confinement heterojunction layers 310 is set such that a plurality of the first sub-confinement heterojunction layers 310 are formed between the first cladding layer 20 and the barrier in the active layer 40. Furthermore, the plurality of first sub-confinement heterojunction layers 310 gradually decrease in energy gap, and a plurality of gradually changing layers with gradually decreasing energy gap are formed between the first cladding layer 20 and the potential barrier in the active layer 40, so that the movement of carriers in the heterojunction can be accelerated, the transit time of the carriers in the heterojunction can be reduced, and the carrier injection efficiency can be improved.
Referring to fig. 3, in one embodiment, the semiconductor device 100 further includes a second cladding layer 60. The second cladding layer 60 is disposed on a surface of the second confinement heterojunction layer 50 away from the active layer 40. The second confinement heterojunction layer 50 includes a plurality of second sub-confinement heterojunction layers 510. The second sub-confinement heterojunction layers 510 are sequentially disposed on the surface of the active layer 40 away from the first confinement heterojunction layer 30. The difference of the forbidden band widths of the adjacent second sub-confinement heterojunction layers 510 is 20 to 100 meV. And the forbidden bandwidth of the second sub-confinement heterojunction layers 510 gradually increases along the direction from the active layer 40 to the second cladding layer 60.
In this embodiment, the second cladding layer 60 is disposed on the surface of the second confinement heterojunction layer 50 away from the active layer 40, and covers the second confinement heterojunction layer 50 to play a role in buffering. The plurality of second sub-confinement heterojunction layers 510 are sequentially disposed on the surface of the active layer 40 away from the first confinement heterojunction layer 30, which can be understood as that the plurality of second sub-confinement heterojunction layers 510 are sequentially disposed on the surface of the active layer 40 in a stacked manner (the structure shown in fig. 3). And the difference Δ E between the band gaps between the materials of two adjacent second sub-confinement heterojunction layers 510g2Is 20 to 100 meV. At this time, the plurality of second sub-confinement heterojunction layers 510 have different forbidden bandwidths. The second confinement heterojunction layer 50 includes n layers of the second sub-confinement heterojunction layer 510 having different material compositions, which are sequentially arranged from bottom to top.
Meanwhile, in the direction from the active layer 40 to the second cladding layer 60 (from bottom to top), the energy gap widths of the second sub-confinement heterojunction layers 510 gradually increase, and a plurality of graded layers with different energy gap widths are formed. At this time, the second confinement heterojunction layer 50 forms a plurality of gradient layers with gradually increasing forbidden band widths, so that the movement of carriers in the heterojunction can be accelerated, the transit time of the carriers in the heterojunction is reduced, and the carrier injection efficiency is improved.
A plurality of graded layers with gradually decreasing energy gap widths and a plurality of graded layers with gradually increasing energy gap widths are formed on both sides of the active layer 40 from bottom to top in sequence through the plurality of first sub-confinement heterojunction layers 310 and the plurality of second sub-confinement heterojunction layers 510 on both sides of the active layer 40. At this time, the active layer 40 is confined between the first and second sub-confinement heterojunction layers 310 and 510 to form a plurality of graded layers having different forbidden band widths, so that carriers can rapidly move, the transit time of the carriers can be reduced, and the carrier injection efficiency can be improved.
In one embodiment, the difference in the gradient of the forbidden band widths of the adjacent second sub-confinement heterojunction layers 510 is 50 meV.
In this embodiment, a difference Δ E between the adjacent two second sub-confinement heterojunction layers 510 in the gradient of the forbidden band width between the materialsg2Is 50 meV. At this time, the band gap of the first one of the second sub-confinement heterojunction layers 510 in the second confinement heterojunction layer 50 is smaller than the band gap of the second one of the second sub-confinement heterojunction layers 510 by 50meV in the direction from the active layer 40 to the second cladding layer 60 (from bottom to top). The second one of the second sub-confinement heterojunction layers 510 has a forbidden band width 50meV smaller than that of the third one of the second sub-confinement heterojunction layers 510. The band gap of the third of the second sub-confinement heterojunction layers 510 is 50meV smaller than the band gap of the fourth of the second sub-confinement heterojunction layers 510. By analogy, a plurality of graded layers with gradually increasing forbidden band widths are formed in the second confinement heterojunction layer 50.
By making the difference Δ E between the forbidden band widths between the materials of two adjacent second sub-confinement heterojunction layers 510g2The gradual change layer with 50meV as an interval is formed between the second sub-confinement heterojunction layers 510, so that the movement of carriers in the heterojunction can be accelerated, the transit time of the carriers in the heterojunction is further reduced, and the carrier injection efficiency is improved.
In one embodiment, the number of the second sub-confinement heterojunction layers 510 is [ (E)gc2-Egb）/△Eg2]Get the whole downwards. Wherein E isgc2Is the forbidden band width, E, of the second cladding layer 60gbThe forbidden band width, Delta E, of the barrier material in the active layer 40g2Is a forbidden band adjacent to the second sub-confinement heterojunction layer 510The gradient difference of the width.
In this embodiment, the number of the second sub-confinement heterojunction layers 510 in the second confinement heterojunction layer 50 may be selected according to a difference between a forbidden bandwidth of the second cladding layer 60 and a forbidden bandwidth of the barrier material in the active layer 40. At this time, according to [ (E)gc2-Egb）/△Eg2]Get the whole downwardsThe number of the second sub-confinement heterojunction layers 510 is set such that a plurality of the second sub-confinement heterojunction layers 510 are formed between the second cladding layer 60 and the barrier in the active layer 40. Furthermore, the plurality of second sub-confinement heterojunction layers 510 have gradually increasing forbidden bandwidths, and a plurality of graded layers with gradually increasing forbidden bandwidths are formed between the second cladding layer 60 and the potential barrier in the active layer 40, so that the movement of carriers in the heterojunction can be accelerated, the transit time of the carriers in the heterojunction is reduced, and the carrier injection efficiency is improved.
In one embodiment, Egc1The forbidden band width at 25 ℃ of the material used for the first cladding layer 20, EgbThe forbidden band width at 25 deg.C, Delta E, of the barrier material in the active layer 40g1Is the difference in the gradient of the band gap at 25 c of the adjacent first sub-confinement heterojunction layer 310. Egc2Is the forbidden band width at 25 ℃ of the material used for the second cladding layer 60, EgbThe forbidden band width at 25 deg.C, Delta E, of the barrier material in the active layer 40g2Is the difference in the gradient of the band gap at 25 c of the adjacent second sub-confinement heterojunction layer 510.
In this embodiment, the number of the first sub-confinement heterojunction layers 310 and the number of the second sub-confinement heterojunction layers 510 are calculated by taking a forbidden band width of 25 ℃ as an example. At this time, the band gap E of the barrier material in the active layer 40 at 25 ℃gbIs 1.18 eV. The temperature is not particularly limited in the application, and the forbidden band width can be other degrees centigrade.
In one embodiment, the first confinement heterojunction layer 30 comprises InGaAlAs doped N-type with a doping concentration in the range of 5 × 1017cm-3To 20X 1017cm-3。
In this example, TongThe doping concentration range of the N-type doping in the first confinement heterojunction layer 30 is set to be 5 x 1017cm-3To 20X 1017cm-3The carrier concentration level in the material can be increased, and the scattering and accumulation of carriers at the heterojunction interface are reduced, so that the transit time of the carriers in the first confinement heterojunction layer 30 is reduced, and the carrier injection efficiency is improved.
In one embodiment, the doping concentration of the N-type doping in the first confinement heterojunction layer 30 is Dnsch =1.5 × 1018 cm-3。
In one embodiment, the second confinement heterojunction layer 50 comprises P-doped InGaAlAs with a doping concentration dspsch in the range of 5 × 1017cm-3To 20X 1017cm-3。
In the present embodiment, the doping concentration range of the P-type doping in the second confinement heterojunction layer 50 is set to be 5 × 1017cm-3To 20X 1017cm-3The carrier concentration level in the material can be increased, and the scattering and accumulation of carriers at the heterojunction interface can be reduced, so that the transit time of the carriers in the second confinement heterojunction layer 50 can be reduced, and the carrier injection efficiency can be improved.
In one embodiment, the doping concentration of the P-type doping in the second confinement heterojunction layer 50 is dspsch =10 × 1017 cm-3。
Therefore, by setting the doping concentration and the forbidden bandwidth gradient of the first confinement heterojunction layer 30 and the second confinement heterojunction layer 50 between the potential barrier in the active layer 40 and the first cladding layer 20 and the second cladding layer 60 respectively, the carrier concentration level in the material is increased, and the scattering and accumulation of carriers at the heterojunction interface are reduced, so that the transit time of the carriers in the first confinement heterojunction layer 30 and the second confinement heterojunction layer 50 is reduced, and the carrier injection efficiency is improved.
Referring to fig. 4, in one embodiment, the first confinement heterojunction layer 30 has a thickness ranging from 10nm to 200 nm. The second confinement heterojunction layer 50 has a thickness in the range of 10nm to 200 nm.
In this embodiment, the thickness Tnsch of the first confinement heterojunction layer 30 ranges from 10nm to 200nm, and preferably ranges from 100 nm. The thickness Tpsch of the second confinement heterojunction layer 50 ranges from 10nm to 200nm, preferably 50 nm.
By adjusting the thicknesses of the first confinement heterojunction layer 30 and the second confinement heterojunction layer 50 within the range of 10nm to 200nm, the equivalent refractive index distribution of the active layer 40 can be improved, thereby realizing high-speed modulation with a bandwidth of more than 25G and assisting in the promotion of new 5G infrastructure.
Referring to fig. 1, in one embodiment, the semiconductor device 100 further includes an ohmic contact layer 70, a first metal electrode layer 810, a second metal electrode layer 820, a high-reflection coating layer 910, and an anti-reflection coating layer 920. The ohmic contact layer 70 is disposed on a surface of the second cladding layer 60 remote from the second confinement heterojunction layer 50. The first metal electrode layer 810 is disposed on a surface of the ohmic contact layer 70 away from the second cladding layer 60. The second metal electrode layer 820 is disposed on the surface of the substrate 10 away from the first cladding layer 20.
The substrate 10, the first cladding layer 20, the first confinement heterojunction layer 30, the active layer 40, the second confinement heterojunction layer 50, the second cladding layer 60, the ohmic contact layer 70, the first metal electrode layer 810 and the second metal electrode layer 820 form a base structure (not labeled in the figures), which can be regarded as a whole structure. As shown in FIG. 1, the highly reflective coating 910 is disposed on a first side of the substrate structure (not shown). The anti-reflective coating 920 is disposed on a second side surface of the base structure (not shown). The first side end face and the second side end face are arranged oppositely. As shown in fig. 1, the high reflection coating layer 910 is provided on the left end surface in fig. 1. The antireflection coating 920 is provided on the right end surface in fig. 1.
At this time, the second metal electrode layer 820, the substrate 10, the first cladding layer 20, the first confinement heterojunction layer 30, the active layer 40, the second confinement heterojunction layer 50, the second cladding layer 60, the ohmic contact layer 70, and the first metal electrode layer 810 are disposed between the high reflection coating layer 910 and the anti-reflection coating layer 920.
In one embodiment, the thickness Tn of the first cladding layer 20 is 0.2 μm to 3 μm, preferably 0.4 μm. The doping concentration of the first cladding layer 20 is 5 × 1017 cm-3~20×1017 cm-3. The first cladding layer 20 is made of N-type InP, and the forbidden band width at 25 ℃ is Egc1Is 1.43 eV. The value range of the doping concentration Dn of the N-type doping in the first cladding layer 20 is 5 × 1017 cm-3~20×1017 cm-3Preferably 5X 1017 cm-3. The material of the second cladding layer 60 is P-type InP, and the doping type is P-type doping.
The quantum well material of the active layer 40 is undoped aluminum gallium indium arsenide (InGaAlAs). A band gap E of 25 ℃ of a barrier material in the active layer 40gbThe range of the value is 0.89eV to 1.38 eV. A band gap E of 25 ℃ of a barrier material in the active layer 40gbIs 1.18 eV. The contact layer material of the ohmic contact layer 70 is InGaAs, and the doping type is P-type doping.
In one embodiment, the present application provides a method of manufacturing a semiconductor device, comprising the steps of:
providing a substrate 10, and growing a first cladding layer 20 on the surface of the substrate 10;
growing a first confinement heterojunction layer 30 on the surface of the first cladding layer 20 away from the substrate 10;
growing an active layer 40 on the surface of the first confinement heterojunction layer 30 away from the first cladding layer 20;
growing a second confinement heterojunction layer 50 on the surface of the active layer 40 away from the first confinement heterojunction layer 30;
in a direction from the first cladding layer 20 to the second confinement heterojunction layer 30, the first confinement heterojunction layer 30 has a gradually decreasing forbidden bandwidth, and the second confinement heterojunction layer 50 has a gradually increasing forbidden bandwidth.
In this embodiment, the method for manufacturing a semiconductor device deposits the first cladding layer 20 on the surface of the substrate 10 by Metal-organic Chemical Vapor Deposition (MOCVD). The first confinement heterojunction layer 30, the active layer 40 and the second confinement heterojunction layer 50 are sequentially deposited over the first cladding layer 20. The active layer 40, the first confinement heterojunction layer 30 and the second confinement heterojunction layer 50 are all InGaAlAs, and the material composition thereof depends on the material forbidden bandwidth. The first confinement heterojunction layer 30 and the second confinement heterojunction layer 50 are each composed of a stack of materials having different band gap widths.
The first cladding layer 20 is disposed on the surface of the substrate 10, and covers the substrate 10 to perform a buffering function. The first confinement heterojunction layer 30 and the second confinement heterojunction layer 50 are respectively disposed on both sides of the active layer 40, i.e., the active layer 40 is disposed between the first confinement heterojunction layer 30 and the second confinement heterojunction layer 50. Meanwhile, along the direction from the first cladding layer 20 to the second confinement heterojunction layer 30, the forbidden bandwidth of the first confinement heterojunction layer 30 gradually becomes smaller, and the forbidden bandwidth of the second confinement heterojunction layer 50 gradually becomes larger. At this time, a plurality of graded layers having different forbidden band widths are formed by the first confinement heterojunction layer 30 and the second confinement heterojunction layer 50. Furthermore, a difference in forbidden bandwidth gradient is formed between the first confinement heterojunction layer 30 and the second confinement heterojunction layer 50, and the movement of carriers in the heterojunction can be accelerated, so that the transit time of carriers in the heterojunction is reduced, the carrier injection efficiency is improved, and the requirement of a high-speed modulation rate of 25G or more can be met.
In one embodiment, the semiconductor device manufacturing method further includes:
depositing the first confinement heterojunction layer 30, the active layer 40, the second confinement heterojunction layer 50, the second cladding layer 60, and the ohmic contact layer 70 in sequence over the first cladding layer 20, resulting in a wafer.
In one embodiment, the step of growing a first confinement heterojunction layer 30 on the surface of the first cladding layer 20 remote from the substrate 10 comprises:
a plurality of first sub-confinement heterojunction layers 310 with gradually-reduced forbidden band widths are sequentially grown on the surface of the first cladding layer 20 far away from the substrate 10. Wherein the difference in the forbidden band widths of the adjacent first sub-confinement heterojunction layers 310 is 20 to 100 meV.
In this embodiment, the plurality of first sub-confinement heterojunction layers 310 gradually decrease in energy gap along the direction from the first cladding layer 20 to the active layer 40 (from bottom to top), and thus a plurality of graded layers having different energy gaps are formed. At this time, the first confinement heterojunction layer 30 forms a plurality of graded layers with gradually decreasing forbidden band widths, which can accelerate the movement of carriers in the heterojunction, thereby reducing the transit time of the carriers in the heterojunction and improving the carrier injection efficiency.
In one embodiment, the step of growing a second confinement heterojunction layer 50 on the surface of the active layer 40 remote from the first confinement heterojunction layer 30 comprises:
a plurality of second sub-confinement heterojunction layers 510 with gradually-increased forbidden band widths are sequentially grown on the surface of the active layer 40 away from the first confinement heterojunction layer 30. Wherein the difference in the forbidden band widths of the adjacent second sub-confinement heterojunction layers 510 is 20meV to 100 meV.
In this embodiment, the plurality of second sub-confinement heterojunction layers 510 have a gradually increasing band gap along the direction from the active layer 40 to the second cladding layer 60 (from bottom to top), and further form a plurality of graded layers having different band gaps. At this time, the second confinement heterojunction layer 50 forms a plurality of gradient layers with gradually increasing forbidden band widths, so that the movement of carriers in the heterojunction can be accelerated, the transit time of the carriers in the heterojunction is reduced, and the carrier injection efficiency is improved.
In this case, a plurality of graded layers having a gradually decreasing bandgap and a plurality of graded layers having a gradually increasing bandgap are formed on both sides of the active layer 40 from bottom to top in sequence by the plurality of first sub-confinement heterojunction layers 310 and the plurality of second sub-confinement heterojunction layers 510 on both sides of the active layer 40. At this time, the active layer 40 is confined between the first and second sub-confinement heterojunction layers 310 and 510 to form a plurality of graded layers having different forbidden band widths, so that carriers can rapidly move, the transit time of the carriers can be reduced, and the carrier injection efficiency can be improved.
In one embodiment, the semiconductor device manufacturing method further includes:
and forming a second cladding layer on the surface of the second confinement heterojunction layer far away from the active layer.
The relevant description in this embodiment may refer to the relevant embodiments described above.
In one embodiment, the semiconductor device manufacturing method further includes:
forming an ohmic contact layer on the surface of the second cladding layer away from the second confinement heterojunction layer;
forming a first metal electrode layer on the surface of the ohmic contact layer far away from the second cladding layer;
and forming a second metal electrode layer on the surface of the substrate far away from the first coating layer.
The relevant description in this embodiment may refer to the relevant embodiments described above.
In one embodiment, the semiconductor device manufacturing method further includes:
a waveguide structure (not labeled) is formed over the ohmic contact layer 70 of the wafer. An insulating layer is then formed on the upper surface of the waveguide structure by plasma chemical vapor deposition, and then the insulating layer on the upper surface of the waveguide structure is removed by etching to expose the ohmic contact layer 70. The first metal electrode layer 810 (i.e., a p-metal electrode layer) is then formed over the ohmic contact layer 70 and the insulating layer. Subsequently, the back side of the substrate 10 is plated with the second metal electrode layer 820 (i.e., an n-metal electrode layer). After the wafer is cut, one end face of the wafer is plated with the anti-reflection coating layer 920, and the other end of the wafer is plated with the high-reflection coating layer 910, so that a high-speed chip for communication is obtained.
In one embodiment, the present application provides the following specific 6 embodiments:
example 1: the first clad layer 20 was provided with a thickness Tn =0.2 μm and a doping concentration Dn =5e17 (5 × 10), respectively17）cm-3，Dn=1.5e18（1.5×1018）cm-3，Dn=2e18（2×1018）cm-3Three groups. A band gap E of 25 ℃ of a barrier material in the active layer 40gb=1.18 eV. The thickness Tnsch =100nm of the first confinement heterojunction layer 30. The thickness Tpsch =200nm of the second confinement heterojunction layer 50. The doping concentration of the first confinement heterojunction layer 30, Dnsch =1.5 × 1018cm-3. The doping concentration of the second confinement heterojunction layer 50 dspsch =1e18 (1 × 10)18）cm-3. A difference Δ E in band gap width between stacked materials of the first sub-confinement heterojunction layers 310 in the first confinement heterojunction layer 30g1=100 meV. A difference Δ E in band gap width between stacked materials of the second sub-confinement heterojunction layers 510 in the second confinement heterojunction layer 50g2=100 meV. As shown in fig. 4, when the doping concentration of the first cladding layer 20 is different, the 3dB bandwidths (shown by the horizontal dotted line in fig. 5) of the three layers can meet the requirement of high-speed adjustment bandwidth of 25GHZ or more. The doping concentrations were Dn =5e17 (5 × 10)17）cm-3The 3dB bandwidth has the greatest response strength.
Please refer to fig. 6, example 2: the first clad layer 20 is provided with three groups of thicknesses Tn =0.2 μm, Tn =0.4 μm and Tn =2 μm, and the doping concentration is Dn =5e17 (5 × 10)17）cm-3. A band gap E of 25 ℃ of a barrier material in the active layer 40gb=1.18 eV. The thickness Tnsch =100nm of the first confinement heterojunction layer 30. The thickness Tpsch =200nm of the second confinement heterojunction layer 50. The doping concentration of the first confinement heterojunction layer 30, Dnsch =1.5 × 1018 cm-3. The doping concentration of the second confinement heterojunction layer 50 dspsch =1e18 (1 × 10)18）cm-3. A difference Δ E in band gap width between stacked materials of the first sub-confinement heterojunction layers 310 in the first confinement heterojunction layer 30g1=100 meV. A difference Δ E in band gap width between stacked materials of the second sub-confinement heterojunction layers 510 in the second confinement heterojunction layer 50g2=100 meV. As shown in fig. 6, the difference between the three groups of Tn =0.2 μm, Tn =0.4 μm, and Tn =2 μm is small, and all of the three thicknesses can satisfy the requirement of the high-speed adjustment bandwidth of 25GHZ and above. And the response intensity of the 3dB bandwidth (shown by the lateral dotted line shown in fig. 6) is maximum at Tn =0.4 μm.
Please refer to fig. 7, example 3: the thickness Tn =0.4 μm of the first clad layer 20 was set, and the doping concentration was set to Dn =5e17 (5 × 10)17）cm-3. A band gap E of 25 ℃ of a barrier material in the active layer 40gb=1.18 eV. The thicknesses of the first confinement heterojunction layer 30 are set to Tnsch =10nm, Tnsch =100nm, and Tnsch =200nm, respectively. The doping concentration of the first confinement heterojunction layer 30, Dnsch =1.5e18 (1.5 × 10)18）cm-3. The second confinement heterojunction layer 50 has a thickness Tpsch =200nm and a doping concentration dspsch =1e18 (1 × 10)18）cm-3. A difference Δ E in band gap width between stacked materials of the first sub-confinement heterojunction layers 310 in the first confinement heterojunction layer 30g1=100 meV. A difference Δ E in band gap width between stacked materials of the second sub-confinement heterojunction layers 510 in the second confinement heterojunction layer 50g2=100 meV. As shown in fig. 7, all three thicknesses can satisfy the requirement of high-speed adjustment bandwidth of 25GHZ and above. And, when Tnsch =100nm, the response intensity of the 3dB bandwidth is maximum.
Please refer to fig. 8, example 4: the thickness Tn =0.4 μm of the first clad layer 20 was set, and the doping concentration was set to Dn =5e17 (5 × 10)17）cm-3. A band gap E of 25 ℃ of a barrier material in the active layer 40gb=1.18 eV. The thickness of the first confinement heterojunction layer 30 is set to Tnsch =100 nm. The doping concentration of the first confinement heterojunction layer 30, Dnsch =1.5e18 (1.5 × 10)18）cm-3. The thicknesses of the second confinement heterojunction layer 50 were set to Tpsch =10nm, Tpsch =50nm, Tpsch =200nm, and doping concentration dspsch =1e18 (1 × 10), respectively (i.e., the thickness of the second confinement heterojunction layer is set to be larger than the thickness of the first confinement heterojunction layer)18）cm-3. A plurality of the first sub-confinement hetero-junctions in the first confinement hetero-junction layer 30Difference Δ E in forbidden band width gradient between stacked materials of the junction layer 310g1=100 meV. A difference Δ E in band gap width between stacked materials of the second sub-confinement heterojunction layers 510 in the second confinement heterojunction layer 50g2=100 meV. As shown in fig. 8, the second confinement heterojunction layer 50 has three thicknesses, which can satisfy the requirement of high-speed adjustment bandwidth of 25GHZ and above. Also, at Tpsch =50nm, the 3dB response intensity is maximum.
Please refer to fig. 9, example 5: the thickness Tn =0.4 μm of the first clad layer 20 was set, and the doping concentration was set to Dn =5e17 (5 × 10)17）cm-3. A band gap E of 25 ℃ of a barrier material in the active layer 40gb=1.18 eV. The thickness of the first confinement heterojunction layer 30 is set to Tnsch =100 nm. The doping concentration of the first confinement heterojunction layer 30, Dnsch =1.5e18 (1.5 × 10)18）cm-3. The thickness of the second confinement heterojunction layer 50 is set to Tpsch =50nm, and the doping concentrations are respectively dspsch =5e17 (5 × 10)17）cm-3，Dpsch=1e18（1×1018）cm-3，Dpsch=2e18（2×1018）cm-3. A difference Δ E in band gap width between stacked materials of the first sub-confinement heterojunction layers 310 in the first confinement heterojunction layer 30g1=100 meV. A difference Δ E in band gap width between stacked materials of the second sub-confinement heterojunction layers 510 in the second confinement heterojunction layer 50g2=100 meV. As shown in fig. 9, the second confinement heterojunction layer 50 has three doping concentrations that can satisfy the requirement of high-speed tuning bandwidth of 25GHZ and above. And at dspsch =1e18 (1 × 10)18）cm-3The 3dB bandwidth has the greatest response strength.
Please refer to fig. 10, example 6: the thickness Tn =0.4 μm of the first clad layer 20 was set, and the doping concentration was set to Dn =5e17 (5 × 10)17）cm-3. A band gap E of 25 ℃ of a barrier material in the active layer 40gb=1.18 eV. The thickness of the first confinement heterojunction layer 30 is set to Tnsch =100 nm. The doping concentration of the first confinement heterojunction layer 30, Dnsch =1.5e18 (1.5 × 10)18）cm-3. The thickness of the second confinement heterojunction layer 50 is setTpsch =50nm, doping concentrations of dspsch =1e18 (1 × 10), respectively18）cm-3. The difference in band gap width between the stacked materials of the first sub-confinement heterojunction layers 310 in the first confinement heterojunction layer 30 is Δ Eg1=20meV，ΔEg1=50meV，ΔEg1=100 meV. A difference Δ E in band gap width between stacked materials of the second sub-confinement heterojunction layers 510 in the second confinement heterojunction layer 50g2=20meV，ΔEg2=50meV，ΔEg2=100 meV. As shown in FIG. 10, Δ E in FIG. 10gRepresents Delta Eg1And Δ Eg2Here, it is understood that Δ Eg1=ΔEg2=ΔEg. Difference Delta E of forbidden band width gradient among three laminated materials of 20meV, 50meV and 100meVgCan meet the requirement of high-speed adjustment bandwidth of 25GHz and above. And the 3dB bandwidth reaches the optimum at 50 meV.
Thus, with the above embodiments, it can be seen that: by setting the doping concentration and the gradient difference of the laminated forbidden band width of the first confinement heterojunction layer 30 and the second confinement heterojunction layer 50, the semiconductor device 100 can meet the requirement of realizing a high-speed modulation rate of more than 25 GHz.
In one embodiment, the present application provides an industrial-temperature high-power semiconductor chip including the semiconductor device 100 described in any of the above embodiments. The application provides a work temperature high-power semiconductor chip which is prepared by adopting the preparation method of the semiconductor device in any embodiment. At the moment, the work temperature high-power semiconductor chip can be a chip with a speed of more than 25G, the bandwidth is more than 18GHZ, the requirements of a single channel of more than 50G of the current 5G network forward transmission, data center and data center on the bandwidth are completely met, the localization scheme of the 5G network can be realized for batch production, the national new infrastructure is assisted, and the rapid deployment of the domestic 5G network is promoted.
In one embodiment, the semiconductor device 100 and the semiconductor device manufacturing method in the above embodiments may also be applied to other semiconductor device technologies.
In the description herein, references to the description of "some embodiments," "other embodiments," or the like, mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the application. In this specification, a schematic description of the above terminology may not necessarily refer to the same embodiment or example.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features of the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the claims. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims (10)

1. A method for manufacturing a semiconductor device is characterized by comprising the following steps:
providing a substrate, and growing a first cladding layer on the surface of the substrate, wherein the thickness of the first cladding layer is 0.2-3 μm, and the doping concentration of the first cladding layer is 5 x 1017cm-3To 20X 1017cm -3The first coating layer is made of N-type InP, and the forbidden band width at 25 ℃ is 1.43 eV;
sequentially growing a plurality of first sub-confinement heterojunction layers with gradually-reduced forbidden band widths on the surface of the first cladding layer far away from the substrate, wherein the gradient difference of the forbidden band widths of the adjacent first sub-confinement heterojunction layers is 20 meV-100 meV, the first sub-confinement heterojunction layers comprise N-type doped InGaAlAs, and the doping concentration range of the first sub-confinement heterojunction layers is 5 multiplied by 1017cm-3To 20X 1017cm-3A first confinement formed by the plurality of first sub-confinement heterojunction layersThe thickness range of the heterojunction layer is 10nm to 200 nm;
growing an active layer on the surface of the first sub-confinement heterojunction layer far away from the first cladding layer, wherein the quantum well material of the active layer is undoped aluminum gallium indium arsenide, and the value of the 25 ℃ forbidden band width of the barrier material in the active layer is in the range of 0.89eV to 1.38 eV;
sequentially growing a plurality of second sub-confinement heterojunction layers with the forbidden band widths gradually increased on the surface of the active layer far away from the first sub-confinement heterojunction layer, wherein the gradient difference of the forbidden band widths of the adjacent second sub-confinement heterojunction layers is 20meV to 100meV, the second sub-confinement heterojunction layer comprises P-type doped InGaAlAs, and the doping concentration range of the second sub-confinement heterojunction layer is 5 multiplied by 1017cm-3To 20X 1017cm-3A second confinement heterojunction layer formed by the plurality of second sub-confinement heterojunction layers and having a thickness ranging from 10nm to 200 nm;
forming a second cladding layer on the surface of the second sub-confinement heterojunction layer far away from the active layer, wherein the material of the second cladding layer is P-type InP, and the doping type is P-type doping;
and respectively forming a high-reflection coating layer and an anti-reflection coating layer at two ends of the substrate, the first coating layer, the plurality of first sub-confinement heterojunction layers, the active layer, the plurality of second sub-confinement heterojunction layers and the second coating layer.
2. The semiconductor device manufacturing method according to claim 1, further comprising:
forming an ohmic contact layer on the surface of the second cladding layer away from the second sub-confinement heterojunction layer;
forming a first metal electrode layer on the surface of the ohmic contact layer far away from the second cladding layer;
and forming a second metal electrode layer on the surface of the substrate far away from the first coating layer.
3. A semiconductor device, comprising:
the substrate comprises a substrate, wherein a first coating layer is arranged on the surface of the substrate, the thickness of the first coating layer is 0.2-3 mu m, and the doping concentration of the first coating layer is 5 x 1017cm-3To 20X 1017cm -3The first coating layer is made of N-type InP, and the forbidden band width at 25 ℃ is 1.43 eV;
a plurality of first sub-confinement heterojunction layers sequentially arranged on the surface of the substrate far away from the first cladding layer, wherein the difference of the forbidden bandwidths of the adjacent first sub-confinement heterojunction layers is 20meV to 100meV, and the gap width of the first sub-confinement heterojunction layers gradually decreases along the direction from the first cladding layer to the active layer, the first sub-confinement heterojunction layers comprise N-type doped InGaAlAs, and the doping concentration range of the first sub-confinement heterojunction layers is 5 multiplied by 1017cm-3To 20X 1017cm-3A first confinement heterojunction layer formed by the plurality of first sub-confinement heterojunction layers and having a thickness ranging from 10nm to 200 nm;
the active layer is arranged on the surface, far away from the first cladding layer, of the first sub-confinement heterojunction layer, the quantum well material of the active layer is undoped aluminum gallium indium arsenide, and the value range of the 25 ℃ forbidden band width of the barrier material in the active layer is 0.89eV to 1.38 eV;
a plurality of second sub-confinement heterojunction layers sequentially arranged on the surface of the active layer far away from the first sub-confinement heterojunction layer, wherein the difference of the forbidden bandwidths of the adjacent second sub-confinement heterojunction layers is 20meV to 100meV, the first cladding layer is arranged on the active layer, the forbidden bandwidths of the second sub-confinement heterojunction layers are gradually increased, the second sub-confinement heterojunction layer comprises P-type doped InGaAlAs, and the doping concentration range of the second sub-confinement heterojunction layer is 5 multiplied by 1017cm-3To 20X 1017cm-3A second confinement heterojunction layer formed by the plurality of second sub-confinement heterojunction layers and having a thickness ranging from 10nm to 200 nm;
the second cladding layer is arranged on the surface, far away from the active layer, of the second sub-confinement heterojunction layer, the material of the second cladding layer is P-type InP, and the doping type is P-type doping;
the substrate, the first coating layer, the plurality of first sub-confinement heterojunction layers, the active layer, the plurality of second sub-confinement heterojunction layers and the second coating layer are arranged between the high-reflection coating layer and the anti-reflection coating layer.
4. The semiconductor device according to claim 3, wherein a difference in the gradient of the forbidden band widths of adjacent first sub-confinement heterojunction layers is 50 meV.
5. The semiconductor device according to claim 3, wherein the number of the first sub-confinement heterojunction layer is [ (E)gc1-Egb）/△Eg1]Get the whole downwards；
Wherein E isgc1Is the forbidden band width of the first cladding layer, EgbIs the forbidden band width, Delta E, of the barrier material in the active layerg1The difference of the forbidden band widths of the adjacent first sub-confinement heterojunction layers is determined.
6. The semiconductor device according to claim 3, wherein a difference in the gradient of the forbidden band widths of adjacent second sub-confinement heterojunction layers is 50 meV.
7. The semiconductor device according to claim 3, wherein the number of the second sub-confinement heterojunction layers is [ (E)gc2-Egb）/△Eg2]Get the whole downwards；
Wherein E isgc2Is the forbidden band width of the second cladding layer, EgbIs the forbidden band width, Delta E, of the barrier material in the active layerg2And the difference of the forbidden band widths of the adjacent second sub-confinement heterojunction layers is shown.
8. A semiconductor device, comprising:
the substrate comprises a substrate, wherein a first coating layer is arranged on the surface of the substrate, the thickness of the first coating layer is 0.2-3 mu m, and the doping concentration of the first coating layer is 5 x 1017cm-3To 20X 1017cm -3The first coating layer is made of N-type InP, and the forbidden band width at 25 ℃ is 1.43 eV;
the first confinement heterojunction layer is arranged on the surface, far away from the substrate, of the first cladding layer;
the active layer is arranged on the surface, far away from the first cladding layer, of the first limiting heterojunction layer, the quantum well material of the active layer is undoped aluminum gallium indium arsenide, and the value range of the 25 ℃ forbidden band width of the barrier material in the active layer is 0.89eV to 1.38 eV;
a second confinement heterojunction layer disposed on a surface of the active layer away from the first confinement heterojunction layer;
the energy gap of the first confinement heterojunction layer is gradually reduced, and the energy gap of the second confinement heterojunction layer is gradually increased along the direction from the first cladding layer to the second confinement heterojunction layer;
the first confinement heterojunction layer comprises N-type doped InGaAlAs, the thickness of the first confinement heterojunction layer is 100nm, and the doping concentration of the first confinement heterojunction layer is 1.5 multiplied by 1018cm-3；
The second confinement heterojunction layer comprises P-type doped InGaAlAs, the thickness of the second confinement heterojunction layer is 200nm, and the doping concentration of the second confinement heterojunction layer is 1 × 1018cm-3；
The forbidden bandwidth of the first limiting heterojunction layer is gradually reduced by a gradient difference of 100meV, and the forbidden bandwidth of the second limiting heterojunction layer is gradually increased by a gradient difference of 100 meV;
the second cladding layer is arranged on the surface, far away from the active layer, of the second confinement heterojunction layer, the material of the second cladding layer is P-type InP, and the doping type is P-type doping;
high reflection coating film layer and anti-reflection coating film layer, the substrate first cladding layer first restriction heterojunction layer active layer the second restriction heterojunction layer and the second cladding layer set up in high reflection coating film layer with between the anti-reflection coating film layer.
9. A semiconductor device, comprising:
the substrate comprises a substrate, wherein a first coating layer is arranged on the surface of the substrate, the thickness of the first coating layer is 0.2-3 mu m, and the doping concentration of the first coating layer is 5 x 1017cm-3To 20X 1017cm -3The first coating layer is made of N-type InP, and the forbidden band width at 25 ℃ is 1.43 eV;
the first confinement heterojunction layer is arranged on the surface, far away from the substrate, of the first cladding layer;
the active layer is arranged on the surface, far away from the first cladding layer, of the first limiting heterojunction layer, the quantum well material of the active layer is undoped aluminum gallium indium arsenide, and the value range of the 25 ℃ forbidden band width of the barrier material in the active layer is 0.89eV to 1.38 eV;
a second confinement heterojunction layer disposed on a surface of the active layer away from the first confinement heterojunction layer;
the energy gap of the first confinement heterojunction layer is gradually reduced, and the energy gap of the second confinement heterojunction layer is gradually increased along the direction from the first cladding layer to the second confinement heterojunction layer;
the first confinement heterojunction layer comprises N-type doped InGaAlAs, the thickness of the first confinement heterojunction layer is 100nm, and the doping concentration of the first confinement heterojunction layer is 1.5 multiplied by 1018cm-3；
The second confinement heterojunction layer comprises P-type doped InGaAlAs, the thickness of the second confinement heterojunction layer is 50nm, and the doping concentration of the second confinement heterojunction layer is 1 × 1018cm-3；
The forbidden bandwidth of the first limiting heterojunction layer is gradually reduced by a gradient difference of 100meV, and the forbidden bandwidth of the second limiting heterojunction layer is gradually increased by a gradient difference of 100 meV;
the second cladding layer is arranged on the surface, far away from the active layer, of the second confinement heterojunction layer, the material of the second cladding layer is P-type InP, and the doping type is P-type doping;
high reflection coating film layer and anti-reflection coating film layer, the substrate first cladding layer first restriction heterojunction layer active layer the second restriction heterojunction layer and the second cladding layer set up in high reflection coating film layer with between the anti-reflection coating film layer.
10. A semiconductor device, comprising:
the substrate comprises a substrate, wherein a first coating layer is arranged on the surface of the substrate, the thickness of the first coating layer is 0.2-3 mu m, and the doping concentration of the first coating layer is 5 x 1017cm-3To 20X 1017cm -3The first coating layer is made of N-type InP, and the forbidden band width at 25 ℃ is 1.43 eV;
the first confinement heterojunction layer is arranged on the surface, far away from the substrate, of the first cladding layer;
the active layer is arranged on the surface, far away from the first cladding layer, of the first limiting heterojunction layer, the quantum well material of the active layer is undoped aluminum gallium indium arsenide, and the value range of the 25 ℃ forbidden band width of the barrier material in the active layer is 0.89eV to 1.38 eV;
a second confinement heterojunction layer disposed on a surface of the active layer away from the first confinement heterojunction layer;
the energy gap of the first confinement heterojunction layer is gradually reduced, and the energy gap of the second confinement heterojunction layer is gradually increased along the direction from the first cladding layer to the second confinement heterojunction layer;
the first confinement heterojunction layer comprises N-type doped InGaAlAs, the thickness of the first confinement heterojunction layer is 100nm, and the doping concentration of the first confinement heterojunction layer is 1.5 multiplied by 1018cm-3；
The second confinement heterojunction layer comprises P-type doped InGaAlAsThe thickness of the layer is 50nm, and the doping concentration of the second confinement heterojunction layer is 1 × 1018cm-3；
The forbidden bandwidth of the first limiting heterojunction layer is gradually reduced by a gradient difference of 50meV, and the forbidden bandwidth of the second limiting heterojunction layer is gradually increased by a gradient difference of 50 meV;
the second cladding layer is arranged on the surface, far away from the active layer, of the second confinement heterojunction layer, the material of the second cladding layer is P-type InP, and the doping type is P-type doping;
high reflection coating film layer and anti-reflection coating film layer, the substrate first cladding layer first restriction heterojunction layer active layer the second restriction heterojunction layer and the second cladding layer set up in high reflection coating film layer with between the anti-reflection coating film layer.
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EP0827241A2 (en) * 1996-09-02 1998-03-04 Nec Corporation Semiconductor laser
CN1466252A (en) * 2002-07-02 2004-01-07 中国科学院半导体研究所 Polarization insensitive semiconductor light amplifier and electric absorption modulator two-purpose device
CN101071935A (en) * 2006-05-12 2007-11-14 中国科学院半导体研究所 Method for preparing buried structure AlInGaAs distributed feedback laser

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JP4814525B2 (en) * 2005-01-11 2011-11-16 株式会社日立製作所 Optical semiconductor device

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EP0827241A2 (en) * 1996-09-02 1998-03-04 Nec Corporation Semiconductor laser
CN1466252A (en) * 2002-07-02 2004-01-07 中国科学院半导体研究所 Polarization insensitive semiconductor light amplifier and electric absorption modulator two-purpose device
CN101071935A (en) * 2006-05-12 2007-11-14 中国科学院半导体研究所 Method for preparing buried structure AlInGaAs distributed feedback laser

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