CN112636179A - Quantum well structure, chip processing method, chip and laser - Google Patents

Quantum well structure, chip processing method, chip and laser Download PDF

Info

Publication number
CN112636179A
CN112636179A CN202011606707.9A CN202011606707A CN112636179A CN 112636179 A CN112636179 A CN 112636179A CN 202011606707 A CN202011606707 A CN 202011606707A CN 112636179 A CN112636179 A CN 112636179A
Authority
CN
China
Prior art keywords
quantum well
layer
chip
inalas
well layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202011606707.9A
Other languages
Chinese (zh)
Inventor
杨彦伟
刘宏亮
邹颜
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Core Technology Shenzhen Co ltd
Original Assignee
Core Technology Shenzhen Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Core Technology Shenzhen Co ltd filed Critical Core Technology Shenzhen Co ltd
Priority to CN202011606707.9A priority Critical patent/CN112636179A/en
Publication of CN112636179A publication Critical patent/CN112636179A/en
Priority to EP21913769.2A priority patent/EP4274040A1/en
Priority to JP2023540828A priority patent/JP2024501749A/en
Priority to PCT/CN2021/135908 priority patent/WO2022143028A1/en
Priority to US18/217,106 priority patent/US20230369829A1/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/30—Structure or shape of the active region; Materials used for the active region
    • H01S5/34—Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers
    • H01S5/343—Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers in AIIIBV compounds, e.g. AlGaAs-laser, InP-based laser
    • H01S5/34313—Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers in AIIIBV compounds, e.g. AlGaAs-laser, InP-based laser with a well layer having only As as V-compound, e.g. AlGaAs, InGaAs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/10—Construction or shape of the optical resonator, e.g. extended or external cavity, coupled cavities, bent-guide, varying width, thickness or composition of the active region
    • H01S5/12—Construction or shape of the optical resonator, e.g. extended or external cavity, coupled cavities, bent-guide, varying width, thickness or composition of the active region the resonator having a periodic structure, e.g. in distributed feedback [DFB] lasers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S2304/00—Special growth methods for semiconductor lasers
    • H01S2304/02—MBE

Abstract

The application relates to the technical field of laser in general, and in particular relates to a quantum well structure, a chip processing method, a chip and a laser, wherein the quantum well structure comprises an InAlAs quantum well layer and an InAlGaAs quantum well layer, the InAlAs quantum well layer is provided with a plurality of layers, the thickness of the InAlGaAs quantum well layer is the same as that of the InAlAs quantum well layer, the InAlGaAs quantum well layer is arranged between two adjacent InAlAs quantum well layers, the thickness of the InAlAs quantum well layer is between 0.4nm and 0.6nm, the number of the InAlAs quantum well layers is between 3 and 17, in the scheme, the thickness of the quantum well layer is small, under the condition that the thickness of the quantum well structure is not changed, the ratio of the thickness of the quantum well structure to the thickness of the single-layer quantum well layer is increased, the value of a quantum well limiting parameter gamma is increased, and the chip threshold current is reduced when the quantum well limiting parameter is increased, and the chip transmission rate is improved.

Description

Quantum well structure, chip processing method, chip and laser
Technical Field
The application relates to the technical field of laser generally, and particularly relates to a quantum well structure, a chip processing method, a chip and a laser.
Background
The DFB laser chip structure mainly comprises an N electrode, a multi-layer quantum well epitaxial structure, a Bragg grating layer, a ridge waveguide and a P-type electrode, wherein laser mainly forms ion number reversal under the action of forward current through the multi-layer quantum well structure to form stimulated radiation and generate laser.
The multilayer quantum well structure is the key for generating laser, according to the laser principle, the threshold current of a laser chip is mainly related to the limiting parameter of a quantum well, the larger the limiting parameter of the quantum well is, the smaller the chip threshold current is, and according to the existing quantum well structure and the processing technology, the limiting parameter is smaller, the threshold current of the chip is larger, and the transmission rate of the chip is seriously influenced.
Disclosure of Invention
In this summary, concepts in a simplified form are introduced that are further described in the detailed description. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
In order to solve the technical problem that the transmission rate is low due to the fact that the threshold current of a chip is large, the application mainly aims to provide a quantum well structure, a chip processing method, a chip and a laser.
In order to achieve the purpose of the invention, the following technical scheme is adopted in the application:
a quantum well structure for a DFB laser chip, comprising:
an InAlAs quantum well layer, the InAlAs quantum well layer providing a plurality of layers;
the thickness of the InAlGaAs quantum well layer is the same as that of the InAlGaAs quantum well layer, the InAlGaAs quantum well layer is arranged between every two adjacent InAlGaAs quantum well layers,
wherein the thickness of the InAlAs quantum well layer is between 0.4nm and 0.6nm, and the number of the InAlAs quantum well layers is between 3 and 17.
Further, in some embodiments of the present application, the InAlAs quantum well layer is 0.5nm thick.
Further, in some embodiments of the present application, the number of inalgas quantum well layers is 6, and the number of inalgas quantum well layers is 5.
Further, In some embodiments of the present application, the inalgas quantum well layer contains 53% by mass In, 36% by mass Al, and 11% by mass Ga and As.
A method of chip processing comprising:
processing a buffer layer and a lower gradient layer group in sequence on a substrate;
processing a plurality of quantum well layers by a molecular beam epitaxy process, wherein the thickness of each quantum well layer is 0.4-0.6 nm;
processing an upper gradient layer group;
the capping layer, the etch stop layer, the top layer, the transition layer and the contact layer are processed by a vapor phase epitaxial growth technique.
Further, in some embodiments of the present application, the processing the multi-layer quantum well layer by a molecular beam epitaxy process includes:
the 11 quantum well layers were processed by a molecular beam epitaxy process.
Further, in some embodiments of the present application, each of the quantum well layers described above is 0.5nm thick.
Further, in some embodiments of the present application, the processing the multi-layer quantum well layer by a molecular beam epitaxy process includes:
and alternately processing the InAlAs quantum well layer and the InAlGaAs quantum well layer, wherein the InAlAs quantum well layer is positioned on the outer side.
A chip is processed by the chip processing method.
A laser is provided with the chip.
According to the technical scheme, the quantum well structure, the chip processing method, the chip and the laser have the advantages and positive effects that:
the quantum well limiting parameters are increased, the chip threshold current is reduced, and the chip transmission rate is improved.
The application provides a quantum well structure on the one hand, and the quantum well structure includes InAIAs quantum well layer and InAIGaAs quantum well layer, InAIAs quantum well layer sets up the multilayer, the thickness of InAIGaAs quantum well layer is the same with InAIAs quantum well layer thickness, and adjacent two be provided with between the InAIAs quantum well layer InAIGaAs quantum well layer, wherein, the thickness of InAIAs quantum well layer is between 0.4nm-0.6nm, the quantity of InAIAs quantum well layer is between 3-17.
The expression according to the quantum well confinement parameter Γ is the following formula:
Γ＝(2π2/λ2)(d/dw)(nra 2-nrc 2) In the scheme of the application, the quantum well structure is formed by alternately overlapping quantum well layers made of two materials, the thicknesses of the InAlAs quantum well layer and the InAlGaAs quantum well layer are the same, and dw can be the thickness of the InAlAs quantum well layer or the thickness of the InAlGaAs quantum well layer, and nraIs the refractive index of InAlGaAs material, nrcThe InAlAs quantum well layer and the InAlGaAs quantum well layer are small in thickness, the quantum well limiting parameter gamma is increased, the threshold current of a chip is reduced, and the transmission rate of the chip is improved.
The application also provides a chip processing method, which comprises the steps of processing a buffer layer and a lower gradient layer group in sequence on a substrate, processing a plurality of quantum well layers by a molecular beam epitaxy process, wherein each quantum well layer is 0.4-0.6 nm in thickness, processing an upper gradient layer group, and processing a covering layer, a corrosion stop layer, a top layer, a transition layer and a contact layer by a vapor phase epitaxy growth technology, the scheme combines an MOCVD (metal organic chemical vapor deposition) meteorological epitaxy growth process and an MBE (molecular beam epitaxy) molecular beam epitaxy process, adopts the MBE molecular beam epitaxy process to carry out epitaxial growth on the quantum well layers, adopts the MOCVD meteorological epitaxy growth process to process each epitaxial growth layer except the quantum well layers, controls the thickness of the quantum well layers to be 0.4-0.6 nm by the MBE epitaxy process, reduces the thickness of the quantum well structure relative to the thickness of the existing chip, improves the transmission rate of the chip, and, the threshold current of the chip is reduced, and the transmission rate of the chip is improved.
Another aspect of the present application provides a chip, which is processed by the above processing technology, and has a small threshold current and a large transmission rate.
The application also provides a laser, and the above-mentioned chip is installed to the laser.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention.
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without inventive exercise.
Fig. 1 is a schematic diagram illustrating a quantum well structure according to an example embodiment.
Wherein the reference numerals are as follows:
100-a second lower graded layer; 200-a second upper graded layer; a 300-InAlAs quantum well layer; 400-InAlGaAs quantum well layer.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments obtained by persons of ordinary skill in the art based on the embodiments in the present application are within the scope of the present application without inventive efforts, and therefore, the following detailed description of the embodiments of the present invention provided in the drawings is not intended to limit the scope of the claimed invention but only to represent selected embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The scheme of the application provides a quantum well structure, a chip processing method, a chip and a laser, wherein the quantum well structure comprises an InAlAs quantum well layer 300 and an InAlGaAs quantum well layer 400, the InAlAs quantum well layer 300 is provided with a plurality of layers, the thickness of the InAlGaAs quantum well layer 400 is the same as the thickness of the InAlAs quantum well layer 300, the InAlAs quantum well layer 400 is arranged between every two adjacent InAlAs quantum well layers 300, the thickness of the InAlAs quantum well layer 300 is between 0.4nm and 0.6nm, and the number of the InAlAs quantum well layers 300 is between 3 and 17. The expression according to the quantum well confinement parameter Γ is the following formula: Γ ═ 2 pi2/λ2)(d/dw)(nra 2-nrc 2) In the present application, the quantum well structure is formed by alternately stacking quantum well layers of two materials, namely, an InAlAs quantum well layer 300 and an inalgas quantum well layer 400, and the thicknesses of the InAlAs quantum well layer 300 and the inalgas quantum well layer 400 are the same, so dw may be the thickness of the InAlAs quantum well layer 300 or the thickness of the inalgas quantum well layer 400, and n is the thickness of the entire quantum well structure, and dw is the thickness of the single-layer quantum well structure, and the thickness of the single-layer quantum well structure is the thickness of the single-layer quantum well structureraIs the refractive index of InAlGaAs material, nrcFor the refractive index of InAlAs materials, according to the formula, for example: the number of the InAlAs quantum well layers is 17, the number of the InAlGaAs quantum well layers is 16, and when the thickness of the InAlAs quantum well layer is 0.6, the value of d is 19.8nm, and the ratio of d/dw is 33, so that the thickness of the InAlAs quantum well layer and the thickness of the InAlGaAs quantum well layer are reduced under the condition that the value of d is not changed, the value of d/dw can be increased, the quantum well limiting parameter gamma is increased, the threshold current of a chip is reduced, and the transmission rate of the chip is improved.
The scheme combines an MOCVD meteorological epitaxial growth process and an MBE molecular beam epitaxial process, adopts the MBE molecular beam epitaxial process to carry out epitaxial growth of a quantum well layer, adopts the MOCVD meteorological epitaxial growth process to process each epitaxial growth layer except the quantum well layer, and the chip processing method comprises the steps of processing a buffer layer and a lower gradient layer group in sequence on a substrate, processing a plurality of quantum well layers by a molecular beam epitaxy process, wherein the thickness of each quantum well layer is 0.4nm-0.6nm, processing an upper gradient layer group, the covering layer, the corrosion stop layer, the top layer, the transition layer and the contact layer are processed by a vapor phase epitaxy growth technology, the thickness of the quantum well layer is controlled to be between 0.4nm and 0.6nm by an MBE epitaxy process, the thickness of the quantum well structure is reduced, the transmission rate of a chip is improved, meanwhile, the quantum well limiting parameter gamma is increased, the threshold current of the chip is reduced, and the transmission rate of the chip is improved.
Referring to fig. 1, the quantum well structure is used for a DFB laser chip, and the quantum well structure includes multiple quantum well layers, in the present application, the quantum well structure includes two quantum well layers formed by two materials, namely an InAlAs quantum well layer 300 and an inalgas quantum well layer 400, the InAlAs quantum well layer 300 and the inalgas quantum well layer 400 are alternately arranged, and one layer located outside is the InAlAs quantum well layer 300.
In this embodiment, the thickness of the InAlAs quantum well layer 300 is the same as that of the InAlAs quantum well layer 400, the thickness of the InAlAs quantum well layer 300 is between 0.4nm and 0.6nm, preferably, the thickness of the InAlAs quantum well layer 300 and the thickness of the InAlAs quantum well layer 400 are both 0.5nm, and the number of the InAlAs quantum well layers 300 is between 3 and 17, preferably 6.
The thickness of the quantum well layer is defined As dw, dw can be the thickness of the InAlAs quantum well layer 300 or the thickness of the InAlGaAs quantum well layer 400 As the InAlAs quantum well layer 300 and the InAlGaAs quantum well layer 400 are the same, d is defined As the thickness of the quantum well structure, when the number of the InAlAs quantum well layers 300 is 6, the number of the InAlGaAs quantum well layers 400 is 5, the thickness of the InAlAs quantum well layer 300 is 0.5nm, the thickness of the quantum well structure is 5.5nm, In the InAlGaAs quantum well layer 400, the mass percent of In is 53%, the mass percent of Al is 36%, and the mass percent of Ga and As is 11%.
The expression according to the quantum well confinement parameter Γ is the following formula: Γ ═ 2 pi2/λ2)(d/dw)(nra 2-nrc 2) λ is the lasing wavelength, nraIs the refractive index of InAlGaAs material, nrcThe refractive index of InAlAs material is reduced, the thickness of the quantum well layer is reduced, and the ratio of d/dw is increased under the condition that the thickness of the quantum well structure is not changed, so that the value of gamma is increased, the threshold current of the chip is reduced due to the increase of the quantum well limiting parameter, and the transmission rate of the chip is improved.
With reference to fig. 1, the present embodiment further provides a chip processing method, including:
step 1, processing an InP buffer layer on a substrate;
specifically, a 1 μm InP buffer layer is grown on a substrate by MOCVD vapor phase epitaxy.
Step 2, processing a lower gradient layer group on the InP buffer layer;
specifically, the lower gradient layer group comprises a first lower gradient layer and a second lower gradient layer 100, the thickness of the first lower gradient layer is 50nm, the thickness of the second lower gradient layer 100 is 10nm, the first lower gradient layer is processed on the InP buffer layer through an MOCVD (metal organic chemical vapor deposition) meteorological epitaxial growth process, the second lower gradient layer 100 is processed on the first lower gradient layer through an MBE (molecular beam epitaxy) epitaxy process, and the first lower gradient layer and the second lower gradient layer are both InAlxGaAs.
The second lower gradient layer with a smaller thickness is grown firstly through the MBE process, so that preparation is provided for the subsequent growth of the InAlAs quantum well layer and the InAlGaAs quantum well layer by the MBE, and the phenomenon that Al element is oxidized in the growth process when the InAlAs quantum well layer or the InAlGaAs quantum well layer is directly grown is avoided, so that the device is invalid.
Step 3, processing a plurality of quantum well layers by a molecular beam epitaxy process, wherein the thickness of each quantum well layer is 0.4-0.6 nm;
specifically, 0.5nm thick InAlAs quantum well layer 300 and 0.5nm thick InAlGaAs quantum well layer 400 are grown in a staggered mode through an MBE molecular beam epitaxy process, the InAlAs quantum well layer 300 is processed into 6 layers, the InAlGaAs quantum well layer 400 is processed into 5 layers, and the layer located on the outer side is the InAlAs quantum well layer 300.
Step 4, processing an upper gradient layer group;
specifically, the upper gradient layer group comprises a first upper gradient layer with the thickness of 50nm and a second upper gradient layer 200 with the thickness of 10nm, the second upper gradient layer 200 is processed to the InAlAs quantum well layer 300 positioned on the outer side by adopting an MBE molecular beam epitaxy process, the first upper gradient layer is processed to the second upper gradient layer 200 by adopting an MOCVD (metal organic chemical vapor deposition) meteorological epitaxy growth process, and the first upper gradient layer and the first lower gradient layer are both made of InAlxGaAs.
A first upper gradient layer with a thin layer is generated by an MBE process, so that the phenomenon that an InAlAs quantum well layer or an InAlGaAs quantum well layer is oxidized and failed when the MBE device is transferred to an MOVCD device can be avoided.
Step 5, processing an InP covering layer;
specifically, an InP cladding layer with the thickness of 30nm is processed by adopting an MOCVD (metal organic chemical vapor deposition) meteorological epitaxial growth process.
Step 6, processing a corrosion cut-off layer;
specifically, an InGaAsP corrosion stop layer with the thickness of 15nm is processed by adopting an MOCVD (metal organic chemical vapor deposition) meteorological epitaxial growth process.
Step 7, processing a top layer;
specifically, an MOCVD (metal organic chemical vapor deposition) meteorological epitaxial growth process is adopted to process an InP top layer with the thickness of 16 microns.
Step 8, processing a transition layer;
specifically, an InGaAsP transition layer with the thickness of 10nm is processed by adopting an MOCVD (metal organic chemical vapor deposition) meteorological epitaxial growth process.
Step 9, processing a contact layer;
specifically, an InGaAs contact layer with the thickness of 0.2 mu m is processed and processed by adopting an MOCVD (metal organic chemical vapor deposition) meteorological epitaxial growth process.
And step 10, carrying out back thinning and polishing of the ridge waveguide, and processing of the positive electrode, the negative electrode, the cleavage, end face coating and the like to complete chip processing.
In the scheme, MOCVD is a novel vapor phase epitaxy growth technology developed on the basis of vapor phase epitaxy growth, and takes organic compounds of III group and II group elements, hydrides of V group and VI group elements and the like as crystal growth source materials, and vapor phase epitaxy is carried out on a substrate 100 in a thermal decomposition reaction mode to grow thin layer single crystal materials of various III-V group and II-VI group compound semiconductors and multi-element solid solutions thereof. MBE refers to molecular beam epitaxy processes. In represents chemical element indium, P represents chemical element phosphorus, AI represents chemical element aluminum, Ga represents chemical element gallium, and As represents chemical element arsenic.
In the embodiment, the chip is processed by combining the MOCVD process and the MBE process, the thickness of the quantum well layer is controlled to be 0.4-0.6 nm through the MBE epitaxial process, the thickness of the quantum well structure is reduced, the transmission rate of the chip is improved, meanwhile, the quantum well limiting parameter gamma is increased, the threshold current of the chip is reduced, and the transmission rate of the chip is improved.
The embodiment also provides a chip which is processed by adopting the chip processing method.
The embodiment also provides a laser, and the laser is provided with the chip.
In summary, the present application provides a quantum well structure, a chip processing method, a chip and a laser, the chip processing method employs an MOCVD process and an MBE process, wherein the MBE process processes the quantum well structure, the MOCVD process processes other epitaxial layers except the quantum well structure, the quantum well structure includes quantum well layers formed by two materials, which are an InAlAs quantum well layer 300 and an InAlAs quantum well layer 400, the InAlAs quantum well layer 300 and the InAlAs quantum well layer 400 are alternately arranged, the layer located on the outer side is the InAlAs quantum well layer 300, the InAlAs quantum well layer 300 and the InAlAs quantum well layer 400 have the same thickness, the thickness of the InAlAs quantum well layer 300 is between 0.4nm and 0.6nm, the number of the InAlAs quantum well layer 300 is between 3 nm and 17, and the expression according to a quantum well limiting parameter Γ is the following formula: Γ ═ 2 pi2/λ2)(d/dw)(nra 2-nrc 2) λ is the lasing wavelength, nraIs the refractive index of InAlGaAs material, nrcThe refractive index of InAlAs material is reduced by the thickness of the quantum well layer through MBE process, and under the condition that the thickness of the quantum well structure is not changed, the ratio of the thickness d of the quantum well structure to the thickness dw of the single-layer quantum well layer is increased, so that the value of gamma is increased, the threshold current of the chip is reduced by increasing the quantum well limiting parameter, and the transmission rate of the chip is increased.
It is noted that, in this document, relational terms such as "first" and "second," and the like, may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The foregoing are merely exemplary embodiments of the present invention, which enable those skilled in the art to understand or practice the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the general inventive concept. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (10)

1. A quantum well structure for a DFB laser chip, comprising:
an InAlAs quantum well layer, the InAlAs quantum well layer providing a plurality of layers;
the thickness of the InAlGaAs quantum well layer is the same as that of the InAlGaAs quantum well layer, the InAlGaAs quantum well layer is arranged between every two adjacent InAlGaAs quantum well layers,
wherein the thickness of the InAlAs quantum well layer is between 0.4nm and 0.6nm, and the number of the InAlAs quantum well layers is between 3 and 17.
2. The quantum well structure of claim 1, wherein the InAlAs quantum well layer is 0.5nm thick.
3. The quantum well structure of claim 2, wherein the number of InAlAs quantum well layers is 6 and the number of InAlGaAs quantum well layers is 5.
4. The quantum well structure of claim 1, wherein the inalgas quantum well layer comprises 53% by mass In, 36% by mass Al, and 11% by mass Ga and As together.
5. A method of processing a chip, comprising:
processing a buffer layer and a lower gradient layer group in sequence on a substrate;
processing a plurality of quantum well layers by a molecular beam epitaxy process, wherein the thickness of each quantum well layer is 0.4nm-0.6 nm;
processing an upper gradient layer group;
the capping layer, the etch stop layer, the top layer, the transition layer and the contact layer are processed by a vapor phase epitaxial growth technique.
6. The chip processing method of claim 5, wherein processing the multi-layer quantum well layer by a molecular beam epitaxy process comprises:
the 11 quantum well layers were processed by a molecular beam epitaxy process.
7. The chip processing method of claim 6, wherein each of the quantum well layers is 0.5nm thick.
8. The chip processing method of claim 5, wherein processing the multi-layer quantum well layer by a molecular beam epitaxy process comprises:
and alternately processing the InAlAs quantum well layer and the InAlGaAs quantum well layer, wherein the InAlAs quantum well layer is positioned on the outer side.
9. A chip produced by the chip production method according to any one of claims 5 to 8.
10. A laser provided with the chip according to claim 9.
CN202011606707.9A 2020-12-30 2020-12-30 Quantum well structure, chip processing method, chip and laser Pending CN112636179A (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
CN202011606707.9A CN112636179A (en) 2020-12-30 2020-12-30 Quantum well structure, chip processing method, chip and laser
EP21913769.2A EP4274040A1 (en) 2020-12-30 2021-12-07 Quantum well structure, chip processing method, chip, and laser
JP2023540828A JP2024501749A (en) 2020-12-30 2021-12-07 Quantum well structure, chip processing method and chip
PCT/CN2021/135908 WO2022143028A1 (en) 2020-12-30 2021-12-07 Quantum well structure, chip processing method, chip, and laser
US18/217,106 US20230369829A1 (en) 2020-12-30 2023-06-30 Quantum well structure, chip processing method, chip, and laser

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202011606707.9A CN112636179A (en) 2020-12-30 2020-12-30 Quantum well structure, chip processing method, chip and laser

Publications (1)

Publication Number Publication Date
CN112636179A true CN112636179A (en) 2021-04-09

Family

ID=75286512

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202011606707.9A Pending CN112636179A (en) 2020-12-30 2020-12-30 Quantum well structure, chip processing method, chip and laser

Country Status (1)

Country Link
CN (1) CN112636179A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2022143028A1 (en) * 2020-12-30 2022-07-07 芯思杰技术(深圳)股份有限公司 Quantum well structure, chip processing method, chip, and laser

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2022143028A1 (en) * 2020-12-30 2022-07-07 芯思杰技术(深圳)股份有限公司 Quantum well structure, chip processing method, chip, and laser

Similar Documents

Publication Publication Date Title
US7403552B2 (en) High efficiency intersubband semiconductor lasers
Shi et al. Continuous-wave electrically pumped 1550 nm lasers epitaxially grown on on-axis (001) silicon
US7830938B2 (en) Laser diode
US20050040384A1 (en) Semiconductor light-emitting element and method of manufacturing the same
WO2010149978A1 (en) Light emitting semiconductor device
JPH08172241A (en) Semiconductor light emitting element with algainas multiple quantum well
US9627849B2 (en) Semiconductor light device and manufacturing method for the same
JP2014508420A5 (en)
EP1081817B1 (en) A semiconductor device
CN109103746A (en) Semiconductor laser
WO2006044124A1 (en) Method and structure for deep well structures for long wavelength active regions
US11196233B2 (en) Quantum cascade laser
CN112636179A (en) Quantum well structure, chip processing method, chip and laser
TW200307385A (en) Semiconductor laser
US6859474B1 (en) Long wavelength pseudomorphic InGaNPAsSb type-I and type-II active layers for the gaas material system
CN215185003U (en) Quantum well structure, chip and laser
JPH04350988A (en) Light-emitting element of quantum well structure
WO2022143028A1 (en) Quantum well structure, chip processing method, chip, and laser
Kim et al. Impact of thermal annealing on internal device parameters of GaAs0. 965Bi0. 035/GaAs0. 75P0. 25 quantum well lasers
JPH053367A (en) Semiconductor laser
JPH10256659A (en) Method for increasing semiconductor light emitting element output, multiple quantum well structure and semiconductor light emitting element
US20220149229A1 (en) Mixed strain multi-quantum well superluminescent light emitting diode
CN109524518B (en) Red light LED epitaxial structure and manufacturing method
JP2005260109A (en) Optical semiconductor element
JPH10290049A (en) Semiconductor laser element

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination