CN112217096B - Semiconductor device and method for manufacturing the same - Google Patents
Semiconductor device and method for manufacturing the same Download PDFInfo
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- CN112217096B CN112217096B CN202011461795.8A CN202011461795A CN112217096B CN 112217096 B CN112217096 B CN 112217096B CN 202011461795 A CN202011461795 A CN 202011461795A CN 112217096 B CN112217096 B CN 112217096B
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- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/30—Structure or shape of the active region; Materials used for the active region
- H01S5/34—Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers
- H01S5/343—Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers in AIIIBV compounds, e.g. AlGaAs-laser, InP-based laser
- H01S5/34313—Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers in AIIIBV compounds, e.g. AlGaAs-laser, InP-based laser with a well layer having only As as V-compound, e.g. AlGaAs, InGaAs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
- H01L33/06—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
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- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/30—Structure or shape of the active region; Materials used for the active region
- H01S5/34—Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers
- H01S5/3403—Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers having a strained layer structure in which the strain performs a special function, e.g. general strain effects, strain versus polarisation
- H01S5/3406—Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers having a strained layer structure in which the strain performs a special function, e.g. general strain effects, strain versus polarisation including strain compensation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/30—Structure or shape of the active region; Materials used for the active region
- H01S5/34—Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers
- H01S5/343—Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers in AIIIBV compounds, e.g. AlGaAs-laser, InP-based laser
- H01S5/34346—Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers in AIIIBV compounds, e.g. AlGaAs-laser, InP-based laser characterised by the materials of the barrier layers
- H01S5/34366—Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers in AIIIBV compounds, e.g. AlGaAs-laser, InP-based laser characterised by the materials of the barrier layers based on InGa(Al)AS
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Abstract
The present application relates to a semiconductor device and a method of manufacturing the same. The active layer in the semiconductor device includes a first quantum well layer and a second quantum well layer arranged in a stacking direction, wherein a wavelength difference between the first quantum well layer and the second quantum well layer is 15nm to 30nm, the number of the first quantum well layers is 5 to 9, and the number of the second quantum well layers is 3 to 6. By setting the number of the first quantum well layer, the number of the second quantum well layer and the wavelength difference between the first quantum well layer and the second quantum well layer, the operating bandwidth of the semiconductor device in a high-temperature environment can be improved by the first quantum well layer structure, the operating bandwidth of the semiconductor device in a low-temperature environment can be improved by the second quantum well layer structure, the semiconductor device can be operated at the ambient temperature of-40 ℃ to 85 ℃, the bandwidth can be guaranteed to be more than 18GHz under the refrigeration-free condition, the 25Gbps modulation rate requirement required by a 5G forward transmission system is met, and the high error code behavior of optical communication can be avoided.
Description
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to a semiconductor device and a method for manufacturing the same.
Background
The development of communication systems tends to be advanced towards high performance and low cost schemes, and as the demand for information increases, the china industry and informatization department have issued 5G license plates to relevant mobile telecommunication operators in 2019 june, which means that the commercialization process of the fifth Generation mobile communication technology scheme (5 th Generation Wireless System, abbreviated as 5G) is in the process of being implemented, generally speaking, the cost of basic equipment accounts for more than 30% of the total System cost, the maintenance of the operating environment of the equipment is a necessary condition for ensuring the operating performance of the equipment, and the energy cost generated by the energy consumption generated by the environment maintenance accounts for more than 50% of the total System cost, so how to reduce the equipment cost and the energy consumption becomes the primary solution for commercialization of the 5G communication System.
According to the 5G standard, the most common deployment in the 5G forward part is the connection between an AAU (Active Antenna Unit) and a DU (distributed Unit). The AAU is located on a 5G base station, and the DU is generally located in a nearby access machine room, so the cost control of 5G forwarding mainly falls on the basic equipment cost and the equipment energy consumption cost of the AAU and the DU, and the currently adopted 5G forwarding schemes mainly include the currently mature 6-wave CWDM (Coarse Wavelength Division Multiplexing) scheme and the newly proposed 12-wave MWDM (medium Wavelength Division Multiplexing) scheme. Compared with the two schemes, the 6-wave CWDM communication technical scheme has the advantages that the CWDM communication technical scheme is mature, the power consumption is low, and the defects that the requirements on the characteristic specification and the reliability of the 5G fronthaul optical module are high, while the 12-wave MWDM communication technical scheme has the advantages that the channel capacity is doubled, the requirement on higher speed is supported, the requirements on the characteristic specification and the reliability of the 5G fronthaul optical module are lower, and the defects that the power consumption is high, and the energy consumption cost is increased. Due to the advantages, the solution selection depends on the scenario requirements when the operator lays the system.
In order to ensure the high-speed performance and reliability of the current commercial 25Gbps semiconductor device, a refrigeration device must be arranged at the end of a chip to avoid the phenomenon that the chip generates heat under long-term operation, the performance is reduced due to overheating, and the transmission quality is influenced, the chip belongs to the refrigeration chip, but the refrigeration device can generate extra power consumption to increase the equipment cost and the energy cost, and the requirement of a 5G communication base station on the cost is strict, so that the best cost reduction scheme is to remove the refrigeration device, the 25Gbps semiconductor device must ensure the performance and reliability of the semiconductor device under the variation of the ambient temperature from minus 40 ℃ to 85 ℃ under the scene of no refrigeration, the semiconductor device is called as a non-refrigeration industrial grade 25Gbps semiconductor device, can be directly applied to a domestic 25Gbps semiconductor device, the specification requirement is equivalent to the requirement of the domestic CWDM system, and the semiconductor device is further required to ensure the performance and reliability under the wide temperature range of no refrigeration, adding more development difficulty to the process of producing commercial semiconductor devices in China.
Generally, a 25Gbps semiconductor device generates a scene of great degradation, particularly, when the device is operated for a long time in a high-temperature environment without refrigeration, the heat accumulation generated by long-time energy consumption of the device can cause the gain wavelength of a material formed by a quantum well in an active region to be far away from the target wavelength generated by a grating, and the phenomenon causes the characteristic of the semiconductor device to be poor and even causes high error code behavior that communication cannot be performed; generally speaking, the drift rate of a target wavelength generated by a grating of a semiconductor device along with temperature is 0.1 nm/DEG C, and the drift rate of a material gain wavelength of the semiconductor device along with temperature is 0.5 nm/DEG C, and the asynchronism of the two drift rates causes that the material gain wavelength is at least far away from the target wavelength by a distance of more than 20-25 nm under the variation of the ambient temperature from-40 ℃ to 85 ℃, and the wavelength distance can cause that the Differential Quantum Efficiency (Differential Efficiency) is seriously reduced, which is characterized in that the device has the characteristics of poor operation Bandwidth (Bandwidth), can not meet the requirement of 25Gbps modulation rate required by a 5G fronthaul system, and can not perform high error code behavior of communication.
Disclosure of Invention
In view of the above, it is necessary to provide a semiconductor device and a method for manufacturing the same.
The application provides a semiconductor device, which comprises an active layer, a first limiting layer and a second limiting layer, wherein the first limiting layer and the second limiting layer are respectively positioned on two opposite sides of the active layer and are arranged in a stacking mode with the active layer;
the active layer includes a first quantum well layer and a second quantum well layer provided in the stacking direction, wherein a wavelength difference between the first quantum well layer and the second quantum well layer is 15nm to 30nm, the number of the first quantum well layers is 5 to 9, and the number of the second quantum well layers is 3 to 6.
In one embodiment, the first quantum well layer has a thickness from 40A to 80A and the second quantum well layer has a thickness from 40A to 80A.
In one embodiment, the active layer further includes a barrier layer, the first quantum well layer, and the second quantum well layer are sequentially stacked along the stacking direction, the stress of the first quantum well layer is +0.8% to +1.3%, the stress of the second quantum well layer is +0.8% to +1.3%, and the stress of the barrier layer is-0.2% to-0.6%.
In one embodiment, the active layer, the first confinement layer and the second confinement layer each comprise an aluminum indium gallium arsenide layer.
In one embodiment, the method further comprises the following steps:
the buffer layer is arranged on the surface, far away from the active layer, of the first limiting layer;
the first cladding layer is arranged on the surface, far away from the active layer, of the second limiting layer;
the plurality of strip-shaped structures are arranged on the surface, away from the second limiting layer, of the first coating layer at intervals;
and the second cladding layer is arranged on the surfaces of the strip-shaped structures and in gaps between the strip-shaped structures, and is provided with a ridge waveguide structure.
In one embodiment, the plurality of stripe structures comprise In1-xGaxAsyP1-yAnd (3) a layer.
In one embodiment, the In1-xGaxAsyP1-yThe value of x in the layer ranges from 0.05 to 0.32, and the value of y ranges from 0.05 to 0.69.
In one embodiment, the method further comprises the following steps:
and the ohmic contact layer is arranged on the surface of the ridge waveguide structure far away from the plurality of strip structures.
In one embodiment, the buffer layer, the first confinement layer, the active layer, the second confinement layer, the first cladding layer, the plurality of stripe structures, the second cladding layer, and the ohmic contact layer form a matrix structure;
the semiconductor device further includes:
the high-reflection coating layer is arranged on the first end face of the base body structure parallel to the long axis of the strip-shaped structure;
and the anti-reflection coating layer is arranged on a second end face of the substrate structure parallel to the long axis of the strip-shaped structure, and the first end face and the second end face are oppositely arranged.
Based on the same inventive concept, the application provides a semiconductor device manufacturing method, which comprises the following steps:
providing a substrate, and growing a first limiting layer on the surface of the substrate;
sequentially stacking and growing a first quantum well layer and a barrier layer on the surface of the first limiting layer far away from the substrate, and then sequentially stacking and growing a second quantum well layer and a barrier layer to generate an active layer;
growing a second limiting layer on the surface of the active layer far away from the first limiting layer;
wherein the wavelength difference between the first quantum well layer and the second quantum well layer is 15nm to 30nm, the number of the first quantum well layers is 5 to 9, and the number of the second quantum well layers is 3 to 6.
In one embodiment, an aluminum indium gallium arsenide material is adopted to sequentially stack and grow the first quantum well layer and the barrier layer on the surface of the first limiting layer far away from the substrate, and then sequentially stack and grow the second quantum well layer and the barrier layer to generate the active layer;
wherein a thickness of the first quantum well layer is 40A to 80A and a thickness of the second quantum well layer is 40A to 80A.
In one embodiment, the first quantum well layer has a stress of +0.8% to +1.3%, the second quantum well layer has a stress of +0.8% to +1.3%, and the barrier layer has a stress of-0.2% to-0.6%.
In one embodiment, the method further comprises the following steps:
growing a buffer layer on the surface of the first limiting layer far away from the active layer;
growing a first cladding layer on the surface of the second limiting layer far away from the active layer;
forming a plurality of strip-shaped structures arranged at intervals on the surface of the first coating layer, which is far away from the second limiting layer, through etching;
and forming a second cladding layer on the surfaces of the strip-shaped structures and gaps of the strip-shaped structures, wherein the second cladding layer is provided with a ridge waveguide structure.
In one embodiment, the method further comprises the following steps:
by using In1-xGaxAsyP1-yEtching the surface of the first coating layer far away from the second limiting layer to form a plurality of strip-shaped structures arranged at intervals;
wherein, the In1-xGaxAsyP1-yThe value of x in the layer ranges from 0.05 to 0.32, and the value of y ranges from 0.05 to 0.69.
In one embodiment, the method further comprises the following steps:
and forming an ohmic contact layer on the surface of the ridge waveguide structure far away from the plurality of strip structures.
In one embodiment, the buffer layer, the first confinement layer, the active layer, the second confinement layer, the first cladding layer, the plurality of stripe structures, the second cladding layer, and the ohmic contact layer form a matrix structure; the semiconductor device manufacturing method further includes:
growing a high-reflection coating layer on the first end face of the base body structure parallel to the long axis of the strip-shaped structure;
and growing an anti-reflection coating layer on a second end face of the substrate structure parallel to the long axis of the strip structure, wherein the first end face and the second end face are arranged oppositely.
Based on the same inventive concept, the present application provides a semiconductor device, including an active layer, and a first confinement layer and a second confinement layer respectively located at two opposite sides of the active layer and arranged in a stack with the active layer;
the active layer includes a first quantum well layer, a barrier layer, and a second quantum well layer disposed along the stacking direction, wherein a wavelength difference between the first quantum well layer and the second quantum well layer is 15nm to 30nm, a number of the first quantum well layer is 5 layers to 9 layers, the number of the second quantum well layer is 3 layers to 6 layers, a thickness of the first quantum well layer is 40 a to 80 a, a thickness of the second quantum well layer is 40 a to 80 a, a stress of the first quantum well layer is +0.8% to +1.3%, a stress of the second quantum well layer is +0.8% to +1.3%, and a stress of the barrier layer is-0.2% to-0.6%.
In the semiconductor device and the manufacturing method thereof, the active layer comprises a first quantum well layer and a second quantum well layer which are arranged along the stacking direction, wherein the wavelength difference between the first quantum well layer and the second quantum well layer is 15nm to 30nm, the number of the first quantum well layers is 5 to 9, and the number of the second quantum well layers is 3 to 6. By setting the number of the first quantum well layers, the number of the second quantum well layers and the wavelength difference between the first quantum well layers and the second quantum well layers, the operating bandwidth of the semiconductor device in a high-temperature environment can be improved by the first quantum well layer structure, the operating bandwidth of the semiconductor device in a low-temperature environment can be improved by the second quantum well layer structure, the semiconductor device can be operated at the ambient temperature of-40 ℃ to 85 ℃, the bandwidth can be guaranteed to be more than 18GHz under the refrigeration-free condition, the 25Gbps modulation rate requirement required by a 5G forward transmission system is met, and high error code behavior of communication can be achieved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments or the conventional technologies of the present application, the drawings used in the descriptions of the embodiments or the conventional technologies will be briefly introduced below, it is obvious that the drawings in the following descriptions are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic cross-sectional structure of an embodiment after one-time epitaxy is completed.
Fig. 2 is a schematic cross-sectional view of an active layer structure provided in an embodiment.
Fig. 3 is a schematic diagram of a process for forming a plurality of bar structures according to an embodiment.
Fig. 4 is a schematic cross-sectional view of an embodiment of a double epitaxy process.
Fig. 5 is a schematic diagram of a process for forming a ridge waveguide structure according to an embodiment.
Fig. 6 is a schematic view of a long axis direction of a stripe structure provided in an embodiment.
FIG. 7 is a schematic cross-sectional view illustrating a finished end-face coating process in one embodiment.
Fig. 8 is a bandwidth distribution diagram at 85 ℃ obtained by different quantum well layers corresponding to different types of quantum wells in one embodiment.
Fig. 9 is a bandwidth distribution diagram at-40 ℃ obtained by different quantum well layers corresponding to different types of quantum wells in one embodiment.
Figure 10 is a graph of bandwidth distribution at 85 c obtained for different quantum well thicknesses in one embodiment.
FIG. 11 is a graph of bandwidth distribution at 85 ℃ obtained under different quantum well stresses in one embodiment.
FIG. 12 is a graph illustrating the bandwidth distribution at 85 ℃ obtained for different quantum well wavelength differences in one embodiment.
Description of reference numerals:
10. a substrate; 11. a buffer layer; 12. a first confinement layer; 13. an active layer; 131. a first quantum well layer; 132. a barrier layer; 133. a second quantum well layer; 14 a second confinement layer; 15. a first cladding layer; 16. a plurality of strip-like structures; 17. a second cladding layer; 18. an ohmic contact layer; 19. a passivation film; 101. a first metal electrode layer; 102. a second metal electrode layer; 103. a high reflection coating layer; 104. and (4) an anti-reflection coating layer.
Detailed Description
To facilitate an understanding of the present application, the present application will now be described more fully with reference to the accompanying drawings. Embodiments of the present application are set forth in the accompanying drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and/or sections, these elements, components, regions, layers, doping types and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or section from another element, component, region, layer, doping type or section. Thus, a first element, component, region, layer, doping type or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application; for example, the first doping type may be made the second doping type, and similarly, the second doping type may be made the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.
Spatial relational terms, such as "under," "below," "under," "over," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations) and the spatial descriptors used herein interpreted accordingly.
As used herein, the singular forms "a", "an" and "the" may include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises/comprising," "includes" or "including," etc., specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. Also, in this specification, the term "and/or" includes any and all combinations of the associated listed items.
The design of the non-refrigeration industrial grade 25Gbps semiconductor device, wherein the design and manufacturing technology of the refrigeration 25Gbps semiconductor device are very mature abroad, if the performance of the semiconductor device needs to be further operated in the non-refrigeration industrial grade-40 ℃ to 85 ℃, the bandwidth of the semiconductor device is reduced due to great temperature variation, and communication error codes are formed on transmission, so that the problem becomes the largest technical threshold of the product. The quantum well structure of the active region is optimized mainly through epitaxial structure design, so that the problem of high-temperature and low-temperature bandwidth degradation is solved, the product is operated at the ambient temperature of-40 ℃ to 85 ℃, and the bandwidth can have excellent performance of more than 18GHz without refrigeration.
Based on this, the present application provides a semiconductor device. The semiconductor device comprises an active layer 13 and a first limiting layer 12 and a second limiting layer 14 which are respectively positioned at two opposite sides of the active layer 13 and are arranged in a stacking mode with the active layer 13. The active layer 13 includes a first quantum well layer 131 and a second quantum well layer 133 arranged in the stacking direction, wherein the wavelength difference between the first quantum well layer 131 and the second quantum well layer 133 is 15nm to 30nm, the number of the first quantum well layers 131 is 5 to 9, and the number of the second quantum well layers 133 is 3 to 6.
Referring specifically to fig. 1 and 2, a first confinement layer 12, an active layer 13, and a second confinement layer 14 may be sequentially deposited on a substrate 10. The first confinement layer 12, the active layer 13 and the second confinement layer 14 may be made of aluminum indium gallium arsenide (AlInGaAs) materials.
Wherein the active layer 13 includes two types of multiple quantum wells. One type of multiple quantum well is the first quantum well layer 131 and the other type of multiple quantum well is the second quantum well layer 133. The wavelength difference between the first quantum well layer 131 and the second quantum well layer 133 is 15nm to 30nm, the number of the first quantum well layers 131 is 5 to 9, and the number of the second quantum well layers 133 is 3 to 6. By setting the number of the first quantum well layers 131, the number of the second quantum well layers 133 and the wavelength difference between the first quantum well layers and the second quantum well layers, the operation bandwidth of the semiconductor device in a high-temperature environment can be improved by the first quantum well layer 131, the operation bandwidth of the semiconductor device in a low-temperature environment can be improved by the second quantum well layer 133, so that the semiconductor device can operate in an environment temperature of-40 ℃ to 85 ℃, and under the condition of no refrigeration, the bandwidth can be ensured to be more than 18GHz, the 25Gbps modulation rate requirement required by a 5G forward transmission system is met, and the high error code behavior of optical communication can be avoided.
In one embodiment, the first quantum well layer 131 has a thickness from 40A to 80A and the second quantum well layer 133 has a thickness from 40A to 80A. With such a design thickness, when the number of the first quantum well layers 131 is 5 to 9 and the number of the second quantum well layers 133 is 3 to 6, the bandwidth at 85 ℃ can be greater than 18GHz, and such a thickness is not difficult to adapt to parameters of MOCVD equipment in an epitaxial production process, and is suitable for mass production.
In one embodiment, the active layer 13 further includes a barrier layer 132, the first quantum well layer 131, and the second quantum well layer 133 are sequentially stacked along the stacking direction, the stress of the first quantum well layer 131 is +0.8% to +1.3%, the stress of the second quantum well layer 133 is +0.8% to +1.3%, and the stress of the barrier layer 132 is-0.2% to-0.6%.
It is understood that the deposition sequence of the first quantum well layer 131 and the second quantum well layer 133 is not particularly limited, and the first quantum well layer 131 and the barrier layer 132 may be alternately deposited on the first confinement layer 12, and then the second quantum well layer 133 and the barrier layer 132 may be alternately deposited on the uppermost barrier layer 132 (see fig. 2 for details). Of course, the second quantum well layer 133 and the barrier layer 132 may be deposited alternately on the first confinement layer 12, and then the first quantum well layer 131 and the barrier layer 132 may be deposited alternately on the uppermost barrier layer 132.
On one hand, the larger the stress of the quantum well or the potential barrier is, the more easily the lattice mismatch is generated in the epitaxial process, so that the quality of the wafer is degraded, and the yield and the characteristics are greatly reduced; on the other hand, the addition of quantum well stress is beneficial to improving the differential quantum efficiency of the semiconductor device and improving the bandwidth. In order to balance the contradiction between the addition of quantum well stress and lattice mismatch, reverse stress is added to a potential barrier adjacent to a stressed quantum well to be used as stress compensation, so that lattice mismatch is avoided; in the embodiment, under the condition that the compressive stress is added to the quantum well, the tensile stress of the adjacent barrier is simultaneously given to serve as stress compensation, so that the problem of lattice mismatch is avoided under the condition of a multi-layer quantum well and barrier stacking epitaxial process.
In one embodiment, the semiconductor device further includes a buffer layer 11, a first cladding layer 15, a plurality of stripe structures 16, and a second cladding layer 17.
The buffer layer 11 is disposed on a surface of the first confinement layer 12 away from the active layer 13. The first cladding layer 15 is disposed on a surface of the second confinement layer 14 away from the active layer 13. The plurality of stripe structures 16 are disposed at intervals on the surface of the first cladding layer 15 away from the second confinement layer 14. The second cladding layer 17 is disposed on the surfaces of the plurality of stripe structures 16 and in the gaps between the plurality of stripe structures 16, and the second cladding layer 17 is provided with a ridge waveguide structure.
In this embodiment, the buffer layer 11, the first cladding layer 15 and the second cladding layer 17 may be indium phosphide (InP) materials. The first cladding layer 15 and the second cladding layer 17 are both P-InP material, and the buffer layer 11 is N-InP material. The buffer layer 11 is disposed on the surface of the substrate 10, andthe substrate 10 is covered to provide a buffer. In one embodiment, the plurality of stripe structures 16 comprises In1-xGaxAsyP1-yAnd (3) a layer. Said In1-xGaxAsyP1-yThe value of x in the layer ranges from 0.05 to 0.32, and the value of y ranges from 0.05 to 0.69. In one possible embodiment, x =0.23 and y = 0.50. The second cladding layer 17 is disposed on the surfaces of the plurality of bar-shaped structures 16 and in the gaps between the plurality of bar-shaped structures 16, and is used to clad the plurality of bar-shaped structures 16 and fill the gaps between the plurality of bar-shaped structures 16. At this time, a large difference in refractive index is formed between the second cladding layer 17 and the plurality of stripe structures 16. The second cladding layer 17 is provided with a ridge waveguide structure, and has the advantages of high power, long-distance transmission and the like.
In one embodiment, the semiconductor device further includes an ohmic contact layer 18, a first metal electrode layer 101, and a second metal electrode layer 102. The ohmic contact layer 18 is disposed on a surface of the ridge waveguide structure away from the plurality of stripe structures 16. The first metal electrode layer 101 is disposed on a surface of the ohmic contact layer 18 away from the second cladding layer 17. The second metal electrode layer 102 is disposed on a surface of the substrate 10 away from the buffer layer 11. The first metal electrode layer 101 is a P-metal electrode layer. The second metal electrode layer 102 is an N-metal electrode layer. The material of the ohmic contact layer 18 may be InGaAs material.
Referring to fig. 3-7, in one embodiment, the second metal electrode layer 102, the substrate 10, the buffer layer 11, the first confinement layer 12, the active layer 13, the second confinement layer 14, the first cladding layer 15, the plurality of stripe structures 16, the second cladding layer 17, the ohmic contact layer 18, and the first metal electrode layer 101 form a matrix structure (not labeled). The semiconductor device further comprises a high reflection coating 103 and an anti-reflection coating 104. The high-reflection coating layer 103 is arranged on the first end face of the base body structure parallel to the long axis of the strip-shaped structure. The anti-reflection coating layer 104 is arranged on the second end face of the substrate structure parallel to the long axis of the strip structure. The first end face is arranged opposite to the second end face.
In this embodiment, the second metal electrode layer 102, the substrate 10, the buffer layer 11, the first confinement layer 12, the active layer 13, the second confinement layer 14, the first cladding layer 15, the plurality of stripe structures 16, the second cladding layer 17, the ohmic contact layer 18, and the first metal electrode layer 101 may be regarded as a single integral structure. As shown in fig. 7, the high reflective coating layer 103 is disposed on a first end surface of the base structure parallel to the long axis of the stripe structure, i.e., a right end surface in fig. 7. The second end face is disposed opposite to the first end face, i.e., the left end face in fig. 7. The long axis direction of the strip-shaped structure is an axis parallel to the length direction of the strip-shaped structure, i.e., the direction shown in the right position in fig. 7. At this time, the second metal electrode layer 102, the substrate 10, the buffer layer 11, the first confinement layer 12, the active layer 13, the second confinement layer 14, the first cladding layer 15, the plurality of stripe structures 16, the second cladding layer 17, the ohmic contact layer 18, and the first metal electrode layer 101 are disposed between the high reflection coating layer 103 and the anti-reflection coating layer 104.
Based on the same inventive concept, the application provides a semiconductor device manufacturing method, which comprises the following steps:
s10, providing a substrate 10, and growing a buffer layer 11 and a first limiting layer 12 on the surface of the substrate 10;
s20, sequentially growing a first quantum well layer 131 and a barrier layer 132 alternately stacked and a second quantum well layer 133 and a barrier layer 132 alternately stacked on the surface of the first confinement layer 12 away from the buffer layer 11 to generate an active layer 13;
s30, growing a second limiting layer 14 on the surface of the active layer 13 far away from the first limiting layer 12;
wherein the wavelength difference between the first quantum well layer 131 and the second quantum well layer 133 is 15nm to 30nm, the number of the first quantum well layers 131 is 5 to 9, and the number of the second quantum well layers 133 is 3 to 6.
In this embodiment, the method for manufacturing the semiconductor device uses MOCVD to grow the buffer layer 11, the first confinement layer 12, the first quantum well layer 131 alternately stacked barrier layer 132, the second quantum well layer 133 alternately stacked barrier layer 132, and the second confinement layer 14 on the surface of the substrate 10. The first confinement layer 12, the active layer 13 and the second confinement layer 14 may be made of aluminum indium gallium arsenide (AlInGaAs) materials.
In the above embodiment, the number of the first quantum well layers 131, the number of the second quantum well layers 133, and the wavelength difference between the two are set, so that the first quantum well layer 131 structure can improve the operating bandwidth of the semiconductor device in a high-temperature environment, the second quantum well layer 133 structure can improve the operating bandwidth of the semiconductor device in a low-temperature environment, and further, the semiconductor device can operate in an ambient temperature of-40 ℃ to 85 ℃, and when the semiconductor device is in an uncooled condition, the bandwidth can be guaranteed to be above 18GHz, the 25Gbps modulation rate requirement required by a 5G fronthaul system is met, and further, the high error code behavior of optical communication can be avoided.
In one embodiment, the semiconductor device growth steps are as follows: an indium phosphide layer (buffer layer 11), a first confinement layer 12, an aluminum indium gallium arsenide layer (active layer 13), a second confinement layer 14, an indium phosphide layer (first cladding layer 15), indium gallium arsenide phosphide (InGaAsP, a plurality of strip structures 16), and an indium phosphide layer (second cladding layer 17) are sequentially grown on the surface of an InP substrate 10 (also called a wafer) from bottom to top by using an MOCVD method, so that the structure shown in fig. 1 is obtained.
The etching area is exposed through the photoetching and dry etching technology, namely the top surface of the end face etching area is subjected to dry etching by adopting an RIE (reactive Ion etching) technology, the second cladding layer 17 and the plurality of strip-shaped structures 16 are etched from top to bottom, the etching is stopped at the first cladding layer 15, so that a plurality of diffraction strip-shaped structures are etched on the InGaAsP material, and the structure shown in the figure 3 is obtained.
Referring to fig. 4, the second clad layer 17 is grown as follows: a second cladding layer 17 and an ohmic contact layer 18 are sequentially grown on the plurality of stripe structures 16 by using the MOCVD growth technique. The second cladding layer 17 is an InP material, and the second cladding layer 17 completely covers and fills the plurality of etched stripe structures. The ohmic contact layer 18 is InGaAs material, and a semi-finished wafer is obtained.
Referring to fig. 5, in order to effectively inject current into the active region for electro-optic conversion, after obtaining a semi-finished wafer, a ridge waveguide structure is defined to limit current carriers and photons to define a ridge waveguide with a width of about 2um by using a photolithography technique and a photomask, and a RIE technique is used to dry-etch a plurality of strip structures, so as to obtain a ridge waveguide structure.
Referring to fig. 5-7, in one embodiment, after an insulating passivation film 19 of silicon dioxide or silicon nitride is formed on the structure surface by using a PECVD technique using plasma enhanced chemical vapor deposition, the passivation film 19 on the surface of the ridge waveguide ohmic contact layer 18 is etched and removed, and at this time, the passivation film 19 only covers the surface of the region outside the ridge waveguide. Then plating a p-metal electrode layer (a first metal electrode layer 101) above the ridge waveguide ohmic contact layer, thinning and polishing the back surface of the substrate 10 of the indium phosphide to 100um, and plating an n-metal electrode layer (a second metal electrode layer 102); and cutting the semi-finished wafer to obtain a chip semi-finished product, plating an anti-reflection coating 104 on one end (the left side in the figure 7) of the chip semi-finished product, and plating a high-reflection coating 103 on the opposite end (the right side in the figure 7), so that the process is finished, and obtaining the non-refrigeration industrial 25Gbps semiconductor chip.
In one embodiment, the present application provides the following specific 5 embodiments optimized for three types of structures in the active region. The three structures are sequentially overlapped by the first quantum well layer 131 and the barrier layer 132 and sequentially overlapped by the second quantum well layer 133 and the barrier layer 132 according to the epitaxial sequence, and because the most serious part affecting the characteristics under the high-temperature and low-temperature operation is that the high-temperature bandwidth is easy to be degraded to less than 18GHz, the embodiments 1, 3, 4 and 5 mainly aim at optimizing the relationship between the structural parameters of the active region and the high-temperature bandwidth, and the embodiment 2 aims at optimizing the low-temperature bandwidth; wherein, the Coupling Coefficient (Coupling Coefficient) of the semiconductor device commonly used in the five embodiments is 100 cm-1, the length of the resonant cavity is 150um, and the width of the ridge waveguide is 2um, and the parameter setting is also within the commercial specification range of the common 25Gbps semiconductor device, wherein if the values of the Coupling Coefficient, the length of the resonant cavity and the width of the ridge waveguide are changed, the trend of the influence on the bandwidth is consistent, and the result of the optimization of the five semiconductor devices in the embodiments is not influenced.
Example 1
In this embodiment, the purpose of increasing the high-temperature bandwidth is achieved by optimizing the number of the first quantum well layers 131 in the active region, wherein four parameters are to be optimized, which are the number of the second quantum well layers 133, the thickness of the quantum wells, the stress of the quantum wells and the barriers, and the wavelength difference between the first quantum well layers 131 and the second quantum well layers 133, respectively, and these four parameters are optimized and designed in embodiments 2 to 5 one by one. In embodiment 1, the thickness of the quantum well is near the middle value of the available value range (i.e., thickness 70), the stress between the quantum well and the potential barrier is near the middle value of the available value range (i.e., compressive stress +1.2% of the quantum well and tensile stress-0.6%) and the wavelength difference between the two types of quantum wells is near the middle value of the available value range (i.e., 20 nm), and the values of the above preliminary parameters are set, which are mainly considered as the settings that the epitaxial equipment of a general commercial product is easily adaptable in production, and the parameters are finely adjusted before and after the production is performed on the premise that the production is easy, so that the production difficulty is reduced; according to the optimization result shown in fig. 8, when the number of the first quantum well layers 131 is in the range of 5 to 9, most of the designs can satisfy that the bandwidth at 85 ℃ is greater than 18GHz, except that the number of the second quantum well layers 133 is reduced to 3, which cannot be satisfied, wherein when the number of the first quantum well layers 131 is 7, and the number of the second quantum well layers 133 is 5, the high bandwidth value is 18.9GHz, and therefore the number of the first quantum well layers 131 is 7, which is the optimal value of the present embodiment.
Example 2
In this embodiment, the number of the second quantum well layers 133 in the active region is optimized to ensure that the bandwidth at-40 ℃ is greater than 18GHz, as shown in fig. 9, taking the number of the first quantum well layers 131 in embodiment 1 as 7 as a design premise, when the number of the second quantum well layers 133 is in a range of 3 to 6, the requirement of the bandwidth at 18GHz can be met, even when the number of the first quantum well layers 131 is 6, the requirement can be met, because the bandwidth at-40 ℃ is gradually increased along with the increase of the number of the second quantum well layers 133, and the bandwidth is gradually increased to 5 to 6 to gradually form bandwidth value saturation, the number of the second quantum well layers 133 is the optimal value in this embodiment when 5 to 6.
Example 3
In this embodiment, individual thicknesses of all quantum wells in an active region are optimized to ensure that a bandwidth at 85 ℃ is greater than 18GHz, as shown in fig. 10, taking the optimal value taking result of embodiment 2 that 7 first quantum well layers 131 are matched with 5 second quantum well layers 133, when a value range of the quantum well thickness is 40 a-80 a, the bandwidth at 85 ℃ is greater than 18GHz, wherein a bandwidth expression of 19.3GHz is obtained when the quantum well thickness is 60 a, and this thickness is used in an epitaxial production process, and is not difficult to adapt to parameters of MOCVD equipment and suitable for mass production.
Example 4
In the embodiment, the stress of all quantum wells and barriers in the active region is optimized to ensure that the bandwidth at 85 ℃ is more than 18 GHz; generally speaking, the larger the stress of a quantum well or a potential barrier is, the more easily the lattice mismatch is generated in the epitaxial process, the wafer quality is deteriorated, the yield and the characteristics are greatly reduced, and the addition of the quantum well stress is helpful for improving the differential quantum efficiency of a semiconductor device, improving the bandwidth, balancing the contradiction between the addition of the quantum well stress and the lattice mismatch, and generally adding reverse stress to the potential barrier adjacent to the stressed quantum well as stress compensation to avoid the lattice mismatch; in the embodiment, under the condition that the quantum well is added with compressive stress, the adjacent barrier tensile stress is also given as stress compensation so as to realize the problem of no lattice mismatch under the multilayer quantum well and barrier stacking epitaxial process; as shown in fig. 11, taking the optimal value result of example 3, taking 7 high-temperature quantum wells, 5 second quantum well layers 133, and a quantum well thickness 60 a as a design premise, when the value range of the quantum well stress is +0.8% to +1.3%, the value range of the barrier stress is-0.2% to-0.6%, and the requirement that the bandwidth at 85 ℃ is greater than 18GHz can be met, wherein when the quantum well stress is +1.3%, and the barrier stress is-0.6%, the bandwidth is 19.4 GHz; from the results of fig. 11, it can be observed that the barrier stress of-0.8% can satisfy the bandwidth requirement at 85 ℃, but considering the condition that the bandwidth is obviously reduced relative to the barrier stress of-0.6%, and considering the stress error occurring during the adjustment of the actual MOCVD epitaxy, it is not recommended to use the barrier stress of-0.8% as a proper value range, which easily causes the reduction of the tolerance of the production quality.
Example 5
In the embodiment, the difference value of the energy system wavelength of the materials of the two types of quantum wells in the active region is optimized to ensure that the bandwidth at 85 ℃ is more than 18 GHz; taking the optimal value taking result of embodiment 4, the number of the high-temperature quantum wells is 7, and the number of the second quantum well layers is 5, the thickness of the quantum wells is 60 a, the stress of the quantum wells is +1.3%, and the barrier stress is-0.6%, as shown in fig. 12, the wavelength difference of the quantum wells defined by the horizontal axis represents the difference between the wavelength of the first quantum well layer 131 and the wavelength of the second quantum well layer 133, when the wavelength difference is in the value range of 15-30 nm, the bandwidth at 85 ℃ can be obtained to be greater than 18GHz, wherein the optimal wavelength difference value of the quantum wells is 25nm, and the bandwidth has a bandwidth expression of 19.7 GHz.
The five embodiments described above are embodied under the cost limit of commercial mass production, starting from the epitaxial design of the chip, and ensuring the feasibility of the non-refrigeration working temperature grade product, and the consideration of each working procedure and the optimization design of the embodiments all have the key commercial requirements of the 5G forwarding system and the data center system: the basic principle of localization, low cost, high speed, easy mass production and no sacrifice of product quality is favorable for promoting the process of commercial popularization of a 5G system and a data center system.
It should be understood that, although the respective steps in the flowcharts in the above-described embodiments are sequentially shown as indicated by arrows, the steps are not necessarily performed sequentially as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise.
In the description herein, references to the description of "some embodiments," "other embodiments," "desired embodiments," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the application. In this specification, a schematic description of the above terminology may not necessarily refer to the same embodiment or example.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features of the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the claims. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (7)
1. A method for manufacturing a semiconductor device is characterized by comprising the following steps:
providing a substrate, and growing a first limiting layer on the surface of the substrate;
sequentially stacking and growing a first quantum well layer and a barrier layer on the surface of the first limiting layer far away from the substrate, and then sequentially stacking and growing a second quantum well layer and a barrier layer to generate an active layer;
growing a second limiting layer on the surface of the active layer far away from the first limiting layer;
wherein the wavelength difference between the first quantum well layer and the second quantum well layer is 15nm to 30nm, the number of the first quantum well layers is 5 to 9, and the number of the second quantum well layers is 3 to 6;
the first quantum well layer has a thickness from 40A to 80A, and the second quantum well layer has a thickness from 40A to 80A;
the stress of the first quantum well layer is +0.8% to +1.3%, the stress of the second quantum well layer is +0.8% to +1.3%, and the stress of the barrier layer is-0.2% to-0.6%.
2. The method of claim 1, wherein the first quantum well layer and the barrier layer are sequentially grown on the surface of the first confinement layer away from the substrate by stacking an aluminum indium gallium arsenide material, and the second quantum well layer and the barrier layer are sequentially grown on the surface of the first confinement layer away from the substrate by stacking the quantum well layer and the barrier layer to form the active layer.
3. The method for manufacturing a semiconductor device according to claim 1, further comprising:
growing a buffer layer on the surface of the first limiting layer far away from the active layer;
growing a first cladding layer on the surface of the second limiting layer far away from the active layer;
forming a plurality of strip-shaped structures arranged at intervals on the surface of the first coating layer, which is far away from the second limiting layer, through etching;
and forming a second cladding layer on the surfaces of the strip-shaped structures and gaps of the strip-shaped structures, wherein the second cladding layer is provided with a ridge waveguide structure.
4. The method for manufacturing a semiconductor device according to claim 3, further comprising:
by using In1-xGaxAsyP1-yEtching the surface of the first coating layer far away from the second limiting layer to form a plurality of strip-shaped structures arranged at intervals;
wherein, the In1-xGaxAsyP1-yThe value of x in the layer ranges from 0.05 to 0.32, and the value of y ranges from 0.05 to 0.69.
5. The method for manufacturing a semiconductor device according to claim 3, further comprising:
and forming an ohmic contact layer on the surface of the ridge waveguide structure far away from the plurality of strip structures.
6. The semiconductor device manufacturing method according to claim 5, wherein the buffer layer, the first confinement layer, the active layer, the second confinement layer, the first cladding layer, the plurality of stripe structures, the second cladding layer, and the ohmic contact layer form a matrix structure; the semiconductor device manufacturing method further includes:
growing a high-reflection coating layer on the first end face of the base body structure parallel to the long axis of the strip-shaped structure;
and growing an anti-reflection coating layer on a second end face of the substrate structure parallel to the long axis of the strip structure, wherein the first end face and the second end face are arranged oppositely.
7. The semiconductor device is characterized by comprising an active layer, a first limiting layer and a second limiting layer, wherein the first limiting layer and the second limiting layer are respectively positioned on two opposite sides of the active layer and are arranged in a stacking mode with the active layer;
the active layer includes a first quantum well layer and a second quantum well layer arranged in the stacking direction, wherein a wavelength difference between the first quantum well layer and the second quantum well layer is 15nm to 30nm, the number of the first quantum well layers is 5 to 9, and the number of the second quantum well layers is 3 to 6;
the first quantum well layer has a thickness from 40A to 80A, and the second quantum well layer has a thickness from 40A to 80A;
the active layer further includes a barrier layer, the first quantum well layer, and the second quantum well layer being sequentially stacked in the stacking direction, a stress of the first quantum well layer being +0.8% to +1.3%, a stress of the second quantum well layer being +0.8% to +1.3%, and a stress of the barrier layer being-0.2% to-0.6%.
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