CN112259611A - Oxide semiconductor thin film transistor and manufacturing method thereof - Google Patents

Oxide semiconductor thin film transistor and manufacturing method thereof Download PDF

Info

Publication number
CN112259611A
CN112259611A CN202011084344.7A CN202011084344A CN112259611A CN 112259611 A CN112259611 A CN 112259611A CN 202011084344 A CN202011084344 A CN 202011084344A CN 112259611 A CN112259611 A CN 112259611A
Authority
CN
China
Prior art keywords
oxide layer
layer
thin film
film transistor
oxide
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202011084344.7A
Other languages
Chinese (zh)
Inventor
董承远
章雯
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai Jiaotong University
InfoVision Optoelectronics Kunshan Co Ltd
Original Assignee
Shanghai Jiaotong University
InfoVision Optoelectronics Kunshan Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shanghai Jiaotong University, InfoVision Optoelectronics Kunshan Co Ltd filed Critical Shanghai Jiaotong University
Priority to CN202011084344.7A priority Critical patent/CN112259611A/en
Publication of CN112259611A publication Critical patent/CN112259611A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78639Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a drain or source connected to a bulk conducting substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742Thin film unipolar transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

An oxide semiconductor thin film transistor comprises a substrate, a grid electrode insulating layer, an oxide semiconductor layer and a source drain electrode metal layer, wherein the grid electrode, the grid electrode insulating layer, the oxide semiconductor layer and the source drain electrode metal layer are sequentially arranged on the substrate; and part of the first oxide layer is exposed from two sides of the second oxide layer, and the source electrode and the drain electrode are mutually spaced and are respectively in direct contact connection with the first oxide layer exposed from two sides of the second oxide layer, so that the source electrode, the drain electrode and the oxide semiconductor layer form better ohmic contact, the on-state current of the thin film transistor is effectively improved, and the comprehensive performance of the thin film transistor is optimized. The invention also relates to a manufacturing method of the oxide semiconductor thin film transistor.

Description

Oxide semiconductor thin film transistor and manufacturing method thereof
Technical Field
The present invention relates to the field of thin film transistors, and more particularly, to an oxide semiconductor thin film transistor and a method for fabricating the same.
Background
The switching elements currently used in displays are still amorphous silicon (a-Si) thin film transistors and polycrystalline silicon (p-Si) thin film transistorsThe amorphous silicon thin film transistor is most widely applied, but the amorphous silicon thin film transistor has low electron mobility (only 0.3-1 cm)2V · s), poor light stability, and the like. Although the polysilicon thin film transistor is much higher than the amorphous silicon thin film transistor in the aspect of electron mobility, the polysilicon thin film transistor has the problems of complex structure, large leakage current, poor film quality uniformity and the like. With the rapid development of display technologies, the video formats are gradually increased from standard definition to high definition to ultra-definition, and the requirements for resolution and shielding of displays are gradually increased, so that higher and higher requirements are put forward on the performance and size of thin film transistors, amorphous silicon thin film transistors and polycrystalline silicon thin film transistors cannot completely meet the requirements, and a high-temperature manufacturing process cannot be used for manufacturing a display panel with a larger size.
In recent years, an Amorphous Oxide Semiconductor Thin Film Transistor (AOS TFT) has attracted much attention in academic and industrial fields because of its excellent electrical and optical characteristics. In particular Amorphous indium gallium zinc oxide Thin Film transistors (a-IGZO TFTs) with high electron mobility (>10cm2V · s), low power consumption, simple process (no need for high temperature fabrication), fast response speed, good large area uniformity, high transmittance in the visible Light range, etc., are considered as core components of Active Matrix Organic Light Emitting Diode (AMOLED) and Active Matrix Liquid Crystal Display (AMLCD) driving circuits, and are also considered as the most competitive backplane driving technologies that are developed along with displays toward large size, flexibility, and portability.
For a thin film transistor with excellent performance, a large threshold voltage, a high on-off current ratio, a small subthreshold swing, and high stability are required. Generally, the larger the field effect mobility of the thin film transistor, the faster the pixel storage capacitor is charged, the smaller the leakage current of the thin film transistor, the faster the pixel storage capacitor is discharged, the smaller the subthreshold swing of the thin film transistor, and the faster the switching state transition of the thin film transistor, the more power saving. However, these have made high demands on the characteristics of the oxide semiconductor layer, such as the structure, surface defect state, carrier concentration, and carrier mobility.
As shown in fig. 1, a conventional oxide semiconductor thin film transistor includes a substrate 1, and a gate electrode 2, a gate insulating layer 3, an oxide semiconductor layer 4, and a source/drain electrode layer 5 sequentially provided on the substrate 1. The oxide semiconductor layer 4 generally has a single-layer structure, and the oxygen content of the oxide semiconductor layer 4 is controlled to adjust the carrier concentration during the process of manufacturing the oxide semiconductor layer 4, so that the oxide semiconductor layer 4 has different electron mobilities. However, the oxide semiconductor layers 4 with different oxygen contents have advantages and disadvantages, for example, although the oxide semiconductor layer 4 with lower oxygen content has high electron mobility and large threshold voltage, the off-state current is also large; the oxide semiconductor layer 4 containing higher oxygen content has lower electron mobility and smaller off-state current, but the threshold voltage is also correspondingly reduced, and the improvement of the comprehensive performance of the thin film transistor is limited by the non-unity characteristic of the oxide semiconductor layer 4 with a single-layer structure.
In order to improve the overall performance of the thin film transistor, another oxide semiconductor thin film transistor using a Double Stacked Channel (DSCL) has been proposed in the prior art, as shown in fig. 2, that is, an oxide semiconductor layer 4 of the oxide semiconductor thin film transistor includes an upper layer and a lower layer, wherein a first oxide layer 41 located in a front Channel of the lower layer is a metal oxide with a lower oxygen content, and a second oxide layer 42 located in a back Channel of the upper layer is a metal oxide with a higher oxygen content. However, in this structure, the back channel in direct contact with the source and drain electrodes in the source-drain electrode layer 5 is made of high-oxygen metal oxide, and because of its high resistivity, it is difficult to form an ideal ohmic contact, and the on-state current of the DSCL oxide semiconductor thin film transistor is still not ideal, which affects the overall performance of the DSCL oxide semiconductor thin film transistor.
Disclosure of Invention
The invention aims to provide an oxide semiconductor thin film transistor, which effectively improves the on-state current of the thin film transistor and optimizes the comprehensive performance of the thin film transistor.
The embodiment of the invention provides an oxide semiconductor thin film transistor, which comprises a substrate, and a grid, a grid insulating layer, an oxide semiconductor layer and a source drain metal layer which are sequentially arranged on the substrate, wherein the source drain metal layer comprises a source electrode and a drain electrode which are arranged at intervals; part of the first oxide layer is exposed from both sides of the second oxide layer, and the source and the drain are spaced apart from each other and are in direct contact with and connected to the first oxide layer exposed from both sides of the second oxide layer, respectively.
Furthermore, the oxygen content of the first oxide layer is 0% -50%, and the oxygen content of the second oxide layer is 4% -60%.
Further, the width M of the first oxide layer exposed from each side of the second oxide layer is 1-8 micrometers.
Further, the source electrode covers the first oxide layer exposed from one side of the second oxide layer and extends towards the second oxide layer to cover a part of the second oxide layer, and the drain electrode covers the first oxide layer exposed from the other side of the second oxide layer and extends towards the second oxide layer to cover a part of the second oxide layer.
Further, the width N of the lamination position of the source electrode and the second oxide layer and the lamination position of the drain electrode and the second oxide layer is greater than or equal to 1 μm.
Furthermore, the thickness D1 of the first oxide layer is 10-90 nm, and the thickness D2 of the second oxide layer is 10-90 nm.
Furthermore, the width X1 of the first oxide layer is 10-20 microns, the width X2 of the second oxide layer is 4-18 microns, the distance between the source electrode and the drain electrode is 2-8 microns, and the width M of the exposed part of the first oxide layer from the two sides of the second oxide layer is 1-8 microns.
Further, the materials of the first oxide layer and the second oxide layer are both metal oxides.
The invention also provides a manufacturing method of the oxide semiconductor thin film transistor, which comprises the following steps: providing a substrate, and patterning the substrate to form a grid electrode. A gate insulating layer is formed on the substrate and covers the gate. And sequentially preparing a first metal oxide layer and a second metal oxide layer on the first metal oxide layer on the gate insulating layer, wherein the oxygen content of the formed first metal oxide layer is less than that of the second metal oxide layer. Coating a layer of photoresist material on the second metal oxide layer and patterning to form a photoresist layer; the photoresist layer comprises a first photoresist area and a second photoresist area, the second photoresist area corresponds to an area where a second oxide layer is formed, and the first photoresist area corresponds to an area where a first oxide layer is removed; the height T1 of the second photoresist region is greater than the height T2 of the first photoresist region. The second metal oxide layer and the first metal oxide layer which are not covered by the photoresist layer are etched to form a first oxide layer. And thinning the photoresist layer to completely remove the photoresist material in the first photoresist region. Under the protection of the second photoresist region, the second metal oxide layer in the first photoresist region is etched away to form a second oxide layer and to expose a portion of the first oxide layer from both sides of the second oxide layer. Removing the photoresist material in the second photoresist region; and forming a source and a drain.
Further, the first metal oxide layer and the second metal oxide layer are sputtered by the same target material, the flow ratio of oxygen to argon entering the film coating chamber in the sputtering process of the first metal oxide layer is x: y, wherein the range of x is 0-3, and the range of y is 5-20; the flow ratio of oxygen to argon entering the film coating chamber in the sputtering process of the second metal oxide layer is a: b, wherein the range of a is 3-10, and the range of b is 5-20; and x: y is less than a: b.
The embodiment of the invention provides an oxide semiconductor thin film transistor and a manufacturing method thereof, wherein the oxide semiconductor thin film transistor comprises a substrate, a grid electrode insulating layer, an oxide semiconductor layer and a source drain electrode metal layer which are sequentially arranged on the substrate, the source drain electrode metal layer comprises a source electrode and a drain electrode which are arranged at intervals, the oxide semiconductor layer comprises a first oxide layer and a second oxide layer which is arranged above the first oxide layer in a stacking mode, and the oxygen content of the first oxide layer is lower than that of the second oxide layer; and part of the first oxide layer is exposed from two sides of the second oxide layer, and the source electrode and the drain electrode are mutually spaced and are respectively in direct contact connection with the first oxide layer exposed from two sides of the second oxide layer, so that the source electrode, the drain electrode and the oxide semiconductor layer form better ohmic contact, the on-state current of the thin film transistor is effectively improved, and the comprehensive performance of the thin film transistor is optimized.
Drawings
Fig. 1 is a schematic structural diagram of a conventional oxide semiconductor thin film transistor.
Fig. 2 is a schematic structural diagram of another conventional oxide semiconductor thin film transistor.
Fig. 3 is a schematic cross-sectional view of an oxide semiconductor thin film transistor according to a preferred embodiment of the invention.
Fig. 4A to 4H are schematic cross-sectional views illustrating a process of fabricating an oxide semiconductor thin film transistor according to a preferred embodiment of the invention.
Fig. 5 is a front view of a partial structure of an oxide semiconductor thin film transistor according to a preferred embodiment of the present invention.
Detailed Description
To further illustrate the technical means and effects of the present invention adopted to achieve the predetermined objects, the following detailed description of the embodiments, structures, features and effects of the present invention will be made with reference to the accompanying drawings and examples.
Fig. 3 is a schematic cross-sectional structure view of an oxide semiconductor thin film transistor according to a preferred embodiment of the present invention, referring to fig. 3, the oxide semiconductor thin film transistor includes a substrate 110, a gate 120, a gate insulating layer 130, an oxide semiconductor layer 140, and a source-drain metal layer 150 sequentially disposed on the substrate 110, the source-drain metal layer 150 includes a source 151 and a drain 152 disposed at an interval, the oxide semiconductor layer 140 includes a first oxide layer 141 and a second oxide layer 142 stacked above the first oxide layer 141, and an oxygen content of the first oxide layer 141 is lower than that of the second oxide layer 142; a portion of the first oxide layer 141 is exposed from both sides of the second oxide layer 142, and the source electrode 151 and the drain electrode 152 are respectively in direct contact with the first oxide layer 141 exposed from both sides of the second oxide layer 142.
The oxide semiconductor layer 140 is a conductive channel (i.e., an active layer) that short-circuits the source and drain electrodes 151 and 152. According to the invention, the second oxide layer 142 with high oxygen content is arranged above the first oxide layer 141 with low oxygen content, and the first oxide layer 141 is exposed from two sides of the second oxide layer 142 and is respectively contacted with the source electrode 151 and the drain electrode 152, so that good ohmic contact is formed between the first oxide layer 141 and the source electrode 151 and the drain electrode 152, the on-state current of the thin film transistor is effectively improved, and the comprehensive performance of the thin film transistor is optimized.
Further, the oxygen content of the first oxide layer 141 is 0% to 50%, and the oxygen content of the second oxide layer 142 is 4% to 60%.
Wherein, the first oxide layer 141 and the second oxide layer 142 are prepared by magnetron sputtering method, and the oxygen content of the first oxide layer 141 and the second oxide layer 142 can be adjusted by adjusting the oxygen (O) entering into the film coating chamber during preparation2) The volume ratio of the flow rate and the argon (Ar) flow rate (oxygen-argon flow rate ratio) was controlled. The first oxide layer 141 has a higher number of oxygen vacancies due to its lower oxygen content, a higher carrier concentration than the second oxide layer 142, and a higher electron mobility.
Further, the width M of the first oxide layer 141 exposed from each side of the second oxide layer 142 is 1 to 8 μ M.
Further, the source electrode 151 and the drain electrode 152 are also in stacked contact connection with a portion of the second oxide layer 142 to completely cover the first oxide layer 141. Specifically, the source electrode 151 covers the first oxide layer 141 exposed from one side of the second oxide layer 142 and extends to a direction of the second oxide layer 142 to cover a portion of the second oxide layer 142, the drain electrode 152 covers the first oxide layer 141 exposed from the other side of the second oxide layer 142 and extends to a direction of the second oxide layer 142 to cover a portion of the second oxide layer 142, and a portion of the second oxide layer 142 is exposed from a middle of the source electrode 151 and the drain electrode 152.
Further, as shown in fig. 4H, the width N of the stacked position of the source electrode 151 and the second oxide layer 142 and the width N of the stacked position of the drain electrode 152 and the second oxide layer 142 are both greater than or equal to 1 μm, and the widths of the stacked positions of the source electrode 151, the drain electrode 152, and the second oxide layer 142 may be equal to each other.
Further, as shown in FIG. 4G, the thickness D1 of the first oxide layer 141 is 10-90 nm, and the thickness D2 of the second oxide layer 142 is 10-90 nm.
Further, as shown in fig. 4G and 4H, the width X1 of the first oxide layer 141 is 10 to 20 micrometers, and the width X2 of the second oxide layer 142 is 4 to 18 micrometers; the distance (i.e., channel length) between the source 151 and the drain 152 is 2-8 μm; the width M of the exposed portion of the first oxide layer 141 from both sides of the second oxide layer 142 is 1 to 8 μ M.
Further, the material of the first oxide layer 141 and the second oxide layer 142 is metal oxide, specifically, Indium Gallium Zinc Oxide (IGZO), for example.
Indium gallium zinc oxide is a mixed oxide based on zinc oxide (ZnO) doped with indium (In) and gallium (Ga), and the main function of indium and gallium as doping elements is to adjust the carrier concentration. The carriers of the indium gallium zinc oxide are mainly generated by Oxygen Vacancies (OV), and under a specific external environment, the metal oxide causes Oxygen in crystal lattices to be desorbed and is lost, so that the Oxygen vacancies are formed. The greater the number of oxygen vacancies, the higher the carrier concentration and vice versa. Therefore, the carrier concentration can be adjusted by controlling the oxygen content, so that the oxide semiconductor layer 140 has different electron mobility.
The oxide semiconductor thin film transistor adopts the oxide semiconductor layer 140 with the double-layer structure of the first oxide layer 141 and the second oxide layer 142, the first oxide layer 141 with lower oxygen content is exposed from the two sides of the second oxide layer 142 with higher oxygen content and is respectively in contact connection with the source 151 and the drain 152, and good ohmic contact is formed between the oxide semiconductor layer 140 and the source 151 and the drain 152, so that the on-state current of the thin film transistor is improved, and the comprehensive performance of the thin film transistor is further improved.
Fig. 4A to 4H are schematic cross-sectional views illustrating a manufacturing process of an oxide semiconductor thin film transistor according to a preferred embodiment of the present invention, please refer to sequentially that the oxide semiconductor thin film transistor adopts a gray-scale Mask (Half-tone Mask) exposure and dry etching technique to realize the above DSCL structure with a special shape, and specifically, the manufacturing method of the oxide semiconductor thin film transistor includes:
as shown in fig. 4A, a substrate 110 is provided, and a gate 120 is patterned on the substrate 110, and the method for forming the gate 120 is a conventional mature technology and is not repeated herein.
As shown in fig. 4B, a gate insulating layer 130 is formed on the substrate 110 and covers the gate 120, and then two metal oxide layers are sequentially formed on the gate insulating layer 130, wherein the two metal oxide layers include a first metal oxide layer 141a directly contacting the gate insulating layer 130 and a second metal oxide layer 142a on the first metal oxide layer 141a, and an oxygen content of the formed first metal oxide layer 141a is less than an oxygen content of the formed second metal oxide layer 142 a. The first metal oxide layer 141a is used to form the first oxide layer 141 of the oxide semiconductor layer 140, and the second metal oxide layer 142a is used to form the second oxide layer 142 of the oxide semiconductor layer 140.
Specifically, the first metal oxide layer 141a and the second metal oxide layer 142a are sequentially prepared by a magnetron sputtering method, in this embodiment, the same target material is used for sputtering, and in the case of indium gallium zinc oxide, the target material is prepared by mixing zinc oxide, indium oxide, and gallium oxide according to a specific ratio.
The method for forming the first metal oxide layer 141a having an oxygen content less than that of the second metal oxide layer 142a includes: when the first metal oxide layer 141a is deposited, the flow ratio of oxygen to argon entering the film coating chamber is x: y, wherein the range of x is 0-3, and the range of y is 5-20; when the second metal oxide layer 142a is deposited, the flow ratio of oxygen to argon entering the film coating chamber is a: b, wherein the range of a is 3-10, and the range of b is 5-20; and x: y is less than a: b, i.e., the flow rate of argon oxygen is higher when depositing the second metal oxide layer 141a than when depositing the first metal oxide layer 141 a.
Taking x: y as 0:10 as an example, the flow rate of oxygen entering the coating chamber during deposition of the first metal oxide layer 141a is 0 standard state milliliter per minute (SCCM), and the flow rate of argon is 10 standard state milliliter per minute (SCCM). Taking a: b as 2:10 as an example, the flow rate of oxygen entering the coating chamber during the deposition of the second metal oxide layer 141a is 2 standard state ml/min (SCCM), and the flow rate of argon is 10 standard state ml/min (SCCM).
The oxide semiconductor layer 140 is prepared by a magnetron sputtering method, the indium gallium zinc oxide is used as the material of the oxide semiconductor layer 140, and the growth and post-treatment temperature of the oxide semiconductor layer 140 is lower than 350 ℃, so that the indium gallium zinc oxide can be grown on the glass substrate in a large scale by the magnetron sputtering method. Therefore, a large-sized display panel can be manufactured using the structure of the oxide semiconductor thin film transistor of the present invention.
As shown in fig. 4C, a photoresist material is coated on the second metal oxide layer 142a, and the photoresist material is patterned by a mask process to form a photoresist layer 200, where the photoresist layer 200 includes a first photoresist region 201 and a second photoresist region 202, where the second photoresist region 202 corresponds to a region where the second oxide layer 142 is formed later, and the first photoresist region 201 corresponds to a region where the second oxide layer 142 is removed from a region where the first oxide layer 141 is formed later, that is, a region where the second oxide layer 142 is exposed from two sides of the first oxide layer 141. Wherein the height T1 of the second photoresist region 202 is greater than the height T2 of the first photoresist region 201. The photoresist material in the other regions is completely removed.
Specifically, the first photoresist region 201 is half-exposed by using a half-tone mask (half-tone mask) or a gray-tone mask (gray-tone mask), wherein the half-tone mask is provided with a semi-transmission film at the position of the first photoresist region 201, and the exposure energy to the photoresist on the first photoresist region 201 is reduced by the semi-transmission film; the gray tone mask has a plurality of slits (slit) closely arranged at intervals at the position of the first photoresist region 201, and the exposure energy to the first photoresist region 201 is reduced by the light diffraction of the slits. Taking the positive photoresist as an example, during the exposure, the photoresist in the second photoresist region 202 is not exposed, the photoresist in the first photoresist region 201 is half exposed, and the photoresist in the other regions is completely exposed, so that after the exposure, the development is performed, so that in the photoresist layer 200 left after the development, the photoresist thickness T2 in the first photoresist region 201 is smaller than the photoresist thickness T1 in the second photoresist region 202.
As shown in fig. 4D, the second metal oxide layer 142a and the first metal oxide layer 141a not covered by the photoresist layer 200 are etched away. That is, the photoresist layer 200 is used as a mask to etch the two metal oxide layers 142a and the first metal oxide layer 141a, and the second metal oxide layer 142a and the first metal oxide layer 141a which are not covered by the photoresist layer 200 are sequentially etched and removed, while the second metal oxide layer 142a and the first metal oxide layer 141a which are covered by the photoresist layer 200 remain after etching, wherein the remaining first metal oxide layer 141a is the first oxide layer 141. This step may use either wet etching or dry etching.
As shown in fig. 4E, the photoresist layer 200 is thinned to completely remove the photoresist material in the first photoresist region 201.
Specifically, the photoresist material remaining in the first photoresist region 201 after the half exposure is completely removed to expose a portion of the second metal oxide layer 142a in the first photoresist region 201. Although the photoresist thickness of the second photoresist region 202 is reduced in this step, a certain thickness of photoresist remains on the first photoresist region 201 because the photoresist thickness T1 of the second photoresist region 202 is much greater than the photoresist thickness T2 of the first photoresist region 201. It should be noted that the method for thinning the photoresist layer 200 includes a wet photoresist Stripping (SPM), a dry photoresist stripping, and an organic solvent cleaning.
As shown in fig. 4F, under the protection of the photoresist material in the second photoresist region 202, the second metal oxide layer 142a in the first photoresist region 201 is etched away to form the second oxide layer 142 and expose a portion of the first oxide layer 141 from both sides of the second oxide layer 142. This step is a half-etching (only the second metal oxide layer 142a of the first photoresist region 201 is removed), and the etching time needs to be precisely controlled, so that dry etching is preferably used. The second metal oxide layer 142a that is not etched away is the second oxide layer 142.
As shown in fig. 4G, the photoresist in the second photoresist region 202 is completely removed, which may be performed in the same manner as the photoresist removal.
As shown in fig. 3, 4H and 5, a source electrode 151 and a drain electrode 152 are formed. Specifically, the source and drain electrodes 151 and 152 are pattern-formed on the oxide semiconductor layer 140, with the source and drain electrodes 151 and 152 spaced apart from each other; the source electrode 151 covers the first oxide layer 141 exposed from one side of the second oxide layer 142 and extends to a direction of the second oxide layer 142 to cover a portion of the second oxide layer 142, the drain electrode 152 covers the first oxide layer 141 exposed from the other side of the second oxide layer 142 and extends to a direction of the second oxide layer 142 to cover a portion of the second oxide layer 142, and a portion of the second oxide layer 142 is exposed from a middle of the source electrode 151 and the drain electrode 152.
According to the oxide semiconductor thin film transistor provided by the invention, the first oxide layer 141 positioned at the lower layer in the oxide semiconductor layer 140 with the double-layer channel is exposed from the two sides of the second oxide layer 142 positioned at the upper layer and is respectively in direct contact connection with the source electrode 151 and the drain electrode 152, and the oxygen content of the first oxide layer 141 is lower than that of the second oxide layer 142, so that the source electrode 151 and the drain electrode 152 form better ohmic contact with the oxide semiconductor layer 140, the on-state current of the thin film transistor is effectively improved, and the comprehensive performance of the thin film transistor is optimized.
Although the present invention has been described with reference to the above embodiments, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (10)

1. An oxide semiconductor thin film transistor comprises a substrate (110), and a gate (120), a gate insulating layer (130), an oxide semiconductor layer (140) and a source drain metal layer (150) which are sequentially arranged on the substrate (110), wherein the source drain metal layer (150) comprises a source electrode (151) and a drain electrode (152) which are arranged at intervals, the oxide semiconductor layer (140) comprises a first oxide layer (141) and a second oxide layer (142) which is arranged above the first oxide layer (141) in a stacking mode, and the oxygen content of the first oxide layer (141) is lower than that of the second oxide layer (142); part of the first oxide layer (141) is exposed from both sides of the second oxide layer (142), and the source electrode (151) and the drain electrode (152) are spaced apart from each other and are in direct contact with the first oxide layer (141) exposed from both sides of the second oxide layer (142), respectively.
2. The oxide semiconductor thin film transistor according to claim 1, wherein an oxygen content of the first oxide layer (141) is 0% to 50%, and an oxygen content of the second oxide layer (142) is 4% to 60%.
3. The oxide semiconductor thin film transistor according to claim 3, wherein a width M of the first oxide layer (141) exposed from each side of the second oxide layer (142) is 1 to 8 μ M.
4. The oxide semiconductor thin film transistor of claim 1, wherein the source electrode (151) covers the first oxide layer (141) exposed from one side of the second oxide layer (142) and extends to cover a portion of the second oxide layer (142) in a direction of the second oxide layer (142), and the drain electrode (152) covers the first oxide layer (141) exposed from the other side of the second oxide layer (142) and extends to cover a portion of the second oxide layer (142) in a direction of the second oxide layer (142).
5. The oxide semiconductor thin film transistor according to claim 4, wherein a width N of a lamination position of the source electrode (151) and the second oxide layer (142) and a lamination position of the drain electrode (152) and the second oxide layer (142) is greater than or equal to 1 μm.
6. The oxide semiconductor thin film transistor of claim 1, wherein the thickness D1 of the first oxide layer (141) is 10-90 nm, and the thickness D2 of the second oxide layer (142) is 10-90 nm.
7. The oxide semiconductor thin film transistor of claim 1, wherein a width X1 of the first oxide layer (141) is 10-20 μ M, a width X2 of the second oxide layer (142) is 4-18 μ M, a distance between the source electrode (151) and the drain electrode (152) is 2-8 μ M, and a width M of a portion of the first oxide layer (141) exposed from both sides of the second oxide layer (142) is 1-8 μ M.
8. The oxide semiconductor thin film transistor according to claim 1, wherein the material of the first oxide layer (141) and the second oxide layer (142) is a metal oxide.
9. A method for fabricating the oxide semiconductor thin film transistor according to any one of claims 1 to 8, comprising:
providing a substrate (110), and patterning to form a grid (120) on the substrate (110);
forming a gate insulating layer (130) on the substrate (110) and covering the gate electrode (120);
sequentially preparing a first metal oxide layer (141a) and a second metal oxide layer (142a) on the first metal oxide layer (141a) on the gate insulating layer (130) and making the oxygen content of the formed first metal oxide layer (141a) less than that of the second metal oxide layer (142 a);
coating a layer of photoresist material on the second metal oxide layer (142a) and patterning to form a photoresist layer (200); the light resistance layer (200) comprises a first light resistance area (201) and a second light resistance area (202), the second light resistance area (202) corresponds to an area where the second oxide layer (142) is formed, and the first light resistance area (201) corresponds to an area where the first oxide layer (141) is formed and the second oxide layer (142) is removed; the height T1 of the second light blocking region (202) is greater than the height T2 of the first light blocking region (201);
etching away the second metal oxide layer (142a) and the first metal oxide layer (141a) not covered by the photoresist layer (200) to form the first oxide layer (141);
thinning the light resistance layer (200) to completely remove the light resistance material of the first light resistance area (201);
under the covering protection of the second photoresist area (202), etching off the second metal oxide layer (142a) positioned in the first photoresist area (201) to form the second oxide layer (142) and expose part of the first oxide layer (141) from two sides of the second oxide layer (142);
removing the photoresist material from the second photoresist region (202); and
a source (151) and a drain (152) are formed.
10. The method for manufacturing the oxide semiconductor thin film transistor according to claim 9, wherein the first metal oxide layer (141a) and the second metal oxide layer (142a) are sputtered by using the same target, and the flow ratio of oxygen to argon entering the film coating chamber during sputtering of the first metal oxide layer (141a) is x: y, wherein x ranges from 0 to 3, and y ranges from 5 to 20; the flow ratio of oxygen to argon entering the film coating chamber in the sputtering process of the second metal oxide layer (142a) is a: b, wherein the range of a is 3-10, and the range of b is 5-20; and x: y is less than a: b.
CN202011084344.7A 2020-10-12 2020-10-12 Oxide semiconductor thin film transistor and manufacturing method thereof Pending CN112259611A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202011084344.7A CN112259611A (en) 2020-10-12 2020-10-12 Oxide semiconductor thin film transistor and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202011084344.7A CN112259611A (en) 2020-10-12 2020-10-12 Oxide semiconductor thin film transistor and manufacturing method thereof

Publications (1)

Publication Number Publication Date
CN112259611A true CN112259611A (en) 2021-01-22

Family

ID=74242281

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202011084344.7A Pending CN112259611A (en) 2020-10-12 2020-10-12 Oxide semiconductor thin film transistor and manufacturing method thereof

Country Status (1)

Country Link
CN (1) CN112259611A (en)

Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101257048A (en) * 2007-02-28 2008-09-03 三星电子株式会社 Thin film transistor and method of manufacturing the same
US20080299702A1 (en) * 2007-05-28 2008-12-04 Samsung Electronics Co., Ltd. METHOD OF MANUFACTURING ZnO-BASED THIN FILM TRANSISTOR
US20100051933A1 (en) * 2008-09-02 2010-03-04 Do-Hyun Kim Thin film transistor array substrate and method of fabricating the same
US20100140612A1 (en) * 2007-05-31 2010-06-10 Canon Kabushiki Kaisha Manufacturing method of thin film transistor using oxide semiconductor
US20110108835A1 (en) * 2009-11-09 2011-05-12 Samsung Electronics Co., Ltd. Transistors, methods of manufacturing a transistor and electronic devices including a transistor
CN102347368A (en) * 2010-07-30 2012-02-08 三星电子株式会社 Transistor, method of manufacturing transistor, and electronic device including transistor
KR20120054496A (en) * 2010-11-19 2012-05-30 삼성전자주식회사 Transistor, method of manufacturing the same and electronic device comprising transistor
CN103650121A (en) * 2011-06-08 2014-03-19 希百特股份有限公司 Metal oxide TFT with improved source/drain contacts
CN103681805A (en) * 2012-09-14 2014-03-26 株式会社半导体能源研究所 Semiconductor device and method for fabricating same
CN104885229A (en) * 2012-12-28 2015-09-02 株式会社神户制钢所 Thin-film transistor and manufacturing method therefor
CN105655291A (en) * 2016-01-07 2016-06-08 京东方科技集团股份有限公司 Method for manufacturing array substrate, array substrate and display panel

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101257048A (en) * 2007-02-28 2008-09-03 三星电子株式会社 Thin film transistor and method of manufacturing the same
US20080299702A1 (en) * 2007-05-28 2008-12-04 Samsung Electronics Co., Ltd. METHOD OF MANUFACTURING ZnO-BASED THIN FILM TRANSISTOR
US20100140612A1 (en) * 2007-05-31 2010-06-10 Canon Kabushiki Kaisha Manufacturing method of thin film transistor using oxide semiconductor
US20100051933A1 (en) * 2008-09-02 2010-03-04 Do-Hyun Kim Thin film transistor array substrate and method of fabricating the same
US20110108835A1 (en) * 2009-11-09 2011-05-12 Samsung Electronics Co., Ltd. Transistors, methods of manufacturing a transistor and electronic devices including a transistor
CN102347368A (en) * 2010-07-30 2012-02-08 三星电子株式会社 Transistor, method of manufacturing transistor, and electronic device including transistor
KR20120054496A (en) * 2010-11-19 2012-05-30 삼성전자주식회사 Transistor, method of manufacturing the same and electronic device comprising transistor
CN103650121A (en) * 2011-06-08 2014-03-19 希百特股份有限公司 Metal oxide TFT with improved source/drain contacts
CN103681805A (en) * 2012-09-14 2014-03-26 株式会社半导体能源研究所 Semiconductor device and method for fabricating same
CN104885229A (en) * 2012-12-28 2015-09-02 株式会社神户制钢所 Thin-film transistor and manufacturing method therefor
CN105655291A (en) * 2016-01-07 2016-06-08 京东方科技集团股份有限公司 Method for manufacturing array substrate, array substrate and display panel

Similar Documents

Publication Publication Date Title
US10403757B2 (en) Top-gate self-aligned metal oxide semiconductor TFT and method of making the same
US10707236B2 (en) Array substrate, manufacturing method therefor and display device
JP6416128B2 (en) Thin film transistor fabrication method
US20160043227A1 (en) Thin film transistor and manufacturing method thereof
US20100044699A1 (en) Thin film transistor and method of fabricating the same
US9570483B2 (en) Flat panel display device with oxide thin film transistor and method of fabricating the same
CN110164923B (en) OLED display panel and preparation method thereof
KR20120110040A (en) Amorphous oxide thin film transistor, forming method thereof and display panel including the same
WO2016165187A1 (en) Manufacturing method for dual-gate oxide semiconductor tft substrate, and structure of dual-gate oxide semiconductor tft substrate
WO2020244313A1 (en) Array substrate and preparation method thereof, display panel, and display device
CN102651343A (en) Manufacturing method of array substrate, array substrate and display device
WO2022193657A1 (en) Thin film transistor and manufacturing method therefor, display panel, and display device
WO2017219412A1 (en) Method for manufacturing top gate thin-film transistor
US10629746B2 (en) Array substrate and manufacturing method thereof
CN112397573B (en) Array substrate, preparation method thereof and display panel
TWI645512B (en) Thin film transistor substrate and manufacturing method thereof
CN111710609A (en) Doping method of indium gallium zinc oxide thin film transistor
US11289513B2 (en) Thin film transistor and method for fabricating the same, array substrate and display device
CN102593008B (en) A kind of preparation method of bottom gate self alignment zino oxide film transistor
CN112259611A (en) Oxide semiconductor thin film transistor and manufacturing method thereof
WO2019100492A1 (en) Back channel-etched tft substrate and preparation method therefor
US9917157B2 (en) Thin film transistor, array substrate, their manufacturing methods, and display device
CN107452810B (en) Metal oxide thin film transistor and preparation method thereof
WO2022120746A1 (en) Array substrate and manufacturing method therefor, and display panel
CN109616444B (en) TFT substrate manufacturing method and TFT substrate

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination